[clang] [clang-format] Stop crashing when formatting Verilog (PR #112043)

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https://github.com/sstwcw created https://github.com/llvm/llvm-project/pull/112043

The part of the code for parsing Verilog module instantiations dereferenced a pointer without checking for null pointer.  The pointer may be null if the input is not complete and a line starts with a comma.

>From 4bac5516b251f75ea105fcf79afbc1ca7b9e7d04 Mon Sep 17 00:00:00 2001
From: sstwcw <su3e8a96kzlver at posteo.net>
Date: Fri, 11 Oct 2024 18:03:00 +0000
Subject: [PATCH] [clang-format] Stop crashing when formatting Verilog

The part of the code for parsing Verilog module instantiations
dereferenced a pointer without checking for null pointer.  The pointer
may be null if the input is not complete and a line starts with a comma.
---
 clang/lib/Format/TokenAnnotator.cpp          | 3 ++-
 clang/unittests/Format/FormatTestVerilog.cpp | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
index 364d7e9855e8cf..f41cf3b32f74e2 100644
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -1551,7 +1551,8 @@ class AnnotatingParser {
           // Case D.
           if (Keywords.isVerilogIdentifier(*Prev) && PrevPrev->is(tok::comma)) {
             const FormatToken *PrevParen = PrevPrev->getPreviousNonComment();
-            if (PrevParen->is(tok::r_paren) && PrevParen->MatchingParen &&
+            if (PrevParen && PrevParen->is(tok::r_paren) &&
+                PrevParen->MatchingParen &&
                 PrevParen->MatchingParen->is(TT_VerilogInstancePortLParen)) {
               return true;
             }
diff --git a/clang/unittests/Format/FormatTestVerilog.cpp b/clang/unittests/Format/FormatTestVerilog.cpp
index fbaf289fbc4d6d..49d276fc78d81b 100644
--- a/clang/unittests/Format/FormatTestVerilog.cpp
+++ b/clang/unittests/Format/FormatTestVerilog.cpp
@@ -964,6 +964,7 @@ TEST_F(FormatTestVerilog, Instantiation) {
                "        .qbar(out1),\n"
                "        .clear(in1),\n"
                "        .preset(in2));");
+  verifyNoCrash(", ff1();");
   // With breaking between instance ports disabled.
   auto Style = getDefaultStyle();
   Style.VerilogBreakBetweenInstancePorts = false;