[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

[Craig Topper via cfe-commits]

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@@ -102,7 +102,7 @@ bool RISCVTargetInfo::validateAsmConstraint(
     return true;
   case 'v':
     // A vector register.
-    if (Name[1] == 'r' || Name[1] == 'm') {
+    if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') {
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topperc wrote:

This needs to be tested in clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

https://github.com/llvm/llvm-project/pull/111653