[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)
Jim Lin via cfe-commits
cfe-commits at lists.llvm.org
Thu Oct 10 19:48:14 PDT 2024
https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/111653
>From 80768f580d4ef6b9841b22ee5b287a87d9f25951 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 9 Oct 2024 11:37:46 +0800
Subject: [PATCH 1/2] [RISCV] Add support for inline asm constraint vd
It constrains vector registers excluding v0.
This patch also adds a testcase for constraints vr, vd and vm.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 15 ++++-
.../CodeGen/RISCV/inline-asm-v-constraint.ll | 66 +++++++++++++++++++
2 files changed, 80 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 463887b8b55e61..0c8fd324edd1cf 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20340,7 +20340,7 @@ RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
return C_Other;
}
} else {
- if (Constraint == "vr" || Constraint == "vm")
+ if (Constraint == "vr" || Constraint == "vd" || Constraint == "vm")
return C_RegisterClass;
}
return TargetLowering::getConstraintType(Constraint);
@@ -20388,6 +20388,19 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
return std::make_pair(0U, RC);
}
+ } else if (Constraint == "vd") {
+ for (const auto *RC :
+ {&RISCV::VRNoV0RegClass, &RISCV::VRM2NoV0RegClass,
+ &RISCV::VRM4NoV0RegClass, &RISCV::VRM8NoV0RegClass,
+ &RISCV::VRN2M1NoV0RegClass, &RISCV::VRN3M1NoV0RegClass,
+ &RISCV::VRN4M1NoV0RegClass, &RISCV::VRN5M1NoV0RegClass,
+ &RISCV::VRN6M1NoV0RegClass, &RISCV::VRN7M1NoV0RegClass,
+ &RISCV::VRN8M1NoV0RegClass, &RISCV::VRN2M2NoV0RegClass,
+ &RISCV::VRN3M2NoV0RegClass, &RISCV::VRN4M2NoV0RegClass,
+ &RISCV::VRN2M4NoV0RegClass}) {
+ if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
+ return std::make_pair(0U, RC);
+ }
} else if (Constraint == "vm") {
if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
return std::make_pair(0U, &RISCV::VMV0RegClass);
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll b/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll
new file mode 100644
index 00000000000000..c04e4fea7b2c29
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/inline-asm-v-constraint.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64I %s
+
+define <vscale x 1 x i8> @constraint_vr(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind {
+; RV32I-LABEL: constraint_vr:
+; RV32I: # %bb.0:
+; RV32I-NEXT: #APP
+; RV32I-NEXT: vadd.vv v8, v8, v9
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: constraint_vr:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: vadd.vv v8, v8, v9
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
+ %a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(
+ <vscale x 1 x i8> %0, <vscale x 1 x i8> %1)
+ ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @constraint_vd(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1) nounwind {
+; RV32I-LABEL: constraint_vd:
+; RV32I: # %bb.0:
+; RV32I-NEXT: #APP
+; RV32I-NEXT: vadd.vv v8, v8, v9
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: constraint_vd:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: vadd.vv v8, v8, v9
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
+ %a = tail call <vscale x 1 x i8> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(
+ <vscale x 1 x i8> %0, <vscale x 1 x i8> %1)
+ ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i1> @constraint_vm(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1) nounwind {
+; RV32I-LABEL: constraint_vm:
+; RV32I: # %bb.0:
+; RV32I-NEXT: vmv1r.v v9, v0
+; RV32I-NEXT: vmv1r.v v0, v8
+; RV32I-NEXT: #APP
+; RV32I-NEXT: vadd.vv v0, v9, v0
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: constraint_vm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: vmv1r.v v9, v0
+; RV64I-NEXT: vmv1r.v v0, v8
+; RV64I-NEXT: #APP
+; RV64I-NEXT: vadd.vv v0, v9, v0
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
+ %a = tail call <vscale x 1 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"(
+ <vscale x 1 x i1> %0, <vscale x 1 x i1> %1)
+ ret <vscale x 1 x i1> %a
+}
>From 0212fb8ba0e3ea07a7216434f73efc77afe08953 Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Fri, 11 Oct 2024 08:38:30 +0800
Subject: [PATCH 2/2] Add the change for vd in clang
---
clang/lib/Basic/Targets/RISCV.cpp | 2 +-
clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c | 8 ++++++++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 2a225820208c8c..870f0f38bc3057 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -102,7 +102,7 @@ bool RISCVTargetInfo::validateAsmConstraint(
return true;
case 'v':
// A vector register.
- if (Name[1] == 'r' || Name[1] == 'm') {
+ if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') {
Info.setAllowsRegister();
Name += 1;
return true;
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
index 59adc5c45521ab..879fb1238d83ab 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
@@ -29,6 +29,14 @@ vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) {
return ret;
}
+vint32m1_t test_vd(vint32m1_t a, vint32m1_t b) {
+// CHECK-LABEL: define{{.*}} @test_vd
+// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=^vd,^vd,^vd"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+ vint32m1_t ret;
+ asm volatile ("vadd.vv %0, %1, %2" : "=vd"(ret) : "vd"(a), "vd"(b));
+ return ret;
+}
+
vbool1_t test_vm(vbool1_t a, vbool1_t b) {
// CHECK-LABEL: define{{.*}} @test_vm
// CHECK: %0 = tail call <vscale x 64 x i1> asm sideeffect "vmand.mm $0, $1, $2", "=^vm,^vm,^vm"(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
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