[clang] [llvm] [AArch64] Introduce new armv9.6 features (PR #111677)

[Jonathan Thackray via cfe-commits]

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@@ -522,6 +522,39 @@ def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW", "FEAT_TLBIW",
 //  Armv9.6 Architecture Extensions
 //===----------------------------------------------------------------------===//
 
+def FeatureCMPBR : ExtensionWithMArch<"cmpbr", "CMPBR", "FEAT_CMPBR",
+  "Enable A64 base compare and branch instructions">;
+
+def FeatureF8F32MM: ExtensionWithMArch<"f8f32mm", "F8F32MM", "FEAT_F8F32MM",
+  "Enable FP8 to Single-Precision Matrix Multiplication", [FeatureFP8DOT4]>;
+
+def FeatureF8F16MM: ExtensionWithMArch<"f8f16mm", "F8F16MM", "FEAT_F8F16MM",
+  "Enable FP8 to Half-Precision Matrix Multiplication", [FeatureFP8DOT2, FeatureF8F32MM]>;
+
+def FeatureFPRCVT: ExtensionWithMArch<"fprcvt", "FPRCVT", "FEAT_FPRCVT",
+  "Enable A64 base convert instructions for SIMD&FP scalar register operands of"
+  " different input and output sizes", [FeatureFPARMv8]>;
+
+def FeatureLSFE : ExtensionWithMArch<"lsfe", "LSFE", "FEAT_LSFE",
+  "Enable A64 base Atomic floating-point in-memory instructions", [FeatureFPARMv8]>;
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jthackray wrote:

Can we mention "Large System Float Extension" so it's obvious what the extension stands for?

Perhaps "Enable Armv9.6-A Large System Float Extension (Atomic floating-point in-memory instructions)" ?

https://github.com/llvm/llvm-project/pull/111677