[clang] [clang][RISC-V] fixed fp calling convention for fpcc eligible structs for risc-v (PR #110690)

[Kamran Yousafzai via cfe-commits]

https://github.com/KamranYousafzai updated https://github.com/llvm/llvm-project/pull/110690

>From f1da56e337a4a2f0414fd600897addb0fa61b843 Mon Sep 17 00:00:00 2001
From: "muhammad.kamran4" <muhammad.kamran at esperantotech.com>
Date: Tue, 1 Oct 2024 17:21:21 +0200
Subject: [PATCH] fixed fp calling convention for fpcc eligible structs for
 risc-v

---
 clang/lib/CodeGen/Targets/RISCV.cpp          |  7 +++++
 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c | 28 ++++++++++++++++++++
 clang/test/CodeGen/RISCV/riscv64-abi.c       |  4 +--
 3 files changed, 37 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGen/RISCV/riscv-fpcc-struct.c

diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index fd72fe673b9b14..ba512f51e52b81 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -251,6 +251,13 @@ bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff,
         // bitwidth is XLen or less.
         if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
           QTy = getContext().getIntTypeForBitwidth(XLen, false);
+        // Trim type to alignment/bitwidth if that is possible
+        else if (getContext().getTypeSize(QTy) > BitWidth) {
+          bool IsSigned =
+              FD->getType().getTypePtr()->hasSignedIntegerRepresentation();
+          unsigned Bits = std::max(8U, (unsigned)llvm::PowerOf2Ceil(BitWidth));
+          QTy = getContext().getIntTypeForBitwidth(Bits, IsSigned);
+        }
         if (BitWidth == 0) {
           ZeroWidthBitFieldCount++;
           continue;
diff --git a/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
new file mode 100644
index 00000000000000..a315b409da613a
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-fpcc-struct.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -emit-llvm %s -o - \
+// RUN:   | FileCheck %s
+
+
+struct __attribute__((packed, aligned(1))) S {
+   const float  f0;
+   unsigned f1 : 1;
+};
+
+// CHECK-LABEL: define dso_local signext i32 @func(
+// CHECK-SAME: float [[TMP0:%.*]], i8 [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:    [[ARG:%.*]] = alloca [[STRUCT_S:%.*]], align 1
+// CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr [[ARG]], i32 0, i32 0
+// CHECK-NEXT:    store float [[TMP0]], ptr [[TMP2]], align 1
+// CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw { float, i8 }, ptr [[ARG]], i32 0, i32 1
+// CHECK-NEXT:    store i8 [[TMP1]], ptr [[TMP3]], align 1
+// CHECK-NEXT:    [[F1:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[ARG]], i32 0, i32 1
+// CHECK-NEXT:    [[BF_LOAD:%.*]] = load i8, ptr [[F1]], align 1
+// CHECK-NEXT:    [[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// CHECK-NEXT:    [[BF_CAST:%.*]] = zext i8 [[BF_CLEAR]] to i32
+// CHECK-NEXT:    ret i32 [[BF_CAST]]
+//
+unsigned  func(struct S  arg)
+{
+    return arg.f1;
+}
diff --git a/clang/test/CodeGen/RISCV/riscv64-abi.c b/clang/test/CodeGen/RISCV/riscv64-abi.c
index 021565238904e4..64c831361cb8e0 100644
--- a/clang/test/CodeGen/RISCV/riscv64-abi.c
+++ b/clang/test/CodeGen/RISCV/riscv64-abi.c
@@ -1710,7 +1710,7 @@ struct float16_int64_s f_ret_float16_int64_s(void) {
 // LP64:  entry:
 //
 // LP64F-LP64D-LABEL: define dso_local void @f_float16_int64bf_s_arg
-// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i64 [[TMP1:%.*]]) #[[ATTR0]] {
+// LP64F-LP64D-SAME: (half [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //
 void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
@@ -1719,7 +1719,7 @@ void f_float16_int64bf_s_arg(struct float16_int64bf_s a) {}
 // LP64-SAME: () #[[ATTR0]] {
 // LP64:  entry:
 //
-// LP64F-LP64D-LABEL: define dso_local <{ half, i64 }> @f_ret_float16_int64bf_s
+// LP64F-LP64D-LABEL: define dso_local <{ half, i32 }> @f_ret_float16_int64bf_s
 // LP64F-LP64D-SAME: () #[[ATTR0]] {
 // LP64F-LP64D:  entry:
 //