[clang] [llvm] [AArch64] Split FeatureAES to FEAT_AES and FEAT_PMULL. (PR #110816)
Alexandros Lamprineas via cfe-commits
cfe-commits at lists.llvm.org
Wed Oct 2 03:14:16 PDT 2024
https://github.com/labrinea created https://github.com/llvm/llvm-project/pull/110816
Currently in LLVM FeatureAES models both FEAT_AES and FEAT_PMULL lumped together. Similarly FeatureSVE2AES means FEAT_SVE_AES plus FEAT_SVE_PMULL128. However the architecture does not mandate that both need to be implemented at the same time. Splitting them will allow Function Multiversioning to enable backend support for 'aes' and 'sve2-aes'. I have added an override for the user visible names of the new features to preserve the old semantics for backwards compatibility with command line, target attribute and assembler directives.
>From 75cc8dde054af252435f770a52bf18117cec2a57 Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: Wed, 2 Oct 2024 10:53:38 +0100
Subject: [PATCH] [AArch64] Split FeatureAES to FEAT_AES and FEAT_PMULL.
Currently in LLVM FeatureAES models both FEAT_AES and FEAT_PMULL lumped together.
Similarly FeatureSVE2AES means FEAT_SVE_AES plus FEAT_SVE_PMULL128. However the
architecture does not mandate that both need to be implemented at the same time.
Splitting them will allow Function Multiversioning to enable backend support for
'aes' and 'sve2-aes'. I have added an override for the user visible names of the
new features to preserve the old semantics for backwards compatibility with
command line, target attribute and assembler directives.
---
clang/lib/Basic/Targets/AArch64.cpp | 4 +-
clang/test/CodeGen/aarch64-fmv-dependencies.c | 13 ++-
clang/test/CodeGen/aarch64-targetattr.c | 12 +-
clang/test/CodeGen/arm64_crypto.c | 2 +-
.../test/CodeGen/attr-target-clones-aarch64.c | 8 +-
clang/test/CodeGen/attr-target-version.c | 110 +++++++++---------
clang/test/CodeGen/neon-crypto.c | 4 +-
clang/test/CodeGenCXX/attr-target-version.cpp | 2 +-
clang/test/Driver/aarch64-aes.c | 9 ++
clang/test/Driver/aarch64-sve2-aes.c | 9 ++
.../print-enabled-extensions/aarch64-a64fx.c | 3 +-
.../aarch64-ampere1.c | 3 +-
.../aarch64-ampere1a.c | 3 +-
.../aarch64-ampere1b.c | 3 +-
.../aarch64-apple-a10.c | 3 +-
.../aarch64-apple-a11.c | 3 +-
.../aarch64-apple-a12.c | 3 +-
.../aarch64-apple-a13.c | 3 +-
.../aarch64-apple-a14.c | 3 +-
.../aarch64-apple-a15.c | 3 +-
.../aarch64-apple-a16.c | 3 +-
.../aarch64-apple-a17.c | 3 +-
.../aarch64-apple-a7.c | 3 +-
.../aarch64-apple-m4.c | 3 +-
.../print-enabled-extensions/aarch64-carmel.c | 3 +-
.../aarch64-cortex-a34.c | 3 +-
.../aarch64-cortex-a35.c | 3 +-
.../aarch64-cortex-a53.c | 3 +-
.../aarch64-cortex-a55.c | 3 +-
.../aarch64-cortex-a57.c | 3 +-
.../aarch64-cortex-a65.c | 3 +-
.../aarch64-cortex-a65ae.c | 3 +-
.../aarch64-cortex-a72.c | 3 +-
.../aarch64-cortex-a73.c | 3 +-
.../aarch64-cortex-a75.c | 3 +-
.../aarch64-cortex-a76.c | 3 +-
.../aarch64-cortex-a76ae.c | 3 +-
.../aarch64-cortex-a77.c | 3 +-
.../aarch64-cortex-a78.c | 3 +-
.../aarch64-cortex-a78ae.c | 3 +-
.../aarch64-cortex-a78c.c | 3 +-
.../aarch64-cortex-x1.c | 3 +-
.../aarch64-cortex-x1c.c | 3 +-
.../aarch64-exynos-m3.c | 3 +-
.../aarch64-exynos-m4.c | 3 +-
.../aarch64-exynos-m5.c | 3 +-
.../print-enabled-extensions/aarch64-falkor.c | 3 +-
.../print-enabled-extensions/aarch64-kryo.c | 3 +-
.../aarch64-neoverse-512tvb.c | 3 +-
.../aarch64-neoverse-e1.c | 3 +-
.../aarch64-neoverse-n1.c | 3 +-
.../aarch64-neoverse-v1.c | 3 +-
.../aarch64-oryon-1.c | 3 +-
.../aarch64-saphira.c | 3 +-
.../aarch64-thunderx.c | 3 +-
.../aarch64-thunderx2t99.c | 3 +-
.../aarch64-thunderx3t110.c | 3 +-
.../aarch64-thunderxt81.c | 3 +-
.../aarch64-thunderxt83.c | 3 +-
.../aarch64-thunderxt88.c | 3 +-
.../print-enabled-extensions/aarch64-tsv110.c | 3 +-
.../print-supported-extensions-aarch64.c | 4 +-
.../Preprocessor/aarch64-target-features.c | 56 ++++-----
llvm/lib/Target/AArch64/AArch64.td | 2 +-
llvm/lib/Target/AArch64/AArch64FMV.td | 8 +-
llvm/lib/Target/AArch64/AArch64Features.td | 19 ++-
.../lib/Target/AArch64/AArch64InstrFormats.td | 2 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 4 +
llvm/lib/Target/AArch64/AArch64Processors.td | 80 ++++++-------
.../lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 +-
.../AArch64/AsmParser/AArch64AsmParser.cpp | 4 +-
llvm/lib/TargetParser/AArch64TargetParser.cpp | 13 ++-
llvm/test/CodeGen/AArch64/aarch64-pmull2.ll | 2 +-
.../test/CodeGen/AArch64/arm64-neon-3vdiff.ll | 2 +-
llvm/test/CodeGen/AArch64/arm64-vmul.ll | 2 +-
.../CodeGen/AArch64/neon-vmull-high-p64.ll | 2 +-
llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll | 2 +-
...e2-intrinsics-polynomial-arithmetic-128.ll | 2 +-
.../MC/AArch64/SVE2/pmullb-128-diagnostics.s | 2 +-
llvm/test/MC/AArch64/SVE2/pmullb-128.s | 10 +-
.../MC/AArch64/SVE2/pmullt-128-diagnostics.s | 2 +-
llvm/test/MC/AArch64/SVE2/pmullt-128.s | 10 +-
llvm/test/MC/AArch64/arm64-diagno-predicate.s | 2 +-
.../directive-arch_extension-negative.s | 19 ++-
.../AArch64/Cortex/A510-sve-instructions.s | 2 +-
.../AArch64/Neoverse/N2-sve-instructions.s | 2 +-
.../AArch64/Neoverse/N3-sve-instructions.s | 2 +-
.../AArch64/Neoverse/V2-sve-instructions.s | 2 +-
.../TargetParser/TargetParserTest.cpp | 8 +-
89 files changed, 357 insertions(+), 238 deletions(-)
create mode 100644 clang/test/Driver/aarch64-aes.c
create mode 100644 clang/test/Driver/aarch64-sve2-aes.c
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 5f5dfcb722f9d4..9b0f744ac543bc 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -853,7 +853,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasSVE2 = true;
HasSVE2p1 = true;
}
- if (Feature == "+sve2-aes") {
+ if (Feature == "+sve2-aes" || Feature == "+sve2-pmull128") {
FPU |= NeonMode;
FPU |= SveMode;
HasFullFP16 = true;
@@ -963,7 +963,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasCRC = true;
if (Feature == "+rcpc")
HasRCPC = true;
- if (Feature == "+aes") {
+ if (Feature == "+aes" || Feature == "+pmull") {
FPU |= NeonMode;
HasAES = true;
}
diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c
index 681f7e82634fa8..12d7ed34eaeaa7 100644
--- a/clang/test/CodeGen/aarch64-fmv-dependencies.c
+++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c
@@ -3,7 +3,7 @@
// RUN: %clang --target=aarch64-linux-gnu --rtlib=compiler-rt -emit-llvm -S -o - %s | FileCheck %s
-// CHECK: define dso_local i32 @fmv._Maes() #[[ATTR0:[0-9]+]] {
+// CHECK: define dso_local i32 @fmv._Maes() #[[aes:[0-9]+]] {
__attribute__((target_version("aes"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16_ebf16:[0-9]+]] {
@@ -156,13 +156,13 @@ __attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] {
__attribute__((target_version("sve2"))) int fmv(void) { return 0; }
-// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes_sve2_pmull128:[0-9]+]] {
+// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes:[0-9]+]] {
__attribute__((target_version("sve2-aes"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Msve2-bitperm() #[[sve2_bitperm:[0-9]+]] {
__attribute__((target_version("sve2-bitperm"))) int fmv(void) { return 0; }
-// CHECK: define dso_local i32 @fmv._Msve2-pmull128() #[[sve2_aes_sve2_pmull128:[0-9]+]] {
+// CHECK: define dso_local i32 @fmv._Msve2-pmull128() #[[sve2_pmull128:[0-9]+]] {
__attribute__((target_version("sve2-pmull128"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Msve2-sha3() #[[sve2_sha3:[0-9]+]] {
@@ -183,7 +183,7 @@ int caller() {
return fmv();
}
-// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a"
@@ -205,7 +205,7 @@ int caller() {
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+pmull,+v8a"
// CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"
// CHECK: attributes #[[rcpc]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a"
// CHECK: attributes #[[rcpc3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc3,+v8a"
@@ -224,8 +224,9 @@ int caller() {
// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a"
// CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a"
-// CHECK: attributes #[[sve2_aes_sve2_pmull128]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
+// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a"
// CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a"
+// CHECK: attributes #[[sve2_pmull128]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+pmull,+sve,+sve2,+sve2-aes,+sve2-pmull128,+v8a"
// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sha3,+v8a"
// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sm4,+v8a"
// CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt"
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 1bc78a6e1f8c0f..ce77c6145156b0 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -208,17 +208,17 @@ void applem4() {}
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
-// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+pmull,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
-// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
+// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+pmull,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" }
+// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+pmull,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" }
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" }
-// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+pmull,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+pmull,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
-// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
+// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+pmull,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
diff --git a/clang/test/CodeGen/arm64_crypto.c b/clang/test/CodeGen/arm64_crypto.c
index da6597be85bc80..5e6d59c490294f 100644
--- a/clang/test/CodeGen/arm64_crypto.c
+++ b/clang/test/CodeGen/arm64_crypto.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-feature +neon -target-feature +aes -target-feature +sha2 -ffreestanding -Os -S -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-feature +neon -target-feature +aes -target-feature +pmull -target-feature +sha2 -ffreestanding -Os -S -o - %s | FileCheck %s
// REQUIRES: aarch64-registered-target
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 274e05de594b8e..ba3ffd5749ea68 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -824,7 +824,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI-NEXT: ret ptr @ftc_inline3.default
//
//.
-// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" }
+// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+fp-armv8,+lse,+neon" }
// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" }
// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" }
// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" }
@@ -837,13 +837,13 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+complxnum,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-bitperm" }
// CHECK: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rand" }
// CHECK: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+predres,+rcpc" }
-// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
+// CHECK: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
// CHECK: attributes #[[ATTR14:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sb,+sve" }
//.
// CHECK-NOFMV: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
//.
-// CHECK-MTE-BTI: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+lse,+mte,+neon" }
+// CHECK-MTE-BTI: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+bti,+fp-armv8,+lse,+mte,+neon" }
// CHECK-MTE-BTI: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2" }
// CHECK-MTE-BTI: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+sha2" }
// CHECK-MTE-BTI: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon" }
@@ -853,7 +853,7 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+complxnum,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-bitperm" }
// CHECK-MTE-BTI: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+rand" }
// CHECK-MTE-BTI: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte,+predres,+rcpc" }
-// CHECK-MTE-BTI: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
+// CHECK-MTE-BTI: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
// CHECK-MTE-BTI: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sb,+sve" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c
index 228435a0494c3e..f3314bb5c32173 100644
--- a/clang/test/CodeGen/attr-target-version.c
+++ b/clang/test/CodeGen/attr-target-version.c
@@ -242,14 +242,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp
-// CHECK-SAME: () #[[ATTR5]] {
+// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd
-// CHECK-SAME: () #[[ATTR5]] {
+// CHECK-SAME: () #[[ATTR12]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 2
//
@@ -263,7 +263,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd
-// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 4
//
@@ -354,14 +354,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops
-// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod
-// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
//
@@ -375,7 +375,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve
-// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
//
@@ -389,7 +389,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16
-// CHECK-SAME: () #[[ATTR12]] {
+// CHECK-SAME: () #[[ATTR13]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
//
@@ -410,14 +410,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse
-// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm
-// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR19:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
//
@@ -431,14 +431,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt
-// CHECK-SAME: () #[[ATTR20:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR21:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm
-// CHECK-SAME: () #[[ATTR18]] {
+// CHECK-SAME: () #[[ATTR19]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 2
//
@@ -618,7 +618,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb
-// CHECK-SAME: () #[[ATTR22:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 0
//
@@ -660,91 +660,91 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha2
-// CHECK-SAME: () #[[ATTR23:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR24:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 1
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme
-// CHECK-SAME: () #[[ATTR24:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR25:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 2
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3
-// CHECK-SAME: () #[[ATTR25:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR26:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 12
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16
-// CHECK-SAME: () #[[ATTR26:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR27:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 8
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2
-// CHECK-SAME: () #[[ATTR27:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 6
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt
-// CHECK-SAME: () #[[ATTR28:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR29:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 7
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc
-// CHECK-SAME: () #[[ATTR29:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR30:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 3
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16
-// CHECK-SAME: () #[[ATTR30:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR31:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 4
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3
-// CHECK-SAME: () #[[ATTR31:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR32:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 5
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-bitpermMsve2-pmull128
-// CHECK-SAME: () #[[ATTR32:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR33:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 9
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag2Msve2-sm4
-// CHECK-SAME: () #[[ATTR33:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR34:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 10
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3MmopsMrcpc3
-// CHECK-SAME: () #[[ATTR34:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR35:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 11
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod
-// CHECK-SAME: () #[[ATTR15]] {
+// CHECK-SAME: () #[[ATTR36:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 13
//
@@ -758,14 +758,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
-// CHECK-SAME: () #[[ATTR35:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR37:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 15
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm
-// CHECK-SAME: () #[[ATTR36:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR38:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 16
//
@@ -1117,39 +1117,41 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+sha2" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+ls64,+neon" }
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon" }
-// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
+// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+fp-armv8,+neon" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+ls64" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+sme,+sme2" }
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+ls64,+neon" }
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp" }
-// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
-// CHECK: attributes #[[ATTR13:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops" }
-// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+neon" }
-// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
-// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse" }
-// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm" }
-// CHECK: attributes #[[ATTR19:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon" }
-// CHECK: attributes #[[ATTR20]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon" }
-// CHECK: attributes #[[ATTR21:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
-// CHECK: attributes #[[ATTR22]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb" }
-// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+sha2,+sve" }
-// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fp-armv8,+fullfp16,+neon,+rdm,+sme" }
-// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fp-armv8,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve" }
-// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fp-armv8,+fullfp16,+neon,+sve" }
-// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,+rcpc" }
-// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+fp-armv8,+jsconv,+neon" }
-// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,+rcpc" }
-// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+sve" }
-// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3" }
-// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm" }
-// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4" }
-// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+rcpc,+rcpc3" }
-// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sm4" }
-// CHECK: attributes #[[ATTR36]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+rdm" }
-// CHECK: attributes #[[ATTR37:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm" }
+// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
+// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
+// CHECK: attributes #[[ATTR14:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops" }
+// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+neon" }
+// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
+// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse" }
+// CHECK: attributes #[[ATTR19]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm" }
+// CHECK: attributes #[[ATTR20:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon" }
+// CHECK: attributes #[[ATTR21]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+jsconv,+neon" }
+// CHECK: attributes #[[ATTR22:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ls64" }
+// CHECK: attributes #[[ATTR23]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+sb" }
+// CHECK: attributes #[[ATTR24]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+f64mm,+fp-armv8,+fullfp16,+neon,+pmull,+sha2,+sve" }
+// CHECK: attributes #[[ATTR25]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+fp-armv8,+fullfp16,+neon,+rdm,+sme" }
+// CHECK: attributes #[[ATTR26]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+f32mm,+fp-armv8,+fullfp16,+i8mm,+neon,+sha2,+sha3,+sve" }
+// CHECK: attributes #[[ATTR27]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+dit,+fp-armv8,+fullfp16,+neon,+sve" }
+// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccpp,+rcpc" }
+// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ccdp,+ccpp,+fp-armv8,+jsconv,+neon" }
+// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fptoint,+rcpc" }
+// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+sve" }
+// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3" }
+// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+pmull,+sve,+sve2,+sve2-aes,+sve2-bitperm,+sve2-pmull128" }
+// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4" }
+// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+rcpc,+rcpc3" }
+// CHECK: attributes #[[ATTR36]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+dotprod,+fp-armv8,+neon" }
+// CHECK: attributes #[[ATTR37]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sm4" }
+// CHECK: attributes #[[ATTR38]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+rdm" }
+// CHECK: attributes #[[ATTR39:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm" }
//.
// CHECK-NOFMV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
diff --git a/clang/test/CodeGen/neon-crypto.c b/clang/test/CodeGen/neon-crypto.c
index 4b46783d930f4c..d18f2ffd69c3a5 100644
--- a/clang/test/CodeGen/neon-crypto.c
+++ b/clang/test/CodeGen/neon-crypto.c
@@ -1,9 +1,9 @@
// RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-feature +neon \
-// RUN: -target-feature +sha2 -target-feature +aes \
+// RUN: -target-feature +sha2 -target-feature +aes -target-feature +pmull \
// RUN: -target-cpu cortex-a57 -emit-llvm -O1 -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
-// RUN: -target-feature +sha2 -target-feature +aes \
+// RUN: -target-feature +sha2 -target-feature +aes -target-feature +pmull \
// RUN: -emit-llvm -O1 -o - %s | FileCheck %s
// RUN: not %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
// RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
diff --git a/clang/test/CodeGenCXX/attr-target-version.cpp b/clang/test/CodeGenCXX/attr-target-version.cpp
index 6661abead20c6d..eb713933a866ae 100644
--- a/clang/test/CodeGenCXX/attr-target-version.cpp
+++ b/clang/test/CodeGenCXX/attr-target-version.cpp
@@ -329,7 +329,7 @@ int bar() {
// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
// CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+neon" }
// CHECK: attributes #[[ATTR5]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops" }
-// CHECK: attributes #[[ATTR6]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
+// CHECK: attributes #[[ATTR6]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+aes,+fp-armv8,+neon" }
// CHECK: attributes #[[ATTR7]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
// CHECK: attributes #[[ATTR8]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
// CHECK: attributes #[[ATTR9]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+lse" }
diff --git a/clang/test/Driver/aarch64-aes.c b/clang/test/Driver/aarch64-aes.c
new file mode 100644
index 00000000000000..5c32ce42858469
--- /dev/null
+++ b/clang/test/Driver/aarch64-aes.c
@@ -0,0 +1,9 @@
+// Test that +aes enables both FEAT_AES and FEAT_PMULL.
+// RUN: %clang -### --target=aarch64-linux-gnu -march=armv8-a+aes %s 2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+aes"
+// CHECK: "-target-feature" "+pmull"
+
+// Test that +noaes disables both FEAT_AES and FEAT_PMULL.
+// RUN: %clang -### --target=aarch64-linux-gnu -march=armv8-a+aes+noaes %s 2>&1 | FileCheck %s --check-prefix=NOAES
+// NOAES: "-target-feature" "-aes"
+// NOAES: "-target-feature" "-pmull"
diff --git a/clang/test/Driver/aarch64-sve2-aes.c b/clang/test/Driver/aarch64-sve2-aes.c
new file mode 100644
index 00000000000000..a5c1ea1a7e7464
--- /dev/null
+++ b/clang/test/Driver/aarch64-sve2-aes.c
@@ -0,0 +1,9 @@
+// Test that +sve2-aes enables both FEAT_SVE_AES and FEAT_SVE_PMULL128.
+// RUN: %clang -### --target=aarch64-linux-gnu -march=armv8-a+sve2-aes %s 2>&1 | FileCheck %s
+// CHECK: "-target-feature" "+sve2-aes"
+// CHECK: "-target-feature" "+sve2-pmull128"
+
+// Test that +nosve2-aes disables both FEAT_SVE_AES and FEAT_SVE_PMULL128.
+// RUN: %clang -### --target=aarch64-linux-gnu -march=armv8-a+sve2-aes+nosve2-aes %s 2>&1 | FileCheck %s --check-prefix=NOSVE2-AES
+// NOSVE2-AES: "-target-feature" "-sve2-aes"
+// NOSVE2-AES: "-target-feature" "-sve2-pmull128"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c b/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
index 269aec5ad08451..1c7393c94c3a22 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-a64fx.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -15,6 +15,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
index bc5edbc77c9b9c..5182ce3a4e2940 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -38,6 +38,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
index 3c20cff28821e7..899add0c061e43 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -39,6 +39,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
index 444ac4526200fe..6456a67c9bbb65 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -41,6 +41,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
index aa8cc7bd3badde..8448ccd2b5bc0b 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a10.c
@@ -4,12 +4,13 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
index d219981e6be3c8..7840e6cfa0b399 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a11.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -14,6 +14,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
index fcc8b674df33f4..b175adc5d72763 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a12.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -18,6 +18,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
index dae95b1297e145..ee1880e69c1afb 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a13.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
@@ -27,6 +27,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
index 8ddcddede4110d..ced9a093f26515 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a14.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
@@ -31,6 +31,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
index b3f0acefd1e2d4..3a3920adfd4222 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a15.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -38,6 +38,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
index 6f417c1592b06c..b08eb221344443 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a16.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -39,6 +39,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
index 39e5b70c25d886..fb06ade84212d6 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a17.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -39,6 +39,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a7.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a7.c
index 084a124eb7e19f..d90ee1a6a308b4 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-a7.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-a7.c
@@ -4,8 +4,9 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
index 29d66dc8826a77..aedbdc17ecf50e 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -39,6 +39,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-carmel.c b/clang/test/Driver/print-enabled-extensions/aarch64-carmel.c
index e89a22224267d3..62fc44ed4c152a 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-carmel.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-carmel.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -14,6 +14,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a34.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a34.c
index 0b052ba69f5cd7..13e6025302d9db 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a34.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a34.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a35.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a35.c
index e8a152a7e002b5..39c582b30801b2 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a35.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a35.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a53.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a53.c
index 5bd912d7731e1f..decb145aeb0da7 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a53.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a53.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a55.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a55.c
index fcc70e6e4e1d70..ea523aea70c564 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a55.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a55.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a57.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a57.c
index 7c63100afb0346..0ad3c1c2115e71 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a57.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a57.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65.c
index e3b32cbf001e6b..e057c2be9817f4 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65ae.c
index 0c9efe67e6d00b..abadd1188880c1 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a65ae.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a72.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a72.c
index e1ba34caf7a7e8..672e0c2b1c353b 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a72.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a72.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a73.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a73.c
index 811bb1a3fab336..756d550346e1b7 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a73.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a73.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a75.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a75.c
index a1229645064704..09ae27719fb4c7 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a75.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a75.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76.c
index e6174de41b2f2c..dfcaa54776a6ce 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76ae.c
index 690c2a56e63c7a..f82d7f9191fce2 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a76ae.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a77.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a77.c
index dccdf6aa50ebe7..9c7474515dbc1f 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a77.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a77.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78.c
index 3e35d78403d01c..7cf0c7b01bdcde 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78ae.c
index 51e6c87e4a2962..ec3ee318de12ec 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78ae.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78c.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78c.c
index 42eb5fb97611d1..7cc09923b3e5d0 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78c.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a78c.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -18,6 +18,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1.c
index 19acf4653e0b99..cc6a492b6d8360 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1c.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1c.c
index 5eaf85aa964c13..12819020fd3934 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1c.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x1c.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -20,6 +20,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m3.c b/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m3.c
index 0e75f536441096..7b5dd7bbb47bef 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m3.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m4.c b/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m4.c
index 8419ec67bb1466..ca7bc1c3764105 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m4.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m4.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -15,6 +15,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m5.c b/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m5.c
index 7dd8318306d70a..d4b99cc7556b31 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m5.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-exynos-m5.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -15,6 +15,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-falkor.c b/clang/test/Driver/print-enabled-extensions/aarch64-falkor.c
index 8d1c37f3501d6f..0b2d43d1b45a37 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-falkor.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-falkor.c
@@ -4,10 +4,11 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-kryo.c b/clang/test/Driver/print-enabled-extensions/aarch64-kryo.c
index 4b6211a9a02984..240ef86c4df4f0 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-kryo.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-kryo.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
index 4f890a2e4b71ff..9cee4b10072a27 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-512tvb.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
@@ -31,6 +31,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-e1.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-e1.c
index 67fe95700ed8d0..bf8ee3e34e825d 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-e1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-e1.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n1.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n1.c
index d4d2310a2a25c8..cd4d6cf4c0d5fc 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n1.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -16,6 +16,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v1.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v1.c
index c6e32f28ee0fd6..c21da68fe06566 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v1.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
@@ -31,6 +31,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c b/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c
index a40b9ae6563538..133f9a3f90a14f 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-oryon-1.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
@@ -38,6 +38,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-saphira.c b/clang/test/Driver/print-enabled-extensions/aarch64-saphira.c
index 7bae4ac1346b2c..9073ffe423f444 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-saphira.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-saphira.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
@@ -26,6 +26,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-thunderx.c b/clang/test/Driver/print-enabled-extensions/aarch64-thunderx.c
index 2a7eb7486c2829..960ff0acbc2b38 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-thunderx.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-thunderx.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-thunderx2t99.c b/clang/test/Driver/print-enabled-extensions/aarch64-thunderx2t99.c
index e8a4d860e8f1f7..9f62f7885a8346 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-thunderx2t99.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-thunderx2t99.c
@@ -4,13 +4,14 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-thunderx3t110.c b/clang/test/Driver/print-enabled-extensions/aarch64-thunderx3t110.c
index 141251eb316e54..b208fef1789bd5 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-thunderx3t110.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-thunderx3t110.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
@@ -18,6 +18,7 @@
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt81.c b/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt81.c
index 48182209bf9c32..c088483b7667d7 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt81.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt81.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt83.c b/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt83.c
index 877c2a1bd243d4..a0d6895319a2fd 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt83.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt83.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt88.c b/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt88.c
index 91486b9da0e24a..c06d537fa503bc 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt88.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-thunderxt88.c
@@ -4,9 +4,10 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-tsv110.c b/clang/test/Driver/print-enabled-extensions/aarch64-tsv110.c
index 632a9f1d3d551b..340e192fe2d6cb 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-tsv110.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-tsv110.c
@@ -4,7 +4,7 @@
// CHECK: Extensions enabled for the given AArch64 target
// CHECK-EMPTY:
// CHECK-NEXT: Architecture Feature(s) Description
-// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
+// CHECK-NEXT: FEAT_AES Enable AES support
// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
@@ -18,6 +18,7 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PMULL Enable PMULL support
// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index e6247307c7219f..427c14d533bdb9 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -4,7 +4,6 @@
// CHECK: All available -march extensions for AArch64
// CHECK-EMPTY:
// CHECK-NEXT: Name Architecture Feature(s) Description
-// CHECK-NEXT: aes FEAT_AES, FEAT_PMULL Enable AES support
// CHECK-NEXT: bf16 FEAT_BF16 Enable BFloat16 Extension
// CHECK-NEXT: brbe FEAT_BRBE Enable Branch Record Buffer Extension
// CHECK-NEXT: bti FEAT_BTI Enable Branch Target Identification
@@ -42,6 +41,7 @@
// CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
// CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
// CHECK-NEXT: pmuv3 FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: aes FEAT_PMULL Enable PMULL support
// CHECK-NEXT: predres FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: rng FEAT_RNG Enable Random Number generation instructions
// CHECK-NEXT: ras FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
@@ -73,8 +73,8 @@
// CHECK-NEXT: sve FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: sve-b16b16 FEAT_SVE_B16B16 Enable SVE2 non-widening and SME2 Z-targeting non-widening BFloat16 instructions
// CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
-// CHECK-NEXT: sve2-aes FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable AES SVE2 instructions
// CHECK-NEXT: sve2-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: sve2-aes FEAT_SVE_PMULL128 Enable PMULL128 SVE2 instructions
// CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
// CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions
// CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions
diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c
index bcc0640c55e35a..321139cbc9c0e5 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -323,37 +323,37 @@
// RUN: %clang -target aarch64 -mcpu=thunderx2t99 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-THUNDERX2T99 %s
// RUN: %clang -target aarch64 -mcpu=a64fx -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A64FX %s
// RUN: %clang -target aarch64 -mcpu=carmel -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CARMEL %s
-// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" "-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+vh"
-// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3"
-// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A7: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A10: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lor" "-target-feature" "+neon" "-target-feature" "+pan" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+vh"
+// CHECK-MCPU-APPLE-A11: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"{{.*}}"-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A12: "-cc1"{{.*}} "-triple" "aarch64"{{.*}} "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2"
+// CHECK-MCPU-A34: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-APPLE-A13: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sha3"
+// CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+flagm" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+ssbs"
-// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
-// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2"
-// CHECK-MCPU-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+rdm" "-target-feature" "+sha2
-// CHECK-MCPU-A64FX: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sve"
-// CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
+// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
+// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+sha2"
+// CHECK-MCPU-THUNDERX2T99: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pmull" "-target-feature" "+rdm" "-target-feature" "+sha2
+// CHECK-MCPU-A64FX: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" "-target-feature" "+sve"
+// CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2"
// RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
-// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+altnzcv" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fptoint" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+specrestrict" "-target-feature" "+ssbs"
+// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+altnzcv" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fptoint" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+specrestrict" "-target-feature" "+ssbs"
// RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s
-// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2"
+// CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+pmull" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2"
// RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
// RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
// RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto -mabi=aapcs-soft -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
// RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto+nofp+nosimd+nocrc+nocrypto -mabi=aapcs-soft -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
// RUN: %clang -target aarch64 -march=armv8-a+nosimd -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-3 %s
-// CHECK-MARCH-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+sha2"
+// CHECK-MARCH-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+pmull" "-target-feature" "+sha2"
// CHECK-MARCH-2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-fp-armv8"{{.*}} "-target-feature" "-neon"
// CHECK-MARCH-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-neon"
@@ -379,7 +379,7 @@
// Check +aes:
//
// RUN: %clang -target aarch64 -march=armv8.3a+aes -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-AES %s
-// CHECK-AES: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.{{.}}a"{{.*}} "-target-feature" "+aes"
+// CHECK-AES: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.{{.}}a"{{.*}} "-target-feature" "+aes" {{.*}} "-target-feature" "+pmull"
//
// Check -sm4:
//
@@ -412,7 +412,7 @@
// RUN: %clang -target aarch64 -march=armv8.2a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO83 %s
// RUN: %clang -target aarch64 -march=armv8.3a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO83 %s
// RUN: %clang -target aarch64 -march=armv8a+crypto+nocrypto+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO83 %s
-// CHECK-CRYPTO83: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes"{{.*}} "-target-feature" "+crypto"{{.*}} "-target-feature" "+sha2"
+// CHECK-CRYPTO83: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+aes"{{.*}} "-target-feature" "+crypto"{{.*}} "-target-feature" "+pmull"{{.*}} "-target-feature" "+sha2"
//
// Check -crypto:
//
@@ -434,7 +434,7 @@
// Check -crypto +sha2 +aes:
//
// RUN: %clang -target aarch64 -march=armv8.1a+nocrypto+sha2+aes -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO83-SHA2-AES %s
-// CHECK-NOCRYPTO83-SHA2-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+sha2"
+// CHECK-NOCRYPTO83-SHA2-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+pmull"{{.*}} "-target-feature" "+sha2"
//
//
// Arch >= ARMv8.4: crypto = sm4 + sha3 + sha2 + aes
@@ -446,7 +446,7 @@
// RUN: %clang -target aarch64 -march=armv8.5a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO8_4567 %s
// RUN: %clang -target aarch64 -march=armv8.6a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO8_4567 %s
// RUN: %clang -target aarch64 -march=armv8.7a+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO8_4567 %s
-// CHECK-CRYPTO8_4567: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.{{[4567]}}a"{{.*}} "-target-feature" "+aes"{{.*}} "-target-feature" "+crypto"{{.*}} "-target-feature" "+sha2"{{.*}} "-target-feature" "+sha3"{{.*}} "-target-feature" "+sm4"
+// CHECK-CRYPTO8_4567: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.{{[4567]}}a"{{.*}} "-target-feature" "+aes"{{.*}} "-target-feature" "+crypto"{{.*}} "-target-feature" "+pmull"{{.*}} "-target-feature" "+sha2"{{.*}} "-target-feature" "+sha3"{{.*}} "-target-feature" "+sm4"
//
// Check -crypto:
//
@@ -456,7 +456,7 @@
// Check +crypto -sm4 -sha3:
//
// RUN: %clang -target aarch64 -march=armv8.4a+crypto+sm4+nosm4+sha3+nosha3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CRYPTO84-NOSMSHA %s
-// CHECK-CRYPTO84-NOSMSHA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.4a"{{.*}} "-target-feature" "+aes"{{.*}} "-target-feature" "+crypto"{{.*}} "-target-feature" "+sha2"{{.*}} "-target-feature" "-sha3"{{.*}} "-target-feature" "-sm4"
+// CHECK-CRYPTO84-NOSMSHA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.4a"{{.*}} "-target-feature" "+aes"{{.*}} "-target-feature" "+crypto"{{.*}} "-target-feature" "+pmull"{{.*}} "-target-feature" "+sha2"{{.*}} "-target-feature" "-sha3"{{.*}} "-target-feature" "-sm4"
//
// RUN: %clang -target aarch64 -mcpu=cyclone+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-1 %s
@@ -470,9 +470,9 @@
// RUN: %clang -target aarch64 -mcpu=generic+Crc -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-2 %s
// RUN: %clang -target aarch64 -mcpu=GENERIC+nocrc+CRC -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-2 %s
// RUN: %clang -target aarch64 -mcpu=cortex-a53+noSIMD -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-3 %s
-// CHECK-MCPU-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-aes"{{.*}} "-target-feature" "-sha2"
+// CHECK-MCPU-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "-aes"{{.*}} "-target-feature" "-pmull"{{.*}} "-target-feature" "-sha2"
// CHECK-MCPU-2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+crc"{{.*}} "-target-feature" "+fp-armv8"{{.*}} "-target-feature" "+neon"
-// CHECK-MCPU-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "-aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "-neon" "-target-feature" "+perfmon" "-target-feature" "-sha2"
+// CHECK-MCPU-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "-aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "-neon" "-target-feature" "+perfmon" "-target-feature" "-pmull" "-target-feature" "-sha2"
// RUN: %clang -target aarch64 -mcpu=cyclone+nocrc+nocrypto -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s
// RUN: %clang -target aarch64 -march=armv8-a -mcpu=cyclone+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-MARCH %s
@@ -500,7 +500,7 @@
// RUN: %clang -target aarch64 -march=ARMV8.1A+CRYPTO -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-FEATURE-1 %s
// RUN: %clang -target aarch64 -march=Armv8.1a+NOcrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-FEATURE-2 %s
// RUN: %clang -target aarch64 -march=armv8.1a+noSIMD -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V81A-FEATURE-3 %s
-// CHECK-V81A-FEATURE-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+rdm" "-target-feature" "+sha2"
+// CHECK-V81A-FEATURE-1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pmull" "-target-feature" "+rdm" "-target-feature" "+sha2"
// CHECK-V81A-FEATURE-2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+rdm"
// CHECK-V81A-FEATURE-3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.1a" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+lse" "-target-feature" "-neon" "-target-feature" "-rdm"
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index cdfbd3db64736f..98a5bda92256ed 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -64,7 +64,7 @@ def SVE2p1Unsupported : AArch64Unsupported;
def SVE2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSVE2, HasSVE2orSME, HasSVE2orSME2, HasSSVE_FP8FMA, HasSMEF8F16,
HasSMEF8F32, HasSVE2AES, HasSVE2SHA3, HasSVE2SM4, HasSVE2BitPerm,
- HasSVEB16B16],
+ HasSVEB16B16, HasSVE2PMULL128],
SVE2p1Unsupported.F);
}
diff --git a/llvm/lib/Target/AArch64/AArch64FMV.td b/llvm/lib/Target/AArch64/AArch64FMV.td
index 8266507379f3b1..1545608828bf1e 100644
--- a/llvm/lib/Target/AArch64/AArch64FMV.td
+++ b/llvm/lib/Target/AArch64/AArch64FMV.td
@@ -37,7 +37,7 @@ class FMVExtension<string n, string b, string f, int p> {
int Priority = p;
}
-def : FMVExtension<"aes", "FEAT_AES", "+fp-armv8,+neon", 150>;
+def : FMVExtension<"aes", "FEAT_AES", "+aes,+fp-armv8,+neon", 150>;
def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>;
def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>;
def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>;
@@ -64,7 +64,7 @@ def : FMVExtension<"memtag", "FEAT_MEMTAG", "", 440>;
def : FMVExtension<"memtag2", "FEAT_MEMTAG2", "+mte", 450>;
def : FMVExtension<"memtag3", "FEAT_MEMTAG3", "+mte", 460>;
def : FMVExtension<"mops", "FEAT_MOPS", "+mops", 650>;
-def : FMVExtension<"pmull", "FEAT_PMULL", "+aes,+fp-armv8,+neon", 160>;
+def : FMVExtension<"pmull", "FEAT_PMULL", "+pmull,+aes,+fp-armv8,+neon", 160>;
def : FMVExtension<"predres", "FEAT_PREDRES", "+predres", 480>;
def : FMVExtension<"rcpc", "FEAT_RCPC", "+rcpc", 230>;
def : FMVExtension<"rcpc2", "FEAT_RCPC2", "+rcpc", 240>;
@@ -88,9 +88,9 @@ def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,
def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>;
def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
-def : FMVExtension<"sve2-aes", "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
+def : FMVExtension<"sve2-aes", "FEAT_SVE_AES", "+aes,+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
-def : FMVExtension<"sve2-pmull128", "FEAT_SVE_PMULL128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>;
+def : FMVExtension<"sve2-pmull128", "FEAT_SVE_PMULL128", "+pmull,+aes,+sve2,+sve,+sve2-pmull128,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>;
def : FMVExtension<"sve2-sha3", "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
def : FMVExtension<"sve2-sm4", "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
def : FMVExtension<"wfxt", "FEAT_WFXT", "+wfxt", 550>;
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 69d6b02fefffe9..7a2bc975defc77 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -74,9 +74,15 @@ def FeatureNEON : ExtensionWithMArch<"neon", "NEON", "FEAT_AdvSIMD",
def FeatureSHA2 : ExtensionWithMArch<"sha2", "SHA2", "FEAT_SHA1, FEAT_SHA256",
"Enable SHA1 and SHA256 support", [FeatureNEON]>;
-def FeatureAES : ExtensionWithMArch<"aes", "AES", "FEAT_AES, FEAT_PMULL",
+def FeatureAES : Extension<"aes", "AES", "FEAT_AES",
"Enable AES support", [FeatureNEON]>;
+// NOTE: "aes" means FEAT_AES + FEAT_PMULL for -march or
+// __attribute((target(...))), but only FEAT_AES for FMV.
+let UserVisibleName = "aes" in
+def FeaturePMULL : ExtensionWithMArch<"pmull", "PMULL", "FEAT_PMULL",
+ "Enable PMULL support", [FeatureAES]>;
+
// Crypto has been split up and any combination is now valid (see the
// crypto definitions above). Also, crypto is now context sensitive:
// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
@@ -86,7 +92,7 @@ def FeatureAES : ExtensionWithMArch<"aes", "AES", "FEAT_AES, FEAT_PMULL",
// compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto.
def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto", "FEAT_Crypto",
- "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
+ "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeaturePMULL]>;
def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32",
"Enable Armv8.0-A CRC-32 checksum instructions">;
@@ -369,10 +375,15 @@ def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions",
[FeatureSVE, FeatureUseScalarIncVL]>;
-def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
- "FEAT_SVE_AES, FEAT_SVE_PMULL128",
+def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES", "FEAT_SVE_AES",
"Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
+// NOTE: "sve2-aes" means FEAT_SVE_AES + FEAT_SVE_PMULL128 for -march or
+// __attribute((target(...))), but only FEAT_SVE_AES for FMV.
+let UserVisibleName = "sve2-aes" in
+def FeatureSVE2PMULL128 : ExtensionWithMArch<"sve2-pmull128", "SVE2PMULL128", "FEAT_SVE_PMULL128",
+ "Enable PMULL128 SVE2 instructions", [FeatureSVE2AES, FeaturePMULL]>;
+
def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
"Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 1d1d9b5512cfc7..4a3a3ef0464d70 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -6992,7 +6992,7 @@ multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
V128, V128, V128,
asm#"2", ".8h", ".16b", ".16b", []>;
- let Predicates = [HasAES] in {
+ let Predicates = [HasPMULL] in {
def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
V128, V64, V64,
asm, ".1q", ".1d", ".1d",
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 943c48c0f230a5..4cdf7ee6854c5e 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -117,6 +117,8 @@ def HasSHA2 : Predicate<"Subtarget->hasSHA2()">,
AssemblerPredicateWithAll<(all_of FeatureSHA2), "sha2">;
def HasAES : Predicate<"Subtarget->hasAES()">,
AssemblerPredicateWithAll<(all_of FeatureAES), "aes">;
+def HasPMULL : Predicate<"Subtarget->hasPMULL()">,
+ AssemblerPredicateWithAll<(all_of FeaturePMULL), "pmull">;
def HasDotProd : Predicate<"Subtarget->hasDotProd()">,
AssemblerPredicateWithAll<(all_of FeatureDotProd), "dotprod">;
def HasCRC : Predicate<"Subtarget->hasCRC()">,
@@ -151,6 +153,8 @@ def HasSVE2p1 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasS
AssemblerPredicateWithAll<(all_of FeatureSVE2p1), "sve2p1">;
def HasSVE2AES : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2AES()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2AES), "sve2-aes">;
+def HasSVE2PMULL128 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2PMULL128()">,
+ AssemblerPredicateWithAll<(all_of FeatureSVE2PMULL128), "sve2-pmull128">;
def HasSVE2SM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SM4()">,
AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">;
def HasSVE2SHA3 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SHA3()">,
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 6886df5392565d..300d8d3fb8d9ea 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -658,7 +658,7 @@ def TuneOryon : SubtargetFeature<"oryon-1", "ARMProcFamily",
"Oryon",
"Nuvia Inc Oryon processors", [
FeatureSHA2,
- FeatureAES,
+ FeaturePMULL,
FeatureFPARMv8,
FeatureNEON,
FeatureFuseAES,
@@ -669,7 +669,7 @@ def TuneOryon : SubtargetFeature<"oryon-1", "ARMProcFamily",
FeatureSM4,
FeatureSHA2,
FeatureSHA3,
- FeatureAES,
+ FeaturePMULL,
FeatureFullFP16,
FeatureFP16FML,
FeaturePerfMon,
@@ -678,9 +678,9 @@ def TuneOryon : SubtargetFeature<"oryon-1", "ARMProcFamily",
HasV8_6aOps]>;
def ProcessorFeatures {
- list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
+ list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeaturePMULL,
FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
- list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeaturePerfMon, FeatureCRC,
FeatureLSE, FeatureRAS, FeatureRDM];
@@ -711,27 +711,27 @@ def ProcessorFeatures {
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS,
FeatureNEON, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureDotProd];
- list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeatureSSBS, FeatureRAS,
FeaturePerfMon, FeatureCRC, FeatureLSE, FeatureRDM];
- list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A76 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeatureSSBS, FeaturePerfMon,
FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeaturePerfMon, FeatureSSBS,
FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeaturePerfMon, FeatureSPE,
FeatureSSBS, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> A78AE = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A78AE = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureRCPC, FeaturePerfMon, FeatureSPE,
FeatureSSBS, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> A78C = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureFullFP16, FeatureDotProd,
FeatureFlagM, FeaturePAuth,
FeaturePerfMon, FeatureRCPC, FeatureSPE,
@@ -794,11 +794,11 @@ def ProcessorFeatures {
FeatureCacheDeepPersist,
FeatureLSE, FeatureFlagM, FeatureCRC, FeatureFPARMv8, FeatureNEON,
FeaturePAuth, FeatureRAS, FeatureRCPC];
- list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureRCPC, FeaturePerfMon,
FeatureSPE, FeatureFullFP16, FeatureDotProd,
FeatureSSBS, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureRCPC_IMMO, FeaturePerfMon,
FeatureSPE, FeatureFullFP16, FeatureDotProd,
FeaturePAuth, FeatureSSBS, FeatureFlagM,
@@ -842,27 +842,27 @@ def ProcessorFeatures {
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
FeatureSVE, FeatureComplxNum,
- FeatureAES, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES,
+ FeaturePMULL, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
+ list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeaturePMULL,
FeatureFullFP16, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM,
FeatureFPARMv8];
- list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON,FeaturePerfMon];
- list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA10 = [HasV8_0aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureCRC,
FeatureRDM, FeaturePAN, FeatureLOR, FeatureVH];
- list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA11 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureFullFP16, FeatureCRC,
FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA12 = [HasV8_3aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureFullFP16,
FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA13 = [HasV8_4aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureFullFP16,
FeatureFP16FML, FeatureSHA3, FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureDotProd];
- list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA14 = [HasV8_4aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16, FeatureFP16FML, FeatureSHA3,
// ArmV8.5-a extensions, excluding BTI:
@@ -872,14 +872,14 @@ def ProcessorFeatures {
FeatureComplxNum, FeatureCRC, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureDotProd];
- list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA15 = [HasV8_6aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureComplxNum, FeatureCRC, FeatureJS,
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
- list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA16 = [HasV8_6aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
@@ -887,7 +887,7 @@ def ProcessorFeatures {
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd, FeatureMatMulInt8, FeatureSSBS];
- list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> AppleA17 = [HasV8_6aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
FeatureHCX,
@@ -903,26 +903,26 @@ def ProcessorFeatures {
list<SubtargetFeature> AppleM4 = [HasV8_7aOps, FeatureSHA2, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSHA3,
FeatureFullFP16, FeatureFP16FML,
- FeatureAES, FeatureBF16,
+ FeaturePMULL, FeatureBF16,
FeatureSME, FeatureSME2,
FeatureSMEF64F64, FeatureSMEI16I64,
FeatureComplxNum, FeatureCRC, FeatureJS,
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureDotProd, FeatureMatMulInt8];
- list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
+ list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeaturePMULL,
FeaturePerfMon, FeatureNEON, FeatureFPARMv8];
- list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd,
+ list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureDotProd,
FeatureFullFP16, FeaturePerfMon, FeatureCRC, FeatureFPARMv8,
FeatureLSE, FeatureNEON, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
+ list<SubtargetFeature> Falkor = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeaturePMULL,
FeatureFPARMv8, FeatureNEON, FeaturePerfMon,
FeatureRDM];
- list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd,
+ list<SubtargetFeature> NeoverseE1 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureDotProd,
FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
FeatureRCPC, FeatureSSBS, FeaturePerfMon, FeatureCRC,
FeatureLSE, FeatureRAS, FeatureRDM];
- list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd,
+ list<SubtargetFeature> NeoverseN1 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureDotProd,
FeatureFPARMv8, FeatureFullFP16, FeatureNEON,
FeatureRCPC, FeatureSPE, FeatureSSBS,
FeaturePerfMon, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
@@ -945,7 +945,7 @@ def ProcessorFeatures {
FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureNEON];
list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
- FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML,
+ FeatureSHA2, FeaturePMULL, FeatureFPARMv8, FeatureFP16FML,
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSSBS, FeatureSVE,
@@ -954,7 +954,7 @@ def ProcessorFeatures {
FeatureCRC, FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS,
FeatureRCPC, FeatureRDM];
list<SubtargetFeature> NeoverseV1 = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
- FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML,
+ FeatureSHA2, FeaturePMULL, FeatureFPARMv8, FeatureFP16FML,
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSSBS, FeatureSVE,
@@ -989,28 +989,28 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS,
FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureRME];
- list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeatureSPE, FeaturePerfMon, FeatureCRC,
FeatureCCIDX,
FeatureLSE, FeatureRDM, FeatureRAS, FeatureRCPC];
- list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
+ list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeaturePMULL,
FeatureFPARMv8, FeaturePerfMon, FeatureNEON];
- list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureSHA2, FeatureAES,
+ list<SubtargetFeature> ThunderX2T99 = [HasV8_1aOps, FeatureCRC, FeatureSHA2, FeaturePMULL,
FeatureFPARMv8, FeatureNEON, FeatureLSE,
FeatureRDM];
- list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureSHA2, FeatureAES,
+ list<SubtargetFeature> ThunderX3T110 = [HasV8_3aOps, FeatureCRC, FeatureSHA2, FeaturePMULL,
FeatureFPARMv8, FeatureNEON, FeatureLSE,
FeatureCCIDX,
FeaturePAuth, FeaturePerfMon, FeatureComplxNum,
FeatureJS, FeatureRAS, FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
+ list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureSHA2, FeaturePMULL, FeatureFPARMv8,
FeatureNEON, FeaturePerfMon, FeatureSPE,
FeatureFullFP16, FeatureFP16FML, FeatureDotProd,
FeatureJS, FeatureComplxNum, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM];
list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureSSBS, FeatureRandGen, FeatureSB,
- FeatureSHA2, FeatureSHA3, FeatureAES,
+ FeatureSHA2, FeatureSHA3, FeaturePMULL,
FeatureFullFP16, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS,
FeatureCCIDX,
@@ -1018,7 +1018,7 @@ def ProcessorFeatures {
list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
- FeatureSHA3, FeatureAES,
+ FeatureSHA3, FeaturePMULL,
FeatureFullFP16, FeatureBF16, FeatureComplxNum,
FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC,
@@ -1027,7 +1027,7 @@ def ProcessorFeatures {
list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
FeatureMTE, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
- FeatureSHA3, FeatureAES, FeatureCSSC,
+ FeatureSHA3, FeaturePMULL, FeatureCSSC,
FeatureWFxT, FeatureFullFP16, FeatureBF16, FeatureComplxNum,
FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC,
@@ -1037,7 +1037,7 @@ def ProcessorFeatures {
list<SubtargetFeature> Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureRandGen,
FeaturePAuth, FeatureSM4, FeatureSHA2,
- FeatureSHA3, FeatureAES,
+ FeatureSHA3, FeaturePMULL,
FeatureSPE, FeatureBF16, FeatureComplxNum, FeatureCRC,
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 7240f6a22a87bd..2024f8bd7fb267 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -3880,13 +3880,15 @@ let Predicates = [HasSVE2AES] in {
// SVE2 crypto unary operations
defm AESMC_ZZ_B : sve2_crypto_unary_op<0b0, "aesmc", int_aarch64_sve_aesmc>;
defm AESIMC_ZZ_B : sve2_crypto_unary_op<0b1, "aesimc", int_aarch64_sve_aesimc>;
+} // End HasSVE2AES
+let Predicates = [HasSVE2PMULL128] in {
// PMULLB and PMULLT instructions which operate with 64-bit source and
// 128-bit destination elements are enabled with crypto extensions, similar
// to NEON PMULL2 instruction.
defm PMULLB_ZZZ_Q : sve2_wide_int_arith_pmul<0b00, 0b11010, "pmullb", int_aarch64_sve_pmullb_pair>;
defm PMULLT_ZZZ_Q : sve2_wide_int_arith_pmul<0b00, 0b11011, "pmullt", int_aarch64_sve_pmullt_pair>;
-} // End HasSVE2AES
+} // End HasSVE2PMULL128
let Predicates = [HasSVE2SM4] in {
// SVE2 crypto constructive binary operations
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 6a4b94a216832e..75439f925babe8 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3655,7 +3655,7 @@ static const struct Extension {
{"sm4", {AArch64::FeatureSM4}},
{"sha3", {AArch64::FeatureSHA3}},
{"sha2", {AArch64::FeatureSHA2}},
- {"aes", {AArch64::FeatureAES}},
+ {"aes", {AArch64::FeatureAES, AArch64::FeaturePMULL}},
{"crypto", {AArch64::FeatureCrypto}},
{"fp", {AArch64::FeatureFPARMv8}},
{"simd", {AArch64::FeatureNEON}},
@@ -3676,7 +3676,7 @@ static const struct Extension {
{"sve", {AArch64::FeatureSVE}},
{"sve-b16b16", {AArch64::FeatureSVEB16B16}},
{"sve2", {AArch64::FeatureSVE2}},
- {"sve2-aes", {AArch64::FeatureSVE2AES}},
+ {"sve2-aes", {AArch64::FeatureSVE2AES, AArch64::FeatureSVE2PMULL128}},
{"sve2-sm4", {AArch64::FeatureSVE2SM4}},
{"sve2-sha3", {AArch64::FeatureSVE2SHA3}},
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 9fc7201efac6e2..316197edc7abab 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -244,15 +244,24 @@ void AArch64::ExtensionSet::enable(ArchExtKind E) {
}
void AArch64::ExtensionSet::disable(ArchExtKind E) {
- // -crypto always disables aes, sha2, sha3 and sm4, even for architectures
+ // -crypto always disables pmull, sha2, sha3 and sm4, even for architectures
// where the latter two would not be enabled by +crypto.
if (E == AEK_CRYPTO) {
- disable(AEK_AES);
+ disable(AEK_PMULL);
disable(AEK_SHA2);
disable(AEK_SHA3);
disable(AEK_SM4);
}
+ // FEAT_AES and FEAT_PMULL were historically lumped under the name 'aes'.
+ // Therefore 'noaes' should disable FEAT_AES too even though it does not
+ // depend on FEAT_PMULL after they got split.
+ if (E == AEK_PMULL)
+ disable(AEK_AES);
+ // The same goes for FEAT_SVE2_AES and FEAT_SVE2_PMULL128.
+ if (E == AEK_SVE2PMULL128)
+ disable(AEK_SVE2AES);
+
if (!Enabled.test(E))
return;
diff --git a/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll b/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
index 9d7aa78ec139f6..288a78a2221a24 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+aes -o - %s| FileCheck %s --check-prefixes=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+pmull -o - %s| FileCheck %s --check-prefixes=CHECK
; User code intends to execute {pmull, pmull2} instructions on {lower, higher} half of the same vector registers directly.
; Test that PMULL2 are generated for higher-half operands.
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
index 79645e32074c89..acda8a4fa0baeb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon,+aes | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon,+pmull | FileCheck %s
declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) #5
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index 499786470d4ac1..169d705ed38a8a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=+aes | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -mattr=+pmull | FileCheck %s
define <8 x i16> @smull8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: smull8h:
diff --git a/llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll b/llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
index 0c4963dfdcedd6..281ecae24c78e0 100644
--- a/llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
+++ b/llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon,+aes | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon,+pmull | FileCheck %s
; This test checks that pmull2 instruction is used for vmull_high_p64 intrinsic.
; There are two extraction operations located in different basic blocks:
diff --git a/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll b/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
index ff9dcbeda18c11..d9952a62d393cd 100644
--- a/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
+++ b/llvm/test/CodeGen/AArch64/pmull-ldr-merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+aes -o - %s| FileCheck %s --check-prefixes=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+pmull -o - %s| FileCheck %s --check-prefixes=CHECK
; Two operands are in scalar form.
; Tests that both operands are loaded into SIMD registers directly as opposed to being loaded into GPR followed by a fmov.
diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic-128.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic-128.ll
index f695fd444be77e..2408784778664c 100644
--- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic-128.ll
+++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic-128.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-aes < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2-pmull128 < %s | FileCheck %s
;
; PMULLB
diff --git a/llvm/test/MC/AArch64/SVE2/pmullb-128-diagnostics.s b/llvm/test/MC/AArch64/SVE2/pmullb-128-diagnostics.s
index 001b40c69fc30e..1f81f6085847da 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullb-128-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullb-128-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-pmull128 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
diff --git a/llvm/test/MC/AArch64/SVE2/pmullb-128.s b/llvm/test/MC/AArch64/SVE2/pmullb-128.s
index d48c75b3d49997..d7fd0d5d45ada0 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullb-128.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullb-128.s
@@ -1,17 +1,17 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-pmull128 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN: | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-pmull128 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2-pmull128 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-pmull128 < %s \
// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmullb z29.q, z30.d, z31.d
// CHECK-INST: pmullb z29.q, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0x6b,0x1f,0x45]
-// CHECK-ERROR: instruction requires: sve2-aes
+// CHECK-ERROR: instruction requires: sve2-pmull128
// CHECK-UNKNOWN: 451f6bdd <unknown>
diff --git a/llvm/test/MC/AArch64/SVE2/pmullt-128-diagnostics.s b/llvm/test/MC/AArch64/SVE2/pmullt-128-diagnostics.s
index 301824e8681722..f732be8edbb6e4 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullt-128-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullt-128-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes 2>&1 < %s| FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-pmull128 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
diff --git a/llvm/test/MC/AArch64/SVE2/pmullt-128.s b/llvm/test/MC/AArch64/SVE2/pmullt-128.s
index e1eca8d1d89f80..33b64aba2caafd 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullt-128.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullt-128.s
@@ -1,17 +1,17 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-aes < %s \
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-pmull128 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
-// RUN: | llvm-objdump -d --mattr=+sve2-aes - | FileCheck %s --check-prefix=CHECK-INST
-// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-aes < %s \
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-pmull128 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2-pmull128 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2-pmull128 < %s \
// RUN: | llvm-objdump -d --mattr=-sve2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
pmullt z29.q, z30.d, z31.d
// CHECK-INST: pmullt z29.q, z30.d, z31.d
// CHECK-ENCODING: [0xdd,0x6f,0x1f,0x45]
-// CHECK-ERROR: instruction requires: sve2-aes
+// CHECK-ERROR: instruction requires: sve2-pmull128
// CHECK-UNKNOWN: 451f6fdd <unknown>
diff --git a/llvm/test/MC/AArch64/arm64-diagno-predicate.s b/llvm/test/MC/AArch64/arm64-diagno-predicate.s
index 763f26067c990b..8756c7408829b8 100644
--- a/llvm/test/MC/AArch64/arm64-diagno-predicate.s
+++ b/llvm/test/MC/AArch64/arm64-diagno-predicate.s
@@ -13,7 +13,7 @@
// CHECK-ERROR-NEXT: ^
pmull v0.1q, v1.1d, v2.1d
-// CHECK-ERROR: error: instruction requires: aes
+// CHECK-ERROR: error: instruction requires: pmull
// CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d
// CHECK-ERROR-NEXT: ^
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 1843af56555461..39d183bd1b87f2 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -1,5 +1,5 @@
// RUN: not llvm-mc -triple aarch64 \
-// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
+// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+sve2-pmull128,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
// RUN: -mattr=+rcpc3,+lse128,+d128,+the,+rasv2,+ite,+cssc,+specres2,+gcs \
// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
@@ -35,12 +35,29 @@ sha1h s0, s1
// CHECK: [[@LINE-1]]:1: error: instruction requires: sha2
// CHECK-NEXT: sha1h s0, s1
+aese z0.b, z0.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: sve2-aes
+pmullt z29.q, z30.d, z31.d
+// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: sve2-pmull128
+.arch_extension nosve2-aes
+aese z0.b, z0.b, z31.b
+// CHECK: [[@LINE-1]]:1: error: instruction requires: sve2-aes
+// CHECK-NEXT: aese z0.b, z0.b, z31.b
+pmullt z29.q, z30.d, z31.d
+// CHECK: [[@LINE-1]]:1: error: instruction requires: sve2-pmull128
+// CHECK-NEXT: pmullt z29.q, z30.d, z31.d
+
aese v0.16b, v1.16b
// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: aes
+pmull v0.1q, v1.1d, v2.1d
+// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: pmull
.arch_extension noaes
aese v0.16b, v1.16b
// CHECK: [[@LINE-1]]:1: error: instruction requires: aes
// CHECK-NEXT: aese v0.16b, v1.16b
+pmull v0.1q, v1.1d, v2.1d
+// CHECK: [[@LINE-1]]:1: error: instruction requires: pmull
+// CHECK-NEXT: pmull v0.1q, v1.1d, v2.1d
fminnm d0, d0, d1
// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: fp
diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
index d8051e7ecb4fe8..9f36ca71137292 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A510-sve-instructions.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a510 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a510 -mattr=+sve2-pmull128,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
abs z0.b, p0/m, z0.b
abs z0.d, p0/m, z0.d
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
index 99e39567b1ad61..6b4adda74a17d9 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -mattr=+sve2-pmull128,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
abs z0.b, p0/m, z0.b
abs z0.d, p0/m, z0.d
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
index 395aa1141abb51..e0aad01cd9038c 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -mattr=+sve2-pmull128,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
abs z0.b, p0/m, z0.b
abs z0.d, p0/m, z0.d
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s
index acd35568249499..fdff3e13edcd4a 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+sve2-pmull128,+sve2-sha3,+sve2-sm4 -instruction-tables < %s | FileCheck %s
abs z0.b, p0/m, z0.b
abs z0.d, p0/m, z0.d
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 13db80ab5c68ea..fb707697fb994e 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1319,7 +1319,8 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_CPA, AArch64::AEK_PAUTHLR,
AArch64::AEK_TLBIW, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_FP8,
- AArch64::AEK_SVEB16B16,
+ AArch64::AEK_SVEB16B16, AArch64::AEK_PMULL,
+ AArch64::AEK_SVE2PMULL128,
};
std::vector<StringRef> Features;
@@ -1343,6 +1344,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sha3"));
EXPECT_TRUE(llvm::is_contained(Features, "+sha2"));
EXPECT_TRUE(llvm::is_contained(Features, "+aes"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+pmull"));
EXPECT_TRUE(llvm::is_contained(Features, "+dotprod"));
EXPECT_TRUE(llvm::is_contained(Features, "+fp-armv8"));
EXPECT_TRUE(llvm::is_contained(Features, "+neon"));
@@ -1354,6 +1356,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sve-b16b16"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-aes"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+sve2-pmull128"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sm4"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-sha3"));
EXPECT_TRUE(llvm::is_contained(Features, "+sve2-bitperm"));
@@ -1491,6 +1494,7 @@ TEST(TargetParserTest, AArch64ArchPartialOrder) {
TEST(TargetParserTest, AArch64ArchExtFeature) {
const char *ArchExt[][4] = {
+ {"aes", "noaes", "+pmull", "-pmull"},
{"crc", "nocrc", "+crc", "-crc"},
{"crypto", "nocrypto", "+crypto", "-crypto"},
{"flagm", "noflagm", "+flagm", "-flagm"},
@@ -1505,7 +1509,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sve", "nosve", "+sve", "-sve"},
{"sve-b16b16", "nosve-b16b16", "+sve-b16b16", "-sve-b16b16"},
{"sve2", "nosve2", "+sve2", "-sve2"},
- {"sve2-aes", "nosve2-aes", "+sve2-aes", "-sve2-aes"},
+ {"sve2-aes", "nosve2-aes", "+sve2-pmull128", "-sve2-pmull128"},
{"sve2-sm4", "nosve2-sm4", "+sve2-sm4", "-sve2-sm4"},
{"sve2-sha3", "nosve2-sha3", "+sve2-sha3", "-sve2-sha3"},
{"sve2p1", "nosve2p1", "+sve2p1", "-sve2p1"},
More information about the cfe-commits
mailing list