[clang] [llvm] riscv: Support -mstack-protector-guard=tls (PR #108942)

[Keith Packard via cfe-commits]

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@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
+
+target triple = "riscv64-unknown-linux-gnu"
+
+define dso_local void @foo(i64 %t) local_unnamed_addr #0 {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -8
+; CHECK-NEXT:    .cfi_offset s0, -16
+; CHECK-NEXT:    .cfi_offset s1, -24
+; CHECK-NEXT:    addi s0, sp, 32
+; CHECK-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-NEXT:    lui s1, %hi(__stack_chk_guard)
+; CHECK-NEXT:    ld a1, %lo(__stack_chk_guard)(s1)
+; CHECK-NEXT:    sd a1, -32(s0)
+; CHECK-NEXT:    slli a0, a0, 2
+; CHECK-NEXT:    addi a0, a0, 15
+; CHECK-NEXT:    andi a0, a0, -16
+; CHECK-NEXT:    sub a0, sp, a0
+; CHECK-NEXT:    mv sp, a0
+; CHECK-NEXT:    call baz
+; CHECK-NEXT:    ld a0, %lo(__stack_chk_guard)(s1)
+; CHECK-NEXT:    ld a1, -32(s0)
+; CHECK-NEXT:    bne a0, a1, .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    addi sp, s0, -32
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    call __stack_chk_fail
+  %vla = alloca i32, i64 %t, align 4
+  call void @baz(ptr nonnull %vla)
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keith-packard wrote:

Inherited from ARM/stack-guard-tls.ll, so I didn't consider it. But, no, it's not necessary.

https://github.com/llvm/llvm-project/pull/108942