[clang] [llvm] [AMDGPU] Change CF intrinsics lowering to reconverge on predecessors (PR #108596)

[Jay Foad via cfe-commits]

jayfoad wrote:

> Although, revisiting this now, I still don't understand why they decided to include ALL spill opcodes in the prologue, but not only the SGPR spills? Clearly, none of the VGPR reloads really belong to the prologue.
> 
> At a first glance, changing the isSpill(opcode) to isSGPRSpill(opcode) in the snippet below would solve the initial case. ` return IsNullOrVectorRegister && (isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY && MI.modifiesRegister(AMDGPU::EXEC, &RI))); }`
> 
> I need to look at this a bit more. I am sure they would have done this if such a simple change had solved the problem.

I like this change - it fixes the problem I reported in #109294.

https://github.com/llvm/llvm-project/pull/108596