[clang] [compiler-rt] [llvm] [AArch64] Split FeatureMTE to FEAT_MTE and FEAT_MTE2. (PR #109299)
Alexandros Lamprineas via cfe-commits
cfe-commits at lists.llvm.org
Thu Sep 19 08:26:33 PDT 2024
https://github.com/labrinea created https://github.com/llvm/llvm-project/pull/109299
These extensions depend on each other as follows: mte -> mte2
Currently in LLVM FeatureMTE models both FEAT_MTE and FEAT_MTE2 lumped together. However the architecture does not mandate that both need to be implemented at the same time. Therefore it makes sense to split them. This will allow Function Multiversioning to enable backend features for 'memtag' (means FEAT_MTE in FMV) which was previously impossible. I have added an override for the user visible name of FeatureMTE2 ('memtag') to preserve the old semantics for backwards compatibility with command line, target attribute and assembler directives.
>From 1d7cce3f3b45f1f0a59cbc16133ded99968348da Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: Wed, 18 Sep 2024 09:07:10 +0100
Subject: [PATCH] [AArch64] Split FeatureMTE to FEAT_MTE and FEAT_MTE2.
These extensions depend on each other as follows: mte -> mte2
Currently in LLVM FeatureMTE models both FEAT_MTE and FEAT_MTE2 lumped together.
However the architecture does not mandate that both need to be implemented at
the same time. Therefore it makes sense to split them. This will allow Function
Multiversioning to enable backend features for 'memtag' (means FEAT_MTE in FMV)
which was previously impossible. I have added an override for the user visible
name of FeatureMTE2 ('memtag') to preserve the old semantics for backwards
compatibility with command line, target attribute and assembler directives.
---
clang/lib/Basic/Targets/AArch64.cpp | 2 +-
clang/test/CodeGen/aarch64-fmv-dependencies.c | 5 ++-
clang/test/CodeGen/aarch64-targetattr.c | 2 +-
.../test/CodeGen/attr-target-clones-aarch64.c | 24 ++++++------
clang/test/CodeGen/attr-target-version.c | 19 +++++-----
.../aarch64-ampere1a.c | 3 +-
.../aarch64-ampere1b.c | 3 +-
.../aarch64-cortex-a510.c | 3 +-
.../aarch64-cortex-a520.c | 3 +-
.../aarch64-cortex-a520ae.c | 3 +-
.../aarch64-cortex-a710.c | 3 +-
.../aarch64-cortex-a715.c | 3 +-
.../aarch64-cortex-a720.c | 3 +-
.../aarch64-cortex-a720ae.c | 3 +-
.../aarch64-cortex-a725.c | 3 +-
.../aarch64-cortex-x2.c | 3 +-
.../aarch64-cortex-x3.c | 3 +-
.../aarch64-cortex-x4.c | 3 +-
.../aarch64-cortex-x925.c | 3 +-
.../aarch64-neoverse-n2.c | 3 +-
.../aarch64-neoverse-n3.c | 3 +-
.../aarch64-neoverse-v2.c | 3 +-
.../aarch64-neoverse-v3.c | 3 +-
.../aarch64-neoverse-v3ae.c | 3 +-
.../print-supported-extensions-aarch64.c | 2 +-
clang/test/Sema/attr-target-clones-aarch64.c | 2 +-
.../builtins/cpu_model/aarch64/fmv/mrs.inc | 5 +++
llvm/lib/Target/AArch64/AArch64.td | 5 +--
llvm/lib/Target/AArch64/AArch64FMV.td | 6 +--
llvm/lib/Target/AArch64/AArch64Features.td | 7 +++-
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 22 ++++++-----
llvm/lib/Target/AArch64/AArch64Processors.td | 38 +++++++++----------
llvm/lib/Target/AArch64/AArch64SchedA53.td | 3 +-
llvm/lib/Target/AArch64/AArch64SchedA55.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedA57.td | 3 +-
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 6 +--
.../lib/Target/AArch64/AArch64SchedAmpere1.td | 2 +-
.../lib/Target/AArch64/AArch64SchedCyclone.td | 3 +-
.../Target/AArch64/AArch64SchedExynosM3.td | 3 +-
.../Target/AArch64/AArch64SchedExynosM4.td | 3 +-
.../Target/AArch64/AArch64SchedExynosM5.td | 3 +-
llvm/lib/Target/AArch64/AArch64SchedFalkor.td | 3 +-
llvm/lib/Target/AArch64/AArch64SchedKryo.td | 3 +-
.../Target/AArch64/AArch64SchedNeoverseN1.td | 3 +-
.../Target/AArch64/AArch64SchedNeoverseV1.td | 4 +-
llvm/lib/Target/AArch64/AArch64SchedTSV110.td | 3 +-
.../Target/AArch64/AArch64SchedThunderX.td | 3 +-
.../AArch64/AArch64SchedThunderX2T99.td | 3 +-
.../AArch64/AArch64SchedThunderX3T110.td | 3 +-
.../Target/AArch64/AArch64SystemOperands.td | 24 +++++++-----
.../AArch64/AsmParser/AArch64AsmParser.cpp | 3 +-
llvm/lib/TargetParser/AArch64TargetParser.cpp | 6 +++
llvm/test/MC/AArch64/armv8.5a-mte-error.s | 2 +-
llvm/test/MC/AArch64/armv8.5a-mte.s | 38 +++++++++----------
.../directive-arch_extension-negative.s | 9 ++++-
.../MC/Disassembler/AArch64/armv8.5a-mte.txt | 4 +-
.../TargetParser/TargetParserTest.cpp | 9 +++--
57 files changed, 204 insertions(+), 140 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index 5f5dfcb722f9d4..60580c478a80d5 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1059,7 +1059,7 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasFullFP16 = true;
HasFP16FML = true;
}
- if (Feature == "+mte")
+ if (Feature == "+mte2")
HasMTE = true;
if (Feature == "+tme")
HasTME = true;
diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c
index e39c7adbe4a9b0..70c0e20df83644 100644
--- a/clang/test/CodeGen/aarch64-fmv-dependencies.c
+++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c
@@ -78,7 +78,7 @@ __attribute__((target_version("ls64_v"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mlse() #[[lse:[0-9]+]] {
__attribute__((target_version("lse"))) int fmv(void) { return 0; }
-// CHECK: define dso_local i32 @fmv._Mmemtag() #[[ATTR0:[0-9]+]] {
+// CHECK: define dso_local i32 @fmv._Mmemtag() #[[memtag:[0-9]+]] {
__attribute__((target_version("memtag"))) int fmv(void) { return 0; }
// CHECK: define dso_local i32 @fmv._Mmemtag2() #[[memtag2:[0-9]+]] {
@@ -212,7 +212,8 @@ int caller() {
// CHECK: attributes #[[jscvt]] = { {{.*}} "target-features"="+fp-armv8,+jsconv,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[ls64_accdata]] = { {{.*}} "target-features"="+fp-armv8,+ls64,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a"
-// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[memtag]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a"
+// CHECK: attributes #[[memtag2]] = { {{.*}} "target-features"="+fp-armv8,+mte,+mte2,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a"
// CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a"
diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c
index 1bc78a6e1f8c0f..e62243735741c2 100644
--- a/clang/test/CodeGen/aarch64-targetattr.c
+++ b/clang/test/CodeGen/aarch64-targetattr.c
@@ -204,7 +204,7 @@ void applem4() {}
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+ete,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+mte2,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+ssbs,+sve,+sve2,+sve2-bitperm,+trbe,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8a,+v9a" }
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+ete,+fp-armv8,+neon,+trbe,+v8a" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
diff --git a/clang/test/CodeGen/attr-target-clones-aarch64.c b/clang/test/CodeGen/attr-target-clones-aarch64.c
index 274e05de594b8e..f4e31c7e3c9f69 100644
--- a/clang/test/CodeGen/attr-target-clones-aarch64.c
+++ b/clang/test/CodeGen/attr-target-clones-aarch64.c
@@ -827,10 +827,10 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon" }
// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2" }
// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sha2" }
-// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+neon,+sha2" }
+// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+mte,+mte2,+neon,+sha2" }
// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+dotprod,+fp-armv8,+neon" }
-// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mte" }
+// CHECK: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mte,+mte2" }
// CHECK: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
// CHECK: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon" }
@@ -846,15 +846,17 @@ inline int __attribute__((target_clones("fp16", "sve2-bitperm+fcma", "default"))
// CHECK-MTE-BTI: attributes #[[ATTR0:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+lse,+mte,+neon" }
// CHECK-MTE-BTI: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2" }
// CHECK-MTE-BTI: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+sha2" }
-// CHECK-MTE-BTI: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon" }
-// CHECK-MTE-BTI: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+crc,+dotprod,+fp-armv8,+mte,+neon" }
-// CHECK-MTE-BTI: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte" }
-// CHECK-MTE-BTI: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon" }
-// CHECK-MTE-BTI: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+complxnum,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-bitperm" }
-// CHECK-MTE-BTI: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+rand" }
-// CHECK-MTE-BTI: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte,+predres,+rcpc" }
-// CHECK-MTE-BTI: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
-// CHECK-MTE-BTI: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sb,+sve" }
+// CHECK-MTE-BTI: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+mte2,+neon,+sha2" }
+// CHECK-MTE-BTI: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon" }
+// CHECK-MTE-BTI: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+crc,+dotprod,+fp-armv8,+mte,+neon" }
+// CHECK-MTE-BTI: attributes #[[ATTR6:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte,+mte2" }
+// CHECK-MTE-BTI: attributes #[[ATTR7:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte" }
+// CHECK-MTE-BTI: attributes #[[ATTR8:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon" }
+// CHECK-MTE-BTI: attributes #[[ATTR9:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+complxnum,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-bitperm" }
+// CHECK-MTE-BTI: attributes #[[ATTR10:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+mte,+neon,+rand" }
+// CHECK-MTE-BTI: attributes #[[ATTR11:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+mte,+predres,+rcpc" }
+// CHECK-MTE-BTI: attributes #[[ATTR12:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-aes,+wfxt" }
+// CHECK-MTE-BTI: attributes #[[ATTR13:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti,+fp-armv8,+fullfp16,+mte,+neon,+sb,+sve" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c
index b058f84f78baad..c1b158a68af38a 100644
--- a/clang/test/CodeGen/attr-target-version.c
+++ b/clang/test/CodeGen/attr-target-version.c
@@ -751,21 +751,21 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd
-// CHECK-SAME: () #[[ATTR4]] {
+// CHECK-SAME: () #[[ATTR33:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 14
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4
-// CHECK-SAME: () #[[ATTR33:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR34:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 15
//
//
// CHECK: Function Attrs: noinline nounwind optnone
// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm
-// CHECK-SAME: () #[[ATTR34:[0-9]+]] {
+// CHECK-SAME: () #[[ATTR35:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: ret i32 16
//
@@ -1116,7 +1116,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+altnzcv,+bf16,+flagm,+sme,+sme-i16i64" }
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+sha2" }
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+dotprod,+fp-armv8,+ls64,+neon" }
-// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon" }
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fp16fml,+fullfp16,+mte,+neon" }
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc" }
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bti" }
@@ -1143,11 +1143,12 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de
// CHECK: attributes #[[ATTR28]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+sve" }
// CHECK: attributes #[[ATTR29]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-sha3" }
// CHECK: attributes #[[ATTR30]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+sve2,+sve2-aes,+sve2-bitperm" }
-// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+mte,+neon,+sve,+sve2,+sve2-sm4" }
-// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+rcpc,+rcpc3" }
-// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sm4" }
-// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+rdm" }
-// CHECK: attributes #[[ATTR35:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm" }
+// CHECK: attributes #[[ATTR31]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+mte,+mte2,+neon,+sve,+sve2,+sve2-sm4" }
+// CHECK: attributes #[[ATTR32]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+mops,+mte,+mte2,+rcpc,+rcpc3" }
+// CHECK: attributes #[[ATTR33]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fp16fml,+fullfp16,+neon" }
+// CHECK: attributes #[[ATTR34]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+sm4" }
+// CHECK: attributes #[[ATTR35]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+lse,+neon,+rdm" }
+// CHECK: attributes #[[ATTR36:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon,+rdm" }
//.
// CHECK-NOFMV: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
// CHECK-NOFMV: attributes #[[ATTR1:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-fmv" }
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
index 3c20cff28821e7..2afcced18618b8 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1a.c
@@ -34,7 +34,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
index 444ac4526200fe..ac0d47f6f00138 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c
@@ -36,7 +36,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
index 4cd80eecf0a81c..d26340805d7972 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a510.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
index 6ddd52a4a7089c..2dc65ee6509733 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
index 35399a3c85c626..fb98ec997ea412 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
index f4ba17195cdf6b..010abc17762768 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a710.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
index 3d04509b033f6d..a4de5455a8aaeb 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a715.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
index a80bc038440c19..93a29df4610421 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
index b2d5178650a672..ccfd9bce0734a4 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a720ae.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
index 5dbf9ce72aa007..523a902db9d9a4 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-a725.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
index c4067dcb400ba9..edf8e96f875992 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x2.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
index 97c1405b94a40f..ef520e41b82b68 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x3.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
index 7ccab05ddab6ad..8fa8236b29afe3 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x4.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
index 9d93aa118290aa..6ab8a1a24589ab 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-cortex-x925.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
index 12a35b7340cf30..a022c5594ac4c0 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n2.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
index 942788d3999978..7f0d67b6455a11 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-n3.c
@@ -35,7 +35,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v2.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v2.c
index b11acdd34ee6d1..7a620db4cb9f6c 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v2.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v2.c
@@ -31,7 +31,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
index 89aef5a47f72cb..d556894e1bb04b 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3.c
@@ -37,7 +37,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
index eda46de652f6fc..63567680dcb637 100644
--- a/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-neoverse-v3ae.c
@@ -37,7 +37,8 @@
// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
-// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_MTE Enable Memory Tagging Extension 1
+// CHECK-NEXT: FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index e6247307c7219f..c6dad22d796950 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -37,7 +37,7 @@
// CHECK-NEXT: lse128 FEAT_LSE128 Enable Armv9.4-A 128-bit Atomic instructions
// CHECK-NEXT: lut FEAT_LUT Enable Lookup Table instructions
// CHECK-NEXT: mops FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
-// CHECK-NEXT: memtag FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: memtag FEAT_MTE2 Enable Memory Tagging Extension 2
// CHECK-NEXT: simd FEAT_AdvSIMD Enable Advanced SIMD instructions
// CHECK-NEXT: pauth FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
// CHECK-NEXT: pauth-lr FEAT_PAuth_LR Enable Armv9.5-A PAC enhancements
diff --git a/clang/test/Sema/attr-target-clones-aarch64.c b/clang/test/Sema/attr-target-clones-aarch64.c
index bc3fceab82825b..8480e98aa6c8c8 100644
--- a/clang/test/Sema/attr-target-clones-aarch64.c
+++ b/clang/test/Sema/attr-target-clones-aarch64.c
@@ -24,7 +24,7 @@ int __attribute__((target_clones("rng", "fp16fml+fp", "default"))) redecl4(void)
// expected-error at +3 {{'target_clones' attribute does not match previous declaration}}
// expected-note at -2 {{previous declaration is here}}
// expected-warning at +1 {{version list contains entries that don't impact code generation}}
-int __attribute__((target_clones("dgh+memtag+rpres+ls64_v", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
+int __attribute__((target_clones("dgh+rpres+ls64_v", "ebf16+dpb+sha1", "default"))) redecl4(void) { return 1; }
int __attribute__((target_version("flagm2"))) redef2(void) { return 1; }
// expected-error at +2 {{multiversioned function redeclarations require identical target attributes}}
diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
index e4d5e7f2bd7e36..e8daa6cbcbc56d 100644
--- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
+++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc
@@ -119,6 +119,11 @@ static void __init_cpu_features_constructor(unsigned long hwcap,
/* ID_AA64ISAR1_EL1.LS64 >= 0b0011 */
if (extractBits(ftr, 60, 4) >= 0x3)
setCPUFeature(FEAT_LS64_ACCDATA);
+
+ getCPUFeature(ID_AA64PFR1_EL1, ftr);
+ // ID_AA64PFR1_EL1.MTE >= 0b0001
+ if (extractBits(ftr, 8, 4) >= 0x1)
+ setCPUFeature(FEAT_MEMTAG);
}
if (hwcap & HWCAP_FP) {
setCPUFeature(FEAT_FP);
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 662813b9d91ed3..0b8db556c79a84 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -87,9 +87,8 @@ def SMEUnsupported : AArch64Unsupported {
SME2Unsupported.F);
}
-def MTEUnsupported : AArch64Unsupported {
- let F = [HasMTE];
-}
+let F = [HasMTE, HasMTE2] in
+def MTEUnsupported : AArch64Unsupported;
let F = [HasPAuth, HasPAuthLR] in
def PAUnsupported : AArch64Unsupported;
diff --git a/llvm/lib/Target/AArch64/AArch64FMV.td b/llvm/lib/Target/AArch64/AArch64FMV.td
index 7a40c83b2bb21e..88bc6766ea0503 100644
--- a/llvm/lib/Target/AArch64/AArch64FMV.td
+++ b/llvm/lib/Target/AArch64/AArch64FMV.td
@@ -62,9 +62,9 @@ def : FMVExtension<"ls64", "FEAT_LS64", "", 520>;
def : FMVExtension<"ls64_accdata", "FEAT_LS64_ACCDATA", "+ls64", 540>;
def : FMVExtension<"ls64_v", "FEAT_LS64_V", "", 530>;
def : FMVExtension<"lse", "FEAT_LSE", "+lse", 80>;
-def : FMVExtension<"memtag", "FEAT_MEMTAG", "", 440>;
-def : FMVExtension<"memtag2", "FEAT_MEMTAG2", "+mte", 450>;
-def : FMVExtension<"memtag3", "FEAT_MEMTAG3", "+mte", 460>;
+def : FMVExtension<"memtag", "FEAT_MEMTAG", "+mte", 440>;
+def : FMVExtension<"memtag2", "FEAT_MEMTAG2", "+mte2,+mte", 450>;
+def : FMVExtension<"memtag3", "FEAT_MEMTAG3", "+mte2,+mte", 460>;
def : FMVExtension<"mops", "FEAT_MOPS", "+mops", 650>;
def : FMVExtension<"pmull", "FEAT_PMULL", "+aes,+fp-armv8,+neon", 160>;
def : FMVExtension<"predres", "FEAT_PREDRES", "+predres", 480>;
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 69d6b02fefffe9..748a6f87f94ea4 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -268,11 +268,14 @@ let ArchExtKindSpelling = "AEK_RAND", UserVisibleName = "rng" in
def FeatureRandGen : ExtensionWithMArch<"rand", "RandGen", "FEAT_RNG",
"Enable Random Number generation instructions">;
+def FeatureMTE : Extension<"mte", "MTE", "FEAT_MTE",
+ "Enable Memory Tagging Extension 1">;
+
// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
// __attribute((target(...))), but only FEAT_MTE for FMV.
let UserVisibleName = "memtag" in
-def FeatureMTE : ExtensionWithMArch<"mte", "MTE", "FEAT_MTE, FEAT_MTE2",
- "Enable Memory Tagging Extension">;
+def FeatureMTE2 : ExtensionWithMArch<"mte2", "MTE2", "FEAT_MTE2",
+ "Enable Memory Tagging Extension 2", [FeatureMTE]>;
//===----------------------------------------------------------------------===//
// Armv8.6 Architecture Extensions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 9a2529a9534d09..acc1ebd51b0b25 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -263,6 +263,8 @@ def HasBTI : Predicate<"Subtarget->hasBTI()">,
AssemblerPredicateWithAll<(all_of FeatureBranchTargetId), "bti">;
def HasMTE : Predicate<"Subtarget->hasMTE()">,
AssemblerPredicateWithAll<(all_of FeatureMTE), "mte">;
+def HasMTE2 : Predicate<"Subtarget->hasMTE2()">,
+ AssemblerPredicateWithAll<(all_of FeatureMTE2), "mte2">;
def HasTME : Predicate<"Subtarget->hasTME()">,
AssemblerPredicateWithAll<(all_of FeatureTME), "tme">;
def HasETE : Predicate<"Subtarget->hasETE()">,
@@ -2656,15 +2658,6 @@ def : Pat<(int_aarch64_ldg GPR64:$Rt, (am_indexeds9s128 GPR64sp:$Rn, simm9s16:$
def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
-def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
- (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
-def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
- (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
-def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
- (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
- let Inst{23} = 0;
-}
-
defm STG : MemTagStore<0b00, "stg">;
defm STZG : MemTagStore<0b01, "stzg">;
defm ST2G : MemTagStore<0b10, "st2g">;
@@ -2730,6 +2723,17 @@ def STZGloop
} // Predicates = [HasMTE]
+let Predicates = [HasMTE2] in {
+def LDGM : MemTagVector<1, "ldgm", "\t$Rt, [$Rn]",
+ (outs GPR64:$Rt), (ins GPR64sp:$Rn)>;
+def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
+ (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
+def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
+ (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
+ let Inst{23} = 0;
+}
+} // Predicates = [HasMTE2]
+
//===----------------------------------------------------------------------===//
// Logical instructions.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 1d6c71cbbf0ec3..da06676fa44a23 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -686,7 +686,7 @@ def ProcessorFeatures {
FeatureLSE, FeatureRAS, FeatureRDM];
list<SubtargetFeature> A510 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureMatMulInt8, FeatureBF16, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE2, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeaturePAuth, FeatureSSBS, FeatureSVE, FeatureSVE2,
@@ -694,7 +694,7 @@ def ProcessorFeatures {
FeatureFPARMv8,FeatureFullFP16, FeatureJS, FeatureLSE,
FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE2, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
@@ -703,7 +703,7 @@ def ProcessorFeatures {
FeatureNEON, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureDotProd];
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE2, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
@@ -738,12 +738,12 @@ def ProcessorFeatures {
FeatureSSBS, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
list<SubtargetFeature> A710 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureCCIDX, FeatureSSBS,
- FeatureETE, FeatureMTE, FeatureFP16FML,
+ FeatureETE, FeatureMTE2, FeatureFP16FML,
FeatureSVE2BitPerm, FeatureBF16, FeatureMatMulInt8,
FeaturePAuth, FeatureFlagM, FeatureSB, FeatureSVE, FeatureSVE2,
FeatureComplxNum, FeatureCRC, FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE,
+ list<SubtargetFeature> A715 = [HasV9_0aOps, FeatureNEON, FeatureMTE2,
FeatureCCIDX,
FeatureFP16FML, FeatureSVE, FeatureTRBE,
FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
@@ -753,7 +753,7 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8,
FeatureJS, FeatureLSE, FeatureRAS,
FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE2, FeatureFP16FML,
FeatureCCIDX,
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
@@ -762,7 +762,7 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS,
FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE2, FeatureFP16FML,
FeatureCCIDX,
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
@@ -771,7 +771,7 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureNEON, FeatureRAS,
FeatureRCPC, FeatureRDM];
- list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE2, FeatureFP16FML,
FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
@@ -806,7 +806,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureMatMulInt8, FeatureBF16, FeatureAM,
- FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
+ FeatureMTE2, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML,
FeatureCCIDX,
FeaturePAuth, FeatureSSBS, FeatureSB, FeatureSVE, FeatureSVE2, FeatureFlagM,
@@ -815,7 +815,7 @@ def ProcessorFeatures {
list<SubtargetFeature> X3 = [HasV9_0aOps, FeatureSVE, FeatureNEON,
FeaturePerfMon, FeatureETE, FeatureTRBE,
FeatureSPE, FeatureBF16, FeatureMatMulInt8,
- FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
+ FeatureMTE2, FeatureSVE2BitPerm, FeatureFullFP16,
FeatureFP16FML,
FeatureCCIDX,
FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS,
@@ -823,14 +823,14 @@ def ProcessorFeatures {
FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureDotProd];
list<SubtargetFeature> X4 = [HasV9_2aOps,
FeaturePerfMon, FeatureETE, FeatureTRBE,
- FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
+ FeatureSPE, FeatureMTE2, FeatureSVE2BitPerm,
FeatureFP16FML, FeatureSPE_EEF,
FeatureCCIDX,
FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureComplxNum, FeatureCRC, FeatureDotProd,
FeatureFPARMv8, FeatureFullFP16, FeatureMatMulInt8, FeatureJS, FeatureLSE,
FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureBF16];
- list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
+ list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE2, FeatureFP16FML,
FeatureCCIDX,
FeatureETE, FeaturePerfMon, FeatureSPE,
FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
@@ -927,7 +927,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureSPE, FeatureSSBS,
FeaturePerfMon, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM];
list<SubtargetFeature> NeoverseN2 = [HasV9_0aOps, FeatureBF16, FeatureETE, FeatureFP16FML,
- FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
+ FeatureMatMulInt8, FeatureMTE2, FeatureSVE2,
FeatureSVE2BitPerm, FeatureTRBE,
FeaturePerfMon,
FeatureCCIDX,
@@ -935,7 +935,7 @@ def ProcessorFeatures {
FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
FeatureNEON, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
- FeatureFullFP16, FeatureMTE, FeaturePerfMon,
+ FeatureFullFP16, FeatureMTE2, FeaturePerfMon,
FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
FeatureSVE2BitPerm,
FeatureCCIDX,
@@ -965,13 +965,13 @@ def ProcessorFeatures {
list<SubtargetFeature> NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE,
FeaturePerfMon, FeatureETE, FeatureMatMulInt8,
FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML,
- FeatureMTE, FeatureRandGen,
+ FeatureMTE2, FeatureRandGen,
FeatureCCIDX,
FeatureSVE, FeatureSVE2, FeatureSSBS, FeatureFullFP16, FeatureDotProd,
FeatureComplxNum, FeatureCRC, FeatureFPARMv8, FeatureJS, FeatureLSE,
FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
- FeatureFullFP16, FeatureLS64, FeatureMTE,
+ FeatureFullFP16, FeatureLS64, FeatureMTE2,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureCCIDX,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
@@ -980,7 +980,7 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS, FeatureLSE,
FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM, FeatureRME];
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
- FeatureFullFP16, FeatureLS64, FeatureMTE,
+ FeatureFullFP16, FeatureLS64, FeatureMTE2,
FeaturePerfMon, FeatureRandGen, FeatureSPE,
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
@@ -1016,7 +1016,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC, FeatureRDM];
list<SubtargetFeature> Ampere1A = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
- FeatureMTE, FeatureSSBS, FeatureRandGen,
+ FeatureMTE2, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES,
FeatureFullFP16, FeatureBF16, FeatureComplxNum,
@@ -1025,7 +1025,7 @@ def ProcessorFeatures {
FeatureCCIDX,
FeatureRDM];
list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
- FeatureMTE, FeatureSSBS, FeatureRandGen,
+ FeatureMTE2, FeatureSSBS, FeatureRandGen,
FeatureSB, FeatureSM4, FeatureSHA2,
FeatureSHA3, FeatureAES, FeatureCSSC,
FeatureWFxT, FeatureFullFP16, FeatureBF16, FeatureComplxNum,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index c714bad92b7fbb..d46a10a299bbdc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -29,7 +29,8 @@ def CortexA53Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA55.td b/llvm/lib/Target/AArch64/AArch64SchedA55.td
index cb77be350d1244..c69b74cc42ebe8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA55.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA55.td
@@ -29,7 +29,7 @@ def CortexA55Model : SchedMachineModel {
let PostRAScheduler = 1; // Enable PostRA scheduler pass.
let CompleteModel = 0; // Covers instructions applicable to Cortex-A55.
- list<Predicate> UnsupportedFeatures = [HasSVE, HasMTE];
+ list<Predicate> UnsupportedFeatures = !listconcat(MTEUnsupported.F, [HasSVE]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index ebbc3b72b50609..25cd6efeeb0d25 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -34,7 +34,8 @@ def CortexA57Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index d6fe84a2c9c9b4..762a5a770a27a8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -21,9 +21,9 @@ def A64FXModel : SchedMachineModel {
let CompleteModel = 1;
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
- [HasMTE, HasMatMulInt8, HasBF16,
- HasPAuth, HasPAuthLR, HasCPA,
- HasCSSC]);
+ MTEUnsupported.F, [HasMatMulInt8,
+ HasBF16, HasPAuth, HasPAuthLR,
+ HasCPA, HasCSSC]);
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
index 269f4ec5e5fb16..c028d7d39e0ee5 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
@@ -27,7 +27,7 @@ def Ampere1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
SMEUnsupported.F,
PAUnsupported.F,
- [HasMTE]);
+ MTEUnsupported.F);
}
let SchedModel = Ampere1Model in {
diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
index 48324654949c06..9d0619cc541004 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
@@ -21,7 +21,8 @@ def CycloneModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 6fc4ec3ae41b77..9bca9b032be7bc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -27,7 +27,8 @@ def ExynosM3Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index b75264602dbc11..a3b42a96594061 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -27,7 +27,8 @@ def ExynosM4Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
index 6b5a6da76b3a81..a2139d0fdd9585 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
@@ -27,7 +27,8 @@ def ExynosM5Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
index e9172e82b099d1..c5e250b8ae9a64 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
@@ -26,7 +26,8 @@ def FalkorModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
index 258b34c38898cd..7b5dc18f839d4b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
@@ -30,7 +30,8 @@ def KryoModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
index 524fa33f498bb0..f3e7302ed3f990 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
@@ -25,7 +25,8 @@ def NeoverseN1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(PAUnsupported.F,
SMEUnsupported.F,
SVEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index f7e6545f0dd386..2d310871ba1076 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -28,8 +28,8 @@ def NeoverseV1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCPA,
- HasCSSC]);
+ MTEUnsupported.F,
+ [HasCPA, HasCSSC]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
index 1c577a25bf7390..d91864877c9aea 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -27,7 +27,8 @@ def TSV110Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
}
// Define each kind of processor resource and number available on the TSV110,
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
index 8df3f56e45738c..4398cb1f392b3d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
@@ -28,7 +28,8 @@ def ThunderXT8XModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
index ef4baa3dedff93..b149f1e5dfae65 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
@@ -28,7 +28,8 @@ def ThunderX2T99Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
index 796bd4b8b5c9ae..8fe47f7d62a78d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -27,7 +27,8 @@ def ThunderX3T110Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC]);
+ MTEUnsupported.F,
+ [HasCSSC]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index dd0ce1cf47a792..28d46ef7cf7679 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -152,19 +152,11 @@ let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;
let Requires = [{ {AArch64::FeatureMTE} }] in {
-def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;
-def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;
-def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>;
-def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>;
def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>;
def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>;
def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>;
def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>;
def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>;
-def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;
-def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;
-def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>;
-def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>;
def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>;
def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;
def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;
@@ -172,6 +164,17 @@ def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
}
+let Requires = [{ {AArch64::FeatureMTE2} }] in {
+def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;
+def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;
+def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>;
+def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>;
+def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;
+def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;
+def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>;
+def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>;
+}
+
let Requires = [{ {AArch64::FeatureMEC} }] in {
def : DC<"CIPAE", 0b100, 0b0111, 0b1110, 0b000>;
def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;
@@ -1639,8 +1642,9 @@ def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
// v8.5a Memory Tagging Extension
// Op0 Op1 CRn CRm Op2
-let Requires = [{ {AArch64::FeatureMTE} }] in {
+let Requires = [{ {AArch64::FeatureMTE} }] in
def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>;
+let Requires = [{ {AArch64::FeatureMTE2} }] in {
def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>;
def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>;
def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>;
@@ -1649,7 +1653,7 @@ def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>;
def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>;
def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>;
def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>;
-} // HasMTE
+}
// Embedded Trace Extension R/W System registers
let Requires = [{ {AArch64::FeatureETE} }] in {
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 4f6131fd835577..89b9fb4e414970 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -3666,7 +3666,8 @@ static const struct Extension {
{"predres2", {AArch64::FeatureSPECRES2}},
{"ccdp", {AArch64::FeatureCacheDeepPersist}},
{"mte", {AArch64::FeatureMTE}},
- {"memtag", {AArch64::FeatureMTE}},
+ {"mte2", {AArch64::FeatureMTE2}},
+ {"memtag", {AArch64::FeatureMTE, AArch64::FeatureMTE2}},
{"tlb-rmi", {AArch64::FeatureTLB_RMI}},
{"pan", {AArch64::FeaturePAN}},
{"pan-rwv", {AArch64::FeaturePAN_RWV}},
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 9fc7201efac6e2..f81b11c8d40002 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -253,6 +253,12 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
disable(AEK_SM4);
}
+ // FEAT_MTE and FEAT_MTE2 were historically lumped under the name 'memtag'.
+ // Therefore 'nomemtag' should disable FEAT_MTE too even though it does not
+ // depend on FEAT_MTE2.
+ if (E == AEK_MTE2)
+ disable(AEK_MTE);
+
if (!Enabled.test(E))
return;
diff --git a/llvm/test/MC/AArch64/armv8.5a-mte-error.s b/llvm/test/MC/AArch64/armv8.5a-mte-error.s
index 07b4a19660d489..8f45d79130ffa4 100644
--- a/llvm/test/MC/AArch64/armv8.5a-mte-error.s
+++ b/llvm/test/MC/AArch64/armv8.5a-mte-error.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s 2>&1| FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+mte2 < %s 2>&1| FileCheck %s
irg
irg x0
diff --git a/llvm/test/MC/AArch64/armv8.5a-mte.s b/llvm/test/MC/AArch64/armv8.5a-mte.s
index 6fa12476b225d1..332276a30e5d7c 100644
--- a/llvm/test/MC/AArch64/armv8.5a-mte.s
+++ b/llvm/test/MC/AArch64/armv8.5a-mte.s
@@ -1,6 +1,6 @@
-// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+mte2 < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
-// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-mte < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-mte2 < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
irg x0, x1
irg sp, x1
@@ -441,19 +441,19 @@ dc gzva, x17
// CHECK: dc cigdvac, x16 // encoding: [0xb0,0x7e,0x0b,0xd5]
// CHECK: dc gzva, x17 // encoding: [0x91,0x74,0x0b,0xd5]
-// NOMTE: DC IGVAC requires: mte
-// NOMTE: DC IGSW requires: mte
-// NOMTE: DC CGSW requires: mte
-// NOMTE: DC CIGSW requires: mte
+// NOMTE: DC IGVAC requires: mte2
+// NOMTE: DC IGSW requires: mte2
+// NOMTE: DC CGSW requires: mte2
+// NOMTE: DC CIGSW requires: mte2
// NOMTE: DC CGVAC requires: mte
// NOMTE: DC CGVAP requires: mte
// NOMTE: DC CGVADP requires: mte
// NOMTE: DC CIGVAC requires: mte
// NOMTE: DC GVA requires: mte
-// NOMTE: DC IGDVAC requires: mte
-// NOMTE: DC IGDSW requires: mte
-// NOMTE: DC CGDSW requires: mte
-// NOMTE: DC CIGDSW requires: mte
+// NOMTE: DC IGDVAC requires: mte2
+// NOMTE: DC IGDSW requires: mte2
+// NOMTE: DC CGDSW requires: mte2
+// NOMTE: DC CIGDSW requires: mte2
// NOMTE: DC CGDVAC requires: mte
// NOMTE: DC CGDVAP requires: mte
// NOMTE: DC CGDVADP requires: mte
@@ -590,9 +590,9 @@ ldgm xzr, [x2]
// CHECK: ldgm x1, [sp] // encoding: [0xe1,0x03,0xe0,0xd9]
// CHECK: ldgm xzr, [x2] // encoding: [0x5f,0x00,0xe0,0xd9]
-// NOMTE: instruction requires: mte
-// NOMTE: instruction requires: mte
-// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte2
+// NOMTE: instruction requires: mte2
+// NOMTE: instruction requires: mte2
stgm x0, [x1]
stgm x1, [sp]
@@ -602,9 +602,9 @@ stgm xzr, [x2]
// CHECK: stgm x1, [sp] // encoding: [0xe1,0x03,0xa0,0xd9]
// CHECK: stgm xzr, [x2] // encoding: [0x5f,0x00,0xa0,0xd9]
-// NOMTE: instruction requires: mte
-// NOMTE: instruction requires: mte
-// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte2
+// NOMTE: instruction requires: mte2
+// NOMTE: instruction requires: mte2
stzgm x0, [x1]
stzgm x1, [sp]
@@ -614,6 +614,6 @@ stzgm xzr, [x2]
// CHECK: stzgm x1, [sp] // encoding: [0xe1,0x03,0x20,0xd9]
// CHECK: stzgm xzr, [x2] // encoding: [0x5f,0x00,0x20,0xd9]
-// NOMTE: instruction requires: mte
-// NOMTE: instruction requires: mte
-// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte2
+// NOMTE: instruction requires: mte2
+// NOMTE: instruction requires: mte2
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 1843af56555461..b9d0e97d8887f6 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -1,5 +1,5 @@
// RUN: not llvm-mc -triple aarch64 \
-// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
+// RUN: -mattr=+crc,+sm4,+sha3,+sha2,+aes,+fp,+neon,+ras,+lse,+predres,+ccdp,+mte2,+tlb-rmi,+pan-rwv,+ccpp,+rcpc,+ls64,+flagm,+hbc,+mops \
// RUN: -mattr=+rcpc3,+lse128,+d128,+the,+rasv2,+ite,+cssc,+specres2,+gcs \
// RUN: -filetype asm -o - %s 2>&1 | FileCheck %s
@@ -106,10 +106,15 @@ dc cvadp, x7
irg x0, x1
// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: mte
-.arch_extension nomte
+ldgm x0, [x1]
+// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: mte2
+.arch_extension nomemtag
irg x0, x1
// CHECK: [[@LINE-1]]:1: error: instruction requires: mte
// CHECK-NEXT: irg x0, x1
+ldgm x0, [x1]
+// CHECK: [[@LINE-1]]:1: error: instruction requires: mte2
+// CHECK-NEXT: ldgm x0, [x1]
tlbi vmalle1os
// CHECK-NOT: [[@LINE-1]]:6: error: TLBI VMALLE1OS requires: tlb-rmi
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
index f93aae235abcd2..983d012189fb66 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+mte2 -disassemble < %s | FileCheck %s
# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
-# RUN: not llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+# RUN: not llvm-mc -triple=aarch64 -mattr=-mte2 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
[0x20,0x10,0xdf,0x9a]
[0x3f,0x10,0xdf,0x9a]
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 13db80ab5c68ea..34304e7707f23d 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1293,7 +1293,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SVE2, AArch64::AEK_SVE2AES,
AArch64::AEK_SVE2SM4, AArch64::AEK_SVE2SHA3,
AArch64::AEK_SVE2BITPERM, AArch64::AEK_RCPC,
- AArch64::AEK_RAND, AArch64::AEK_MTE,
+ AArch64::AEK_RAND, AArch64::AEK_SVEB16B16,
AArch64::AEK_SSBS, AArch64::AEK_SB,
AArch64::AEK_PREDRES, AArch64::AEK_BF16,
AArch64::AEK_I8MM, AArch64::AEK_F32MM,
@@ -1319,7 +1319,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_CPA, AArch64::AEK_PAUTHLR,
AArch64::AEK_TLBIW, AArch64::AEK_JSCVT,
AArch64::AEK_FCMA, AArch64::AEK_FP8,
- AArch64::AEK_SVEB16B16,
+ AArch64::AEK_MTE, AArch64::AEK_MTE2,
};
std::vector<StringRef> Features;
@@ -1361,6 +1361,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+rcpc"));
EXPECT_TRUE(llvm::is_contained(Features, "+rand"));
EXPECT_TRUE(llvm::is_contained(Features, "+mte"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+mte2"));
EXPECT_TRUE(llvm::is_contained(Features, "+ssbs"));
EXPECT_TRUE(llvm::is_contained(Features, "+sb"));
EXPECT_TRUE(llvm::is_contained(Features, "+predres"));
@@ -1513,7 +1514,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
{"rcpc", "norcpc", "+rcpc", "-rcpc"},
{"rng", "norng", "+rand", "-rand"},
- {"memtag", "nomemtag", "+mte", "-mte"},
+ {"memtag", "nomemtag", "+mte2", "-mte2"},
{"tme", "notme", "+tme", "-tme"},
{"pauth", "nopauth", "+pauth", "-pauth"},
{"ssbs", "nossbs", "+ssbs", "-ssbs"},
@@ -1898,7 +1899,7 @@ AArch64ExtensionDependenciesBaseCPUTestParams
{"cortex-a520",
{},
{"v9.2a", "bf16", "crc", "dotprod", "flagm", "fp-armv8",
- "fullfp16", "fp16fml", "i8mm", "lse", "mte", "pauth",
+ "fullfp16", "fp16fml", "i8mm", "lse", "mte2", "pauth",
"perfmon", "predres", "ras", "rcpc", "rdm", "sb",
"neon", "ssbs", "sve", "sve2-bitperm", "sve2"},
{}},
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