[clang] [llvm] [RISCV][VCIX] Add vcix_state to GNU inline assembly register set (PR #106914)

Brandon Wu via cfe-commits cfe-commits at lists.llvm.org
Wed Sep 11 00:33:25 PDT 2024


================
@@ -44,7 +44,7 @@ ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
       "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
 
       // CSRs
-      "fflags", "frm", "vtype", "vl", "vxsat", "vxrm"
+      "fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf_vcix_state"
----------------
4vtomat wrote:

```
#include <riscv_vector.h>
#include <sifive_vector.h>


int foo(__rvv_uint64m1_t vreg) {

  auto vl = __riscv_vsetvl_e64m1(1);

  // This VCIX instruction gets scheduled after the asm block below.
  __riscv_sf_vc_iv_se_u64m1(0, 0, vreg, 0, vl);

  asm volatile(
      R"(
        vsetivli zero, 2, e64, m1, ta, ma
        sf.vc.vv 0x3, 0x0, %[vreg], %[vreg];
      )"
      : "=r"(vl)
      : [vreg]"vr"(vreg)
      : "memory", "vl", "sf_vcix_state");

  return 0;
}
```
Use the code above as an example, it compiles to the llvm:
```
  define dso_local noundef signext i32 @_Z3foou16__rvv_uint64m1_t(<vscale x 1 x i64> %vreg) local_unnamed_addr #0 {
  entry:
    %0 = tail call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 3, i64 0)
    tail call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i64.i64.i64(i64 0, i64 0, <vscale x 1 x i64> %vreg, i64 0, i64 %0)
    %1 = tail call i64 asm sideeffect "\0A        vsetivli zero, 2, e64, m1, ta, ma\0A        sf.vc.vv 0x3, 0x0, $1, $1;\0A      ", "=r,^vr,~{memory},~{vl},~{sf_vcix_state}"(<vscale x 1 x i64> %vreg)
    ret i32 0
  }
```

if we change `sf_vcix_state` to `sf.vcix_state`, the code doesn't work as expected, the instruction is still reordered, so I doubt that the name here is the defining name of the register in `RISCVRegisterInfo.td` rather than the actually name of the register.


https://github.com/llvm/llvm-project/pull/106914


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