[clang] [llvm] Double run offloading (PR #107834)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Sep 9 03:05:34 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-llvm-transforms
Author: Aleksei Romanov (saveasguy)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/107834.diff
11 Files Affected:
- (modified) clang/include/clang/Driver/Options.td (+6)
- (modified) clang/lib/Driver/Driver.cpp (+60)
- (added) llvm/include/llvm/Transforms/Scalar/LVN.h (+18)
- (modified) llvm/lib/Passes/PassBuilder.cpp (+1)
- (modified) llvm/lib/Passes/PassRegistry.def (+1)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+10-3)
- (modified) llvm/lib/Transforms/Scalar/CMakeLists.txt (+1)
- (added) llvm/lib/Transforms/Scalar/LVN.cpp (+50)
- (modified) llvm/test/MC/RISCV/rvv/invalid.s (+26-26)
- (modified) llvm/test/MC/RISCV/rvv/vsetvl.s (+6)
- (added) llvm/test/Transforms/LVN/basic_tests.ll (+62)
``````````diff
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 553c7928c4f949..0363f34ed790e1 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6118,6 +6118,12 @@ def fno_sycl : Flag<["-"], "fno-sycl">, Flags<[NoXarchOption]>,
Visibility<[ClangOption, CLOption]>,
Group<sycl_Group>, HelpText<"Disables SYCL kernels compilation for device">;
+// double run options
+def fdoublerun : Flag<["-"], "fdoublerun">,
+ Group<f_Group>, HelpText<"Enables double run">;
+def fno_doublerun : Flag<["-"], "fno-doublerun">,
+ Group<f_Group>, HelpText<"Disables double run">;
+
//===----------------------------------------------------------------------===//
// FLangOption + NoXarchOption
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 84b8fc7685fed4..c5794e9644e5bf 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -2865,6 +2865,64 @@ class OffloadingActionBuilder final {
}
};
+ class MyActionBuilder : public DeviceActionBuilder {
+ Action *FirstRunAction;
+ public:
+ MyActionBuilder(Compilation &C, DerivedArgList &Args,
+ const Driver::InputList &Inputs)
+ : DeviceActionBuilder(C, Args, Inputs, Action::OFK_Host) {}
+
+ bool initialize() override {
+ if (Args.hasFlag(options::OPT_fdoublerun, options::OPT_fno_doublerun,
+ false)) {
+ const ToolChain *TC =
+ C.getSingleOffloadToolChain<Action::OFK_Host>();
+ ToolChains.push_back(TC);
+ return false;
+ }
+ return true;
+ }
+
+ ActionBuilderReturnCode addDeviceDependences(Action *HostAction) override {
+ if (auto *IA = dyn_cast<InputAction>(HostAction)) {
+ FirstRunAction = C.MakeAction<InputAction>(
+ IA->getInputArg(), IA->getType(), IA->getId());
+ return ABRT_Success;
+ }
+ return ABRT_Inactive;
+ }
+
+ ActionBuilderReturnCode
+ getDeviceDependences(OffloadAction::DeviceDependences &DA,
+ phases::ID CurPhase, phases::ID FinalPhase,
+ PhasesTy &Phases) override {
+ if (CurPhase != phases::Backend)
+ return ABRT_Inactive;
+
+ assert(FirstRunAction);
+ Action *PrevFirstRunAction = FirstRunAction;
+ for (auto Ph : Phases) {
+ if (Ph > CurPhase)
+ break;
+ FirstRunAction = C.getDriver().ConstructPhaseAction(C, Args, Ph, FirstRunAction);
+ // FirstRunAction
+ }
+ if (PrevFirstRunAction == FirstRunAction)
+ return ABRT_Inactive;
+ DA.add(*FirstRunAction, *ToolChains.front(), ToolChains.front()->getArchName().data(), Action::OFK_Host);
+ return ABRT_Success;
+ }
+
+ StringRef getCanonicalOffloadArch(StringRef Arch) {
+ return Arch;
+ }
+
+ std::optional<std::pair<StringRef, StringRef>>
+ getConflictOffloadArchCombination(const std::set<StringRef> &ArchSet) {
+ return std::nullopt;
+ }
+ };
+
/// Base class for CUDA/HIP action builder. It injects device code in
/// the host backend action.
class CudaActionBuilderBase : public DeviceActionBuilder {
@@ -3612,6 +3670,8 @@ class OffloadingActionBuilder final {
// Create a specialized builder for HIP.
SpecializedBuilders.push_back(new HIPActionBuilder(C, Args, Inputs));
+ SpecializedBuilders.push_back(new MyActionBuilder(C, Args, Inputs));
+
//
// TODO: Build other specialized builders here.
//
diff --git a/llvm/include/llvm/Transforms/Scalar/LVN.h b/llvm/include/llvm/Transforms/Scalar/LVN.h
new file mode 100644
index 00000000000000..de6feed0fc8837
--- /dev/null
+++ b/llvm/include/llvm/Transforms/Scalar/LVN.h
@@ -0,0 +1,18 @@
+#ifndef LLVM_TRANSFORMS_SCALAR_LVN_H
+#define LLVM_TRANSFORMS_SCALAR_LVN_H
+
+#include "llvm/IR/PassManager.h"
+
+namespace llvm {
+
+class LVNPass : public PassInfoMixin<LVNPass> {
+public:
+ PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
+
+private:
+ void runOnBasicBlock(BasicBlock &BB);
+};
+
+} // end namespace llvm
+
+#endif // LLVM_TRANSFORMS_SCALAR_LVN_H
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 5c7f26109930c9..dc99c9408a20cd 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -201,6 +201,7 @@
#include "llvm/Transforms/Scalar/LowerGuardIntrinsic.h"
#include "llvm/Transforms/Scalar/LowerMatrixIntrinsics.h"
#include "llvm/Transforms/Scalar/LowerWidenableCondition.h"
+#include "llvm/Transforms/Scalar/LVN.h"
#include "llvm/Transforms/Scalar/MakeGuardsExplicit.h"
#include "llvm/Transforms/Scalar/MemCpyOptimizer.h"
#include "llvm/Transforms/Scalar/MergeICmps.h"
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index b9aa015d02dd95..1729eb6120db72 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -358,6 +358,7 @@ FUNCTION_PASS("loop-simplify", LoopSimplifyPass())
FUNCTION_PASS("loop-sink", LoopSinkPass())
FUNCTION_PASS("lowerinvoke", LowerInvokePass())
FUNCTION_PASS("lowerswitch", LowerSwitchPass())
+FUNCTION_PASS("lvn", LVNPass())
FUNCTION_PASS("mem2reg", PromotePass())
FUNCTION_PASS("memcpyopt", MemCpyOptPass())
FUNCTION_PASS("mergeicmps", MergeICmpsPass())
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7d8d82e381313b..ad9ca703e48bdf 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2102,8 +2102,15 @@ bool RISCVAsmParser::parseVTypeToken(StringRef Identifier, VTypeState &State,
State = VTypeState_LMUL;
return false;
case VTypeState_LMUL: {
- if (!Identifier.consume_front("m"))
- break;
+ if (!Identifier.consume_front("m")) {
+ Lmul = 1;
+ Fractional = false;
+ State = VTypeState_TailPolicy;
+ // Intentionally fall through parsing step
+ // since LMUL is omitted
+ return parseVTypeToken(Identifier, State, Sew, Lmul, Fractional,
+ TailAgnostic, MaskAgnostic);
+ }
Fractional = Identifier.consume_front("f");
if (Identifier.getAsInteger(10, Lmul))
break;
@@ -2189,7 +2196,7 @@ bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
return Error(
ErrorLoc,
"operand must be "
- "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
+ "e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
}
ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
diff --git a/llvm/lib/Transforms/Scalar/CMakeLists.txt b/llvm/lib/Transforms/Scalar/CMakeLists.txt
index eb008c15903a74..1f39809420e4c7 100644
--- a/llvm/lib/Transforms/Scalar/CMakeLists.txt
+++ b/llvm/lib/Transforms/Scalar/CMakeLists.txt
@@ -52,6 +52,7 @@ add_llvm_component_library(LLVMScalarOpts
LowerGuardIntrinsic.cpp
LowerMatrixIntrinsics.cpp
LowerWidenableCondition.cpp
+ LVN.cpp
MakeGuardsExplicit.cpp
MemCpyOptimizer.cpp
MergeICmps.cpp
diff --git a/llvm/lib/Transforms/Scalar/LVN.cpp b/llvm/lib/Transforms/Scalar/LVN.cpp
new file mode 100644
index 00000000000000..e774e6a472e6d9
--- /dev/null
+++ b/llvm/lib/Transforms/Scalar/LVN.cpp
@@ -0,0 +1,50 @@
+#include "llvm/Transforms/Scalar/LVN.h"
+
+#include <cstdint>
+#include <tuple>
+#include <unordered_map>
+
+#include "llvm/IR/InstrTypes.h"
+
+using namespace llvm;
+
+namespace {
+
+using InstrTupleTy = std::tuple<Instruction::BinaryOps, Value *, Value *>;
+
+struct InstrTupleHash {
+ size_t operator()(const InstrTupleTy &InstrTuple) const {
+ auto LHSPtrVal = reinterpret_cast<uintptr_t>(std::get<1>(InstrTuple));
+ auto RHSPtrVal = reinterpret_cast<uintptr_t>(std::get<2>(InstrTuple));
+ return std::get<0>(InstrTuple) ^ LHSPtrVal * RHSPtrVal;
+ }
+};
+
+} // end namespace
+
+PreservedAnalyses LVNPass::run(Function &F, FunctionAnalysisManager &FAM) {
+ for (auto &BB : F) {
+ runOnBasicBlock(BB);
+ }
+ return PreservedAnalyses::all();
+}
+
+void LVNPass::runOnBasicBlock(BasicBlock &BB) {
+ std::unordered_map<InstrTupleTy, Value *, InstrTupleHash> InstrToValue;
+ for (auto &I : BB) {
+ BinaryOperator *BO = dyn_cast<BinaryOperator>(&I);
+ if (!BO) {
+ continue;
+ }
+ Value *RHS = BO->getOperand(0);
+ Value *LHS = BO->getOperand(1);
+ auto InstrTuple = std::make_tuple(BO->getOpcode(), RHS, LHS);
+ Value *BOValue = static_cast<Value *>(BO);
+ auto FoundInstrIt = InstrToValue.find(InstrTuple);
+ if (FoundInstrIt == InstrToValue.end()) {
+ InstrToValue.insert({InstrTuple, BOValue});
+ } else {
+ BO->replaceAllUsesWith(FoundInstrIt->second);
+ }
+ }
+}
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index 09fd2c3bebf035..c6a405cc38f8c5 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -2,83 +2,83 @@
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
vsetivli a2, 32, e8,m1
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetivli a2, zero, e8,m1
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetivli a2, 5, (1 << 10)
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetivli a2, 5, 0x400
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetivli a2, 5, e31
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, (1 << 11)
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, 0x800
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e31
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e32,m3
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, m1,e32
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e32,m16
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e2048,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e1,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,tx
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,ta,mx
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,ma
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,mu
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8x,m1,tu,mu
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1z,tu,mu
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,mf1,tu,mu
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,tu,mut
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,tut,mu
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,m1,ta
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vsetvli a2, a0, e8,1,ta,ma
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],[m[1|2|4|8|f2|f4|f8],][ta|tu],[ma|mu]
vadd.vv v1, v3, v2, v4.t
# CHECK-ERROR: operand must be v0.t
diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s
index bdf0553841b9ce..b0a31e79a2ab13 100644
--- a/llvm/test/MC/RISCV/rvv/vsetvl.s
+++ b/llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -45,6 +45,12 @@ vsetvli a2, a0, 144
# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
# CHECK-UNKNOWN: 57 76 05 09 <unknown>
+vsetvli a2, a0, e32, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma
+# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
+# CHECK-UNKNOWN: 57 76 05 0d <unknown>
+
vsetvli a2, a0, e32, m1, ta, ma
# CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
diff --git a/llvm/test/Transforms/LVN/basic_tests.ll b/llvm/test/Transforms/LVN/basic_tests.ll
new file mode 100644
index 00000000000000..3c1902d0c7501b
--- /dev/null
+++ b/llvm/test/Transforms/LVN/basic_tests.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; RUN: opt -passes='lvn,dce' -S < %s | FileCheck %s
+
+define i32 @redundant_add(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: define i32 @redundant_add(
+; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[A]], [[B]]
+; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[B]], [[C]]
+; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[ADD]], [[MUL]]
+; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[MUL2]], [[ADD]]
+; CHECK-NEXT: ret i32 [[ADD2]]
+;
+entry:
+ %add = add i32 %a, %b
+ %mul = mul i32 %b, %c
+ %add1 = add i32 %a, %b
+ %mul2 = mul i32 %add, %mul
+ %add2 = add i32 %mul2, %add1
+ ret i32 %add2
+}
+
+define i32 @redundant_mul(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
+; CHECK-LABEL: define i32 @redundant_mul(
+; CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[A]], [[B]]
+; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[B]], [[C]]
+; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[ADD]], [[MUL]]
+; CHECK-NEXT: [[ADD1:%.*]] = add i32 [[MUL2]], [[MUL]]
+; CHECK-NEXT: ret i32 [[ADD1]]
+;
+entry:
+ %add = add i32 %a, %b
+ %mul = mul i32 %b, %c
+ %mul1 = mul i32 %b, %c
+ %mul2 = mul i32 %add, %mul
+ %add1 = add i32 %mul2, %mul1
+ ret i32 %add1
+}
+
+define i32 @redundant_add_x2(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
+; CHECK-LABEL: define i32 @redundant_add_x2(
+; CHECK-SAME: i32 noundef [[A:%.*]], i32 noundef [[B:%.*]], i32 noundef [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[A]], [[B]]
+; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[B]], [[C]]
+; CHECK-NEXT: [[MUL2:%.*]] = mul i32 [[ADD]], [[MUL]]
+; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[MUL2]], [[ADD]]
+; CHECK-NEXT: [[ADD4:%.*]] = add i32 [[ADD2]], [[ADD]]
+; CHECK-NEXT: ret i32 [[ADD4]]
+;
+entry:
+ %add = add i32 %a, %b
+ %mul = mul i32 %b, %c
+ %add1 = add i32 %a, %b
+ %mul2 = mul i32 %add, %mul
+ %add2 = add i32 %mul2, %add1
+ %add3 = add i32 %a, %b
+ %add4 = add i32 %add2, %add3
+ ret i32 %add4
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/107834
More information about the cfe-commits
mailing list