[clang] [llvm] fix kcfi doesn't take effect when callee function has no input parameter (PR #106677)
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cfe-commits at lists.llvm.org
Fri Aug 30 02:39:34 PDT 2024
https://github.com/Zhenhang1213 updated https://github.com/llvm/llvm-project/pull/106677
>From ed682daff12596b12d03e5d0342d0514e29e9896 Mon Sep 17 00:00:00 2001
From: Austin <zhenhangwang at huawei.com>
Date: Fri, 30 Aug 2024 15:21:12 +0800
Subject: [PATCH] fix kcfi doesn't take effect when callee function has no
input parameter
---
clang/lib/CodeGen/CodeGenFunction.cpp | 5 ++
llvm/test/CodeGen/ARM/vmov.ll | 92 +++++++++++++--------------
2 files changed, 51 insertions(+), 46 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index c89eaa0f4e3bfc..4d3fb780243022 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2813,6 +2813,11 @@ void CodeGenFunction::EmitKCFIOperandBundle(
Callee.getAbstractInfo().getCalleeFunctionProtoType();
if (FP)
Bundles.emplace_back("kcfi", CGM.CreateKCFITypeId(FP->desugar()));
+ else {
+ ASTContext &context = this->getContext();
+ QualType voidType = context.VoidTy;
+ Bundles.emplace_back("kcfi", CGM.CreateKCFITypeId(voidType));
+ }
}
llvm::Value *CodeGenFunction::FormAArch64ResolverCondition(
diff --git a/llvm/test/CodeGen/ARM/vmov.ll b/llvm/test/CodeGen/ARM/vmov.ll
index 8835497669b324..86f90869fe7146 100644
--- a/llvm/test/CodeGen/ARM/vmov.ll
+++ b/llvm/test/CodeGen/ARM/vmov.ll
@@ -7,7 +7,7 @@ define arm_aapcs_vfpcc <8 x i8> @v_movi8() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d0, #0x8
; CHECK-NEXT: mov pc, lr
- ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define arm_aapcs_vfpcc <4 x i16> @v_movi16a() nounwind {
@@ -15,7 +15,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_movi16a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d0, #0x10
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
+ ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
}
define arm_aapcs_vfpcc <4 x i16> @v_movi16b() nounwind {
@@ -23,7 +23,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_movi16b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d0, #0x1000
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
+ ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
}
define arm_aapcs_vfpcc <4 x i16> @v_mvni16a() nounwind {
@@ -31,7 +31,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_mvni16a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d0, #0x10
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
+ ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
}
define arm_aapcs_vfpcc <4 x i16> @v_mvni16b() nounwind {
@@ -39,7 +39,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_mvni16b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d0, #0x1000
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
+ ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32a() nounwind {
@@ -47,7 +47,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 32, i32 32 >
+ ret <2 x i32> < i32 32, i32 32 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32b() nounwind {
@@ -55,7 +55,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x2000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 8192, i32 8192 >
+ ret <2 x i32> < i32 8192, i32 8192 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32c() nounwind {
@@ -63,7 +63,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32c() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x200000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 2097152, i32 2097152 >
+ ret <2 x i32> < i32 2097152, i32 2097152 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32d() nounwind {
@@ -71,7 +71,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32d() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20000000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 536870912, i32 536870912 >
+ ret <2 x i32> < i32 536870912, i32 536870912 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32e() nounwind {
@@ -79,7 +79,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32e() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20ff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 8447, i32 8447 >
+ ret <2 x i32> < i32 8447, i32 8447 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32f() nounwind {
@@ -87,7 +87,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32f() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20ffff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 2162687, i32 2162687 >
+ ret <2 x i32> < i32 2162687, i32 2162687 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32a() nounwind {
@@ -95,7 +95,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4294967263, i32 4294967263 >
+ ret <2 x i32> < i32 4294967263, i32 4294967263 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32b() nounwind {
@@ -103,7 +103,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x2000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4294959103, i32 4294959103 >
+ ret <2 x i32> < i32 4294959103, i32 4294959103 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32c() nounwind {
@@ -111,7 +111,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32c() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x200000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4292870143, i32 4292870143 >
+ ret <2 x i32> < i32 4292870143, i32 4292870143 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32d() nounwind {
@@ -119,7 +119,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32d() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20000000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 3758096383, i32 3758096383 >
+ ret <2 x i32> < i32 3758096383, i32 3758096383 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32e() nounwind {
@@ -127,7 +127,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32e() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20ff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4294958848, i32 4294958848 >
+ ret <2 x i32> < i32 4294958848, i32 4294958848 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32f() nounwind {
@@ -135,7 +135,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32f() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20ffff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4292804608, i32 4292804608 >
+ ret <2 x i32> < i32 4292804608, i32 4292804608 >
}
define arm_aapcs_vfpcc <1 x i64> @v_movi64() nounwind {
@@ -143,7 +143,7 @@ define arm_aapcs_vfpcc <1 x i64> @v_movi64() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i64 d0, #0xff0000ff0000ffff
; CHECK-NEXT: mov pc, lr
- ret <1 x i64> < i64 18374687574888349695 >
+ ret <1 x i64> < i64 18374687574888349695 >
}
define arm_aapcs_vfpcc <16 x i8> @v_movQi8() nounwind {
@@ -151,7 +151,7 @@ define arm_aapcs_vfpcc <16 x i8> @v_movQi8() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q0, #0x8
; CHECK-NEXT: mov pc, lr
- ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define arm_aapcs_vfpcc <8 x i16> @v_movQi16a() nounwind {
@@ -159,7 +159,7 @@ define arm_aapcs_vfpcc <8 x i16> @v_movQi16a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q0, #0x10
; CHECK-NEXT: mov pc, lr
- ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+ ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
define arm_aapcs_vfpcc <8 x i16> @v_movQi16b() nounwind {
@@ -167,7 +167,7 @@ define arm_aapcs_vfpcc <8 x i16> @v_movQi16b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q0, #0x1000
; CHECK-NEXT: mov pc, lr
- ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
+ ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32a() nounwind {
@@ -175,7 +175,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
+ ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32b() nounwind {
@@ -183,7 +183,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x2000
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
+ ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32c() nounwind {
@@ -191,7 +191,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32c() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x200000
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
+ ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32d() nounwind {
@@ -199,7 +199,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32d() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20000000
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
+ ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32e() nounwind {
@@ -207,7 +207,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32e() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20ff
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
+ ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32f() nounwind {
@@ -215,7 +215,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32f() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20ffff
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
+ ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
}
define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {
@@ -223,7 +223,7 @@ define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff
; CHECK-NEXT: mov pc, lr
- ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+ ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}
; Check for correct assembler printing for immediate values.
@@ -267,7 +267,7 @@ define arm_aapcs_vfpcc <8 x i16> @vmovls8(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
- ret <8 x i16> %tmp2
+ ret <8 x i16> %tmp2
}
define arm_aapcs_vfpcc <4 x i32> @vmovls16(ptr %A) nounwind {
@@ -285,7 +285,7 @@ define arm_aapcs_vfpcc <4 x i32> @vmovls16(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
- ret <4 x i32> %tmp2
+ ret <4 x i32> %tmp2
}
define arm_aapcs_vfpcc <2 x i64> @vmovls32(ptr %A) nounwind {
@@ -296,7 +296,7 @@ define arm_aapcs_vfpcc <2 x i64> @vmovls32(ptr %A) nounwind {
; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
- ret <2 x i64> %tmp2
+ ret <2 x i64> %tmp2
}
define arm_aapcs_vfpcc <8 x i16> @vmovlu8(ptr %A) nounwind {
@@ -314,7 +314,7 @@ define arm_aapcs_vfpcc <8 x i16> @vmovlu8(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
- ret <8 x i16> %tmp2
+ ret <8 x i16> %tmp2
}
define arm_aapcs_vfpcc <4 x i32> @vmovlu16(ptr %A) nounwind {
@@ -332,7 +332,7 @@ define arm_aapcs_vfpcc <4 x i32> @vmovlu16(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
- ret <4 x i32> %tmp2
+ ret <4 x i32> %tmp2
}
define arm_aapcs_vfpcc <2 x i64> @vmovlu32(ptr %A) nounwind {
@@ -343,7 +343,7 @@ define arm_aapcs_vfpcc <2 x i64> @vmovlu32(ptr %A) nounwind {
; CHECK-NEXT: mov pc, lr
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
- ret <2 x i64> %tmp2
+ ret <2 x i64> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vmovni16(ptr %A) nounwind {
@@ -362,7 +362,7 @@ define arm_aapcs_vfpcc <8 x i8> @vmovni16(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
- ret <8 x i8> %tmp2
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vmovni32(ptr %A) nounwind {
@@ -381,7 +381,7 @@ define arm_aapcs_vfpcc <4 x i16> @vmovni32(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
- ret <4 x i16> %tmp2
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vmovni64(ptr %A) nounwind {
@@ -399,7 +399,7 @@ define arm_aapcs_vfpcc <2 x i32> @vmovni64(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <2 x i64>, ptr %A
%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
- ret <2 x i32> %tmp2
+ ret <2 x i32> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vqmovns16(ptr %A) nounwind {
@@ -418,7 +418,7 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovns16(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
- ret <8 x i8> %tmp2
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vqmovns32(ptr %A) nounwind {
@@ -437,7 +437,7 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovns32(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
- ret <4 x i16> %tmp2
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vqmovns64(ptr %A) nounwind {
@@ -455,7 +455,7 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovns64(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
- ret <2 x i32> %tmp2
+ ret <2 x i32> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(ptr %A) nounwind {
@@ -474,7 +474,7 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
- ret <8 x i8> %tmp2
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(ptr %A) nounwind {
@@ -493,7 +493,7 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
- ret <4 x i16> %tmp2
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(ptr %A) nounwind {
@@ -511,7 +511,7 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
- ret <2 x i32> %tmp2
+ ret <2 x i32> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(ptr %A) nounwind {
@@ -530,7 +530,7 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
- ret <8 x i8> %tmp2
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(ptr %A) nounwind {
@@ -549,7 +549,7 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
- ret <4 x i16> %tmp2
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(ptr %A) nounwind {
@@ -567,7 +567,7 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(ptr %A) nounwind {
; CHECK-BE-NEXT: mov pc, lr
%tmp1 = load <2 x i64>, ptr %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
- ret <2 x i32> %tmp2
+ ret <2 x i32> %tmp2
}
declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
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