[clang] [llvm] [Clang][AArch64] Add customisable immediate range checking to NEON (PR #100278)

[via cfe-commits]

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@@ -1959,9 +2064,12 @@ multiclass VCMLA_ROTS<string type, string lanety, string laneqty> {
 
     let isLaneQ = 1 in  {
       // vcmla{ROT}_laneq
+      // ACLE specifies that the fp16 vcmla_#ROT_laneq variant has an immedaite range of 0 <= lane <= 1.
+      // fp16 is the only variant for which these two differ.
+      // https://developer.arm.com/documentation/ihi0073/latest/ 
+      defvar getlanety = !if(!eq(type, "h"), lanety, laneqty);
       def : SOpInst<"vcmla" # ROT # "_laneq", "...QI", type,  Op<(call "vcmla" # ROT, $p0, $p1,
-              (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast laneqty, $p2), $p3))))>>;
-
+                (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast getlanety, $p2), $p3))))>>;
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rsandifo-arm wrote:

> [I]f you look at the most recent spec for this [instruction](https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions/FCMLA--indexed---Floating-point-complex-multiply-add-by-indexed-values-with-rotate-), it says quite clearly that immediate range for half-precision variant is from 0 to 3

That link is to the SVE instruction though, rather than the Advanced SIMD one.  The range for the 8H Advanced SIMD instruction is [0, 3], but the range for the 4H one is [0, 1].

https://github.com/llvm/llvm-project/pull/100278