[clang] [llvm] [RISCV] Add Hazard3 Core as taped out for RP2350 (PR #102452)

[Luke Wren via cfe-commits]

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@@ -402,6 +402,21 @@
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
 // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s
+// MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3"
+// MCPU-HAZARD3-SAME: "-target-feature" "+m"
+// MCPU-HAZARD3-SAME: "-target-feature" "+a"
+// MCPU-HAZARD3-SAME: "-target-feature" "+c"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zicsr"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zifencei"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zcb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zcmp"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zba"
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Wren6991 wrote:

Thanks. I got @lenary to explain the arch string expansion stuff to me offline, and I think I am clear on this now. I'm satisfied that not setting `FeatureStdExtB` is not going to cause any issues with feature detect in the future as long as people don't become too reliant on testing `__riscv_b` only.

Thanks again for the clarification.

https://github.com/llvm/llvm-project/pull/102452