[clang] [llvm] [RISCV][MC] Support experimental extensions Zvbc32e and Zvkgs (PR #103709)
Yingwei Zheng via cfe-commits
cfe-commits at lists.llvm.org
Wed Aug 14 01:21:25 PDT 2024
================
@@ -150,6 +150,14 @@ let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">;
} // Predicates = [HasStdExtZvkg]
+let Predicates = [HasStdExtZvkgs], RVVConstraint = NoConstraint in {
----------------
dtcxzyw wrote:
```suggestion
let Predicates = [HasStdExtZvkgs], RVVConstraint = VS2Constraint in {
```
Reserved Encodings
+ SEW is any value other than 32
+ **the vd register group overlaps the vs2 scalar element group**
https://github.com/llvm/llvm-project/pull/103709
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