[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
Piyou Chen via cfe-commits
cfe-commits at lists.llvm.org
Fri Aug 9 00:38:25 PDT 2024
================
@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RISCVExtensionBitmaskTable
+
+namespace {
+struct LessExtName {
+ bool operator()(const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &LHS,
+ StringRef RHS) {
+ return StringRef(LHS.Name) < RHS;
+ }
+ bool
+ operator()(StringRef LHS,
+ const RISCVExtensionBitmaskTable::RISCVExtensionBitmask &RHS) {
+ return LHS < StringRef(RHS.Name);
+ }
+};
+} // namespace
+
+static Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask>
+getExtensionBitmask(StringRef ExtName) {
+ ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
+ RISCVExtensionBitmaskTable::ExtensionBitmask;
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
+
+ if (I != ExtBitmasks.end())
+ return *I;
+
+ return createStringError("Unsupport extension");
+}
+
+llvm::SmallVector<uint64_t> getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
+ llvm::SmallVector<uint64_t> BitMasks(RISCV::RISCVFeatureBitSize);
+
+ for (auto Ext : Exts) {
+ Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmask =
+ getExtensionBitmask(Ext);
+ assert(ExtBitmask && "This extension doesn't has bitmask.");
----------------
BeMg wrote:
Sema check now also verifies whether the extension has already allocated the bit in the bitmask.
https://github.com/llvm/llvm-project/pull/85786
More information about the cfe-commits
mailing list