[clang] [llvm] [ARM][AArch64] BTI, GCS, PAC Module flag update. (PR #86212)

[Daniel Kiss via cfe-commits]

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@@ -0,0 +1,35 @@
+; This file contains the new semantic of the branch-target-enforcement, sign-return-address.
+; Used for test mixing a mixed link case and also verify the import too in llc.
+
+; RUN: llc %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define dso_local void @bar() #0 {
+entry:
+  ret void
+}
+; CHECK-LABEL: bar:
+; CHECK-NOT:       hint
+; CHECK-NOT:       bti
+; CHECK:           ret
+
+define dso_local void @baz() #1 {
+entry:
+  ret void
+}
+
+; CHECK-LABEL: baz:
+; CHECK:           hint
+; CHECK:           ret
+
+attributes #0 = { noinline nounwind optnone uwtable }
+attributes #1 = { noinline nounwind optnone uwtable "branch-target-enforcement" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+
+!0 = !{i32 8, !"branch-target-enforcement", i32 2}
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DanielKristofKiss wrote:

Yes, it is for counter test as `bar` shouldn't get BTI bits.
If something goes wrong and the module flag is treated as `1` then it will get BTI landing pads.

https://github.com/llvm/llvm-project/pull/86212