[clang] [llvm] [RISCV] Add Hazard3 CPU (PR #102452)

[Michael Maitland via cfe-commits]

michaelmaitland wrote:

There was a prior discussion about what designs should go in. The initial quote from @asb was:

> it's obvious that commercial designs with active support should go in, and that some core design I hacked up over a weekend shouldn't but we haven't had the need to discuss anything in-between that

@preames suggested:

> we might want to think about deprecation policy so that we can be fairly liberal in accepting support for new CPUs/microarchs, yet remove them later if they become less relevant

My main concern here is that we'd like to ensure that there is a maintainer for this. Could you provide us some more information on what entity would be the maintainer? It looks like @Wren6991 is the only maintainer of Hazard3.

I'm also interested in understanding whether there are any customers or users of this core.

I think it would be helpful to raise this at the next LLVM RISC-V syncup.

https://github.com/llvm/llvm-project/pull/102452