[clang] [llvm] [RISCV] Use RVA22U64Features in the definition of sifive-p450 and sifive-p670. (PR #102350)

[via cfe-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-clang

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

This matches sifive-p470.

RVA22U64Features includes the Zicntr extension which was not present for these CPUs before. I believe that was a mistake due to weird history of the Zicntr extension. I've updated the p470 test accordingly since this was missed there too.

---
Full diff: https://github.com/llvm/llvm-project/pull/102350.diff


2 Files Affected:

- (modified) clang/test/Driver/riscv-cpus.c (+3) 
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+6-48) 


``````````diff
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 750fb637edeb1..29687ac4e1c83 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -292,6 +292,7 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicntr"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl"
@@ -320,6 +321,7 @@
 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicntr"
 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
 // MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
@@ -368,6 +370,7 @@
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicntr"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei"
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index cc40d6a2f9865..ec9322f3e9924 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -246,32 +246,11 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
                                  FeaturePostRAScheduler];
 
 def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
-                                      [Feature64Bit,
-                                       FeatureStdExtI,
-                                       FeatureStdExtZifencei,
-                                       FeatureStdExtM,
-                                       FeatureStdExtA,
-                                       FeatureStdExtF,
-                                       FeatureStdExtD,
-                                       FeatureStdExtC,
-                                       FeatureStdExtZa64rs,
-                                       FeatureStdExtZic64b,
-                                       FeatureStdExtZicbop,
-                                       FeatureStdExtZicbom,
-                                       FeatureStdExtZicboz,
-                                       FeatureStdExtZiccamoa,
-                                       FeatureStdExtZiccif,
-                                       FeatureStdExtZicclsm,
-                                       FeatureStdExtZiccrse,
+                                      !listconcat(RVA22U64Features,
+                                      [FeatureStdExtZifencei,
                                        FeatureStdExtZihintntl,
-                                       FeatureStdExtZihintpause,
-                                       FeatureStdExtZihpm,
-                                       FeatureStdExtZba,
-                                       FeatureStdExtZbb,
-                                       FeatureStdExtZbs,
-                                       FeatureStdExtZfhmin,
                                        FeatureUnalignedScalarMem,
-                                       FeatureUnalignedVectorMem],
+                                       FeatureUnalignedVectorMem]),
                                       SiFiveP400TuneFeatures>;
 
 def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
@@ -294,31 +273,10 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
 
 
 def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
-                                      [Feature64Bit,
-                                       FeatureStdExtI,
+                                      !listconcat(RVA22U64Features,
+                                      [FeatureStdExtV,
                                        FeatureStdExtZifencei,
-                                       FeatureStdExtM,
-                                       FeatureStdExtA,
-                                       FeatureStdExtF,
-                                       FeatureStdExtD,
-                                       FeatureStdExtC,
-                                       FeatureStdExtZa64rs,
-                                       FeatureStdExtZic64b,
-                                       FeatureStdExtZicbop,
-                                       FeatureStdExtZicbom,
-                                       FeatureStdExtZicboz,
-                                       FeatureStdExtZiccamoa,
-                                       FeatureStdExtZiccif,
-                                       FeatureStdExtZicclsm,
-                                       FeatureStdExtZiccrse,
                                        FeatureStdExtZihintntl,
-                                       FeatureStdExtZihintpause,
-                                       FeatureStdExtZihpm,
-                                       FeatureStdExtZba,
-                                       FeatureStdExtZbb,
-                                       FeatureStdExtZbs,
-                                       FeatureStdExtZfhmin,
-                                       FeatureStdExtV,
                                        FeatureStdExtZvl128b,
                                        FeatureStdExtZvbb,
                                        FeatureStdExtZvknc,
@@ -326,7 +284,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
                                        FeatureStdExtZvksc,
                                        FeatureStdExtZvksg,
                                        FeatureUnalignedScalarMem,
-                                       FeatureUnalignedVectorMem],
+                                       FeatureUnalignedVectorMem]),
                                       [TuneNoDefaultUnroll,
                                        TuneConditionalCompressedMoveFusion,
                                        TuneLUIADDIFusion,

``````````

</details>


https://github.com/llvm/llvm-project/pull/102350