[clang] [llvm] [RISCV] Use RVA22U64Features in the definition of sifive-p450 and sifive-p670. (PR #102350)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Wed Aug 7 11:41:41 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/102350
RVA22U64Features includes the Zicntr extension which was not present for these CPUs before. I believe that was a mistake due to weird history of the Zicntr extension. I've updated the p470 test accordingly since this was missed there too.
>From c27fc33cf99118008aae6a9af8e4df7b05ff6135 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 7 Aug 2024 11:20:56 -0700
Subject: [PATCH] [RISCV] Use RVA22U64Features in the definition of sifive-p450
and sifive-p670.
RVA22U64Features includes the Zicntr extension which was not
present for these CPUs before. I believe that was a mistake due to
weird history of the Zicntr extension. I've updated the p470 test
accordingly since this was missed there too.
---
clang/test/Driver/riscv-cpus.c | 3 ++
llvm/lib/Target/RISCV/RISCVProcessors.td | 54 +++---------------------
2 files changed, 9 insertions(+), 48 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 750fb637edeb1a..29687ac4e1c83e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -292,6 +292,7 @@
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccif"
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicclsm"
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicntr"
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zicsr"
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zifencei"
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zihintntl"
@@ -320,6 +321,7 @@
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicntr"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
@@ -368,6 +370,7 @@
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicntr"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index cc40d6a2f9865d..ec9322f3e99240 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -246,32 +246,11 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
FeaturePostRAScheduler];
def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
- [Feature64Bit,
- FeatureStdExtI,
- FeatureStdExtZifencei,
- FeatureStdExtM,
- FeatureStdExtA,
- FeatureStdExtF,
- FeatureStdExtD,
- FeatureStdExtC,
- FeatureStdExtZa64rs,
- FeatureStdExtZic64b,
- FeatureStdExtZicbop,
- FeatureStdExtZicbom,
- FeatureStdExtZicboz,
- FeatureStdExtZiccamoa,
- FeatureStdExtZiccif,
- FeatureStdExtZicclsm,
- FeatureStdExtZiccrse,
+ !listconcat(RVA22U64Features,
+ [FeatureStdExtZifencei,
FeatureStdExtZihintntl,
- FeatureStdExtZihintpause,
- FeatureStdExtZihpm,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbs,
- FeatureStdExtZfhmin,
FeatureUnalignedScalarMem,
- FeatureUnalignedVectorMem],
+ FeatureUnalignedVectorMem]),
SiFiveP400TuneFeatures>;
def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
@@ -294,31 +273,10 @@ def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
- [Feature64Bit,
- FeatureStdExtI,
+ !listconcat(RVA22U64Features,
+ [FeatureStdExtV,
FeatureStdExtZifencei,
- FeatureStdExtM,
- FeatureStdExtA,
- FeatureStdExtF,
- FeatureStdExtD,
- FeatureStdExtC,
- FeatureStdExtZa64rs,
- FeatureStdExtZic64b,
- FeatureStdExtZicbop,
- FeatureStdExtZicbom,
- FeatureStdExtZicboz,
- FeatureStdExtZiccamoa,
- FeatureStdExtZiccif,
- FeatureStdExtZicclsm,
- FeatureStdExtZiccrse,
FeatureStdExtZihintntl,
- FeatureStdExtZihintpause,
- FeatureStdExtZihpm,
- FeatureStdExtZba,
- FeatureStdExtZbb,
- FeatureStdExtZbs,
- FeatureStdExtZfhmin,
- FeatureStdExtV,
FeatureStdExtZvl128b,
FeatureStdExtZvbb,
FeatureStdExtZvknc,
@@ -326,7 +284,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
FeatureStdExtZvksc,
FeatureStdExtZvksg,
FeatureUnalignedScalarMem,
- FeatureUnalignedVectorMem],
+ FeatureUnalignedVectorMem]),
[TuneNoDefaultUnroll,
TuneConditionalCompressedMoveFusion,
TuneLUIADDIFusion,
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