[clang] [llvm] [RISCV] Add Syntacore SCR5 RV32/64 processors definition (PR #102285)
Yingwei Zheng via cfe-commits
cfe-commits at lists.llvm.org
Wed Aug 7 08:27:27 PDT 2024
================
@@ -378,6 +378,32 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
+def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
+ NoSchedModel,
+ [Feature32Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
----------------
dtcxzyw wrote:
The documentation says A and F are both optional. It is weird to me because D always depends on F.
https://github.com/llvm/llvm-project/pull/102285
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