[clang] [llvm] [RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (PR #102155)
Michael Maitland via cfe-commits
cfe-commits at lists.llvm.org
Tue Aug 6 07:40:16 PDT 2024
https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/102155
The SiFiveP400 scheduler model did not support vector or vector crypto. With
the addition of the sifive-p470 processor, this model needs to support these
extensions.
The processors who use this model but do not have vector or vector crypto
will never produce these instructions, so there is no impact to these
processors.
This change is stacked on #102022
Co-authored-by: Min Hsu <min.hsu at sifive.com>
>From 24f8c5349f6df43cf3a58b30a6fa1cb74a167b14 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Mon, 5 Aug 2024 10:01:08 -0700
Subject: [PATCH 1/2] [RISCV] Add sifive-p470 processor
This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p450-470.
Use the existing P400 scheduler model. This model is missing accurate vector
scheduling support, but it will be added in a follow up patch.
Other tunings can come in future patches too.
---
clang/test/Driver/riscv-cpus.c | 48 +++++++++++++++++++++
clang/test/Misc/target-invalid-cpu-note.c | 5 ++-
llvm/docs/ReleaseNotes.rst | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 52 ++++++++++++++++++++---
4 files changed, 99 insertions(+), 7 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 7a885cde76d6a..750fb637edeb1 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -304,6 +304,54 @@
// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p470 | FileCheck -check-prefix=MCPU-SIFIVE-P470 %s
+// MCPU-SIFIVE-P470: "-target-cpu" "sifive-p470"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+m"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+a"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+f"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+d"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+c"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+v"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zic64b"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbom"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicbop"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicboz"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccamoa"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccif"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicclsm"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zicsr"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zifencei"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintntl"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihintpause"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zihpm"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zmmul"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+za64rs"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zfhmin"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zba"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbb"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zbs"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbb"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32f"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve32x"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64d"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64f"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zve64x"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkg"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkn"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknc"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkned"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkng"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvknhb"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvks"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksc"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksed"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksg"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvksh"
+// MCPU-SIFIVE-P470-SAME: "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P470-SAME: "-target-abi" "lp64d"
+
// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s
// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index b87bced18cb2b..249bea2311549 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu{{$}}
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,5 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p470, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, syntacore-scr4-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index a95cb53694e2b..1ed860de6b9dc 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -107,6 +107,7 @@ Changes to the RISC-V Backend
the required alignment space with a sequence of `0x0` bytes (the requested
fill value) rather than NOPs.
* Added Syntacore SCR4 CPUs: ``-mcpu=syntacore-scr4-rv32/64``
+* ``-mcpu=sifive-p470`` was added.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 83d27b35cf0da..a118e1fe5e502 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -239,6 +239,12 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
FeatureStdExtZbb],
SiFiveX280TuneFeatures>;
+defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
+ TuneConditionalCompressedMoveFusion,
+ TuneLUIADDIFusion,
+ TuneAUIPCADDIFusion,
+ FeaturePostRAScheduler];
+
def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
[Feature64Bit,
FeatureStdExtI,
@@ -266,11 +272,47 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
FeatureStdExtZfhmin,
FeatureUnalignedScalarMem,
FeatureUnalignedVectorMem],
- [TuneNoDefaultUnroll,
- TuneConditionalCompressedMoveFusion,
- TuneLUIADDIFusion,
- TuneAUIPCADDIFusion,
- FeaturePostRAScheduler]>;
+ SiFiveP400TuneFeatures>;
+
+def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureVendorXSiFivecdiscarddlone,
+ FeatureVendorXSiFivecflushdlone,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicboz,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZiccif,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZihpm,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZfhmin,
+ FeatureStdExtV,
+ FeatureStdExtZvl128b,
+ FeatureStdExtZvbb,
+ FeatureStdExtZvknc,
+ FeatureStdExtZvkng,
+ FeatureStdExtZvksc,
+ FeatureStdExtZvksg,
+ FeatureUnalignedScalarMem,
+ FeatureUnalignedVectorMem],
+ !listconcat(SiFiveP400TuneFeatures,
+ [TuneNoSinkSplatOperands])>;
+
def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
[Feature64Bit,
>From b171a13599d615deea63903550fe16e67bac2bbc Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 6 Aug 2024 07:34:12 -0700
Subject: [PATCH 2/2] [RISCV] Add vector and vector crypto to SiFiveP400
scheduler model
The SiFiveP400 scheduler model did not support vector or vector crypto. With
the addition of the sifive-p470 processor, this model needs to support these
extensions.
The processors who use this model but do not have vector or vector crypto
will never produce these instructions, so there is no impact to these
processors.
Co-authored-by: Min Hsu <min.hsu at sifive.com>
---
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 869 +-
.../tools/llvm-mca/RISCV/SiFiveP400/load.s | 21 +-
.../llvm-mca/RISCV/SiFiveP400/vislide-vx.s | 108 +
.../llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s | 9827 +++++++++++++++++
.../tools/llvm-mca/RISCV/SiFiveP400/vmv.s | 895 ++
.../tools/llvm-mca/RISCV/SiFiveP400/vreduce.s | 438 +
.../llvm-mca/RISCV/SiFiveP400/vrgather.s | 86 +
.../llvm-mca/RISCV/SiFiveP400/vshift-vmul.s | 132 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvbb.s | 460 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvbc.s | 112 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvkg.s | 127 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvkned.s | 203 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s | 152 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvksed.s | 113 +
.../tools/llvm-mca/RISCV/SiFiveP400/zvksh.s | 98 +
15 files changed, 13631 insertions(+), 10 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 9fa455be38525..6926184e92399 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -8,6 +8,115 @@
//===----------------------------------------------------------------------===//
+/// c is true if mx has the worst case behavior compared to LMULs in MxList.
+/// On the SiFiveP400, the worst case LMUL is the Largest LMUL
+/// and the worst case sew is the smallest SEW for that LMUL.
+class SiFiveP400IsWorstCaseMX<string mx, list<string> MxList> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+class SiFiveP400IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ int SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+// 1 Micro-Op per cycle.
+class SiFiveP400GetLMulCycles<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+}
+
+// Latency for segmented loads and stores are calculated as vl * nf.
+class SiFiveP400GetCyclesSegmented<string mx, int sew, int nf> {
+ defvar VLEN = 128;
+ defvar VLUpperBound = !cond(
+ !eq(mx, "M1") : !div(VLEN, sew),
+ !eq(mx, "M2") : !div(!mul(VLEN, 2), sew),
+ !eq(mx, "M4") : !div(!mul(VLEN, 4), sew),
+ !eq(mx, "M8") : !div(!mul(VLEN, 8), sew),
+ !eq(mx, "MF2") : !div(!div(VLEN, 2), sew),
+ !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
+ !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
+ );
+ int c = !mul(VLUpperBound, nf);
+}
+
+// Both variants of floating point vector reductions are based on numbers collected
+// from llvm-exegesis.
+class VFReduceBaseCycles<int sew> {
+ // The latency for simple unordered VFReduce is `C + 6 * log2(LMUL)`,
+ // and `C * LMUL` for ordered VFReduce. This helper class provides the `C`.
+ int val = !cond(!eq(sew, 16): 16,
+ !eq(sew, 32): 10,
+ !eq(sew, 64): 6);
+}
+
+class AdvancedVFReduceCycles<int sew, string mx> {
+ // SEW = 64 has lower latencies and RThroughputs than other SEWs.
+ int latency = !cond(!eq(mx, "M1"): !if(!eq(sew, 64), 4, 6),
+ !eq(mx, "M2"): !if(!eq(sew, 64), 6, 8),
+ !eq(mx, "M4"): !if(!eq(sew, 64), 8, 10),
+ !eq(mx, "M8"): !if(!eq(sew, 64), 11, 13),
+ true: !if(!eq(sew, 64), 4, 6));
+ int rthroughput = !cond(!eq(mx, "M1"): !if(!eq(sew, 64), 2, 3),
+ !eq(mx, "M2"): !if(!eq(sew, 64), 3, 4),
+ !eq(mx, "M4"): !if(!eq(sew, 64), 5, 6),
+ !eq(mx, "M8"): !if(!eq(sew, 64), 10, 12),
+ true: !if(!eq(sew, 64), 2, 3));
+}
+
+// Both variants of integer vector reductions are based on numbers collected
+// from llvm-exegesis.
+// TODO: Fractional LMUL's latency and rthroughput.
+class SimpleVIReduceCycles<string mx> {
+ defvar LMul = SiFiveP400GetLMulCycles<mx>.c;
+ int latency = !mul(LMul, 2);
+ int rthroughput = !cond(
+ !eq(mx, "M1"): 1,
+ !eq(mx, "M2"): 2,
+ !eq(mx, "M4"): 4,
+ !eq(mx, "M8"): 9,
+ true: 1);
+}
+
+class AdvancedVIReduceCycles<int sew, string mx> {
+ // `C - 2 * log2(SEW)`, where `C` = 16.1, 18.1, 20.1, and 23.8 for
+ // M1/2/4/8, respectively.
+ int latency = !cond(!eq(mx, "M1"): !sub(16, !mul(2, !logtwo(sew))),
+ !eq(mx, "M2"): !sub(18, !mul(2, !logtwo(sew))),
+ !eq(mx, "M4"): !sub(20, !mul(2, !logtwo(sew))),
+ !eq(mx, "M8"): !sub(23, !mul(2, !logtwo(sew))),
+ true: 4);
+ int rthroughput = !cond(
+ // `8.3 - 1.02 * log2(SEW)`
+ !eq(mx, "M1"): !sub(8, !logtwo(sew)),
+ // `10.0 - 1.16 * log2(SEW)`. Note that `9 - log2(SEW)`
+ // is closer to the floor value of the original formula.
+ !eq(mx, "M2"): !sub(9, !logtwo(sew)),
+ // `14.2 - 1.53 * log2(SEW)`
+ !eq(mx, "M4"): !div(!sub(1420, !mul(153, !logtwo(sew))), 100),
+ // `24.1 - 2.3 * log2(SEW)`
+ !eq(mx, "M8"): !div(!sub(241, !mul(23, !logtwo(sew))), 10),
+ true: 1);
+}
+
+class SiFiveP400VSM3CCycles<string mx> {
+ // c = ceil(LMUL / 2)
+ int c = !cond(!eq(mx, "M2") : 1,
+ !eq(mx, "M4") : 2,
+ !eq(mx, "M8") : 4,
+ true : 1);
+}
+
def SiFiveP400Model : SchedMachineModel {
let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
let MicroOpBufferSize = 56; // Max micro-ops that can be buffered.
@@ -45,6 +154,13 @@ defvar SiFiveP400FloatArith = SiFiveP400FEXQ0;
defvar SiFiveP400F2I = SiFiveP400FEXQ0;
def SiFiveP400FloatDiv : ProcResource<1>;
+// Vector pipeline
+def SiFiveP400VEXQ0 : ProcResource<1>;
+def SiFiveP400VLD : ProcResource<1>;
+def SiFiveP400VST : ProcResource<1>;
+def SiFiveP400VDiv : ProcResource<1>;
+def SiFiveP400VFloatDiv : ProcResource<1>;
+
let Latency = 1 in {
// Integer arithmetic and logic
def : WriteRes<WriteIALU, [SiFiveP400IntArith]>;
@@ -246,9 +362,549 @@ def : WriteRes<WriteFMovI64ToF64, [SiFiveP400I2F]>;
def : WriteRes<WriteFMovF64ToI64, [SiFiveP400F2I]>;
}
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, [SiFiveP400SYS]>;
+def : WriteRes<WriteVSETIVLI, [SiFiveP400SYS]>;
+def : WriteRes<WriteVSETVL, [SiFiveP400SYS]>;
+
+// 7. Vector Loads and Stores
+// FIXME: This unit is still being improved, currently
+// it is based on stage numbers. Estimates are optimistic,
+// latency may be longer.
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 8, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDM", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [SiFiveP400VLD], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDS8", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS16", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS32", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDS64", [SiFiveP400VLD], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFiveP400VLD], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 8, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSTE", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [SiFiveP400VST], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSTS8", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS16", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS32", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS64", [SiFiveP400VST], mx, IsWorstCase>;
+ }
+ let Latency = 12, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFiveP400VST], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ defvar LMulLat = SiFiveP400GetCyclesSegmented<mx, eew, nf>.c;
+ let Latency = !add(12, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" #eew, [SiFiveP400VLD], mx, IsWorstCase>;
+ }
+ let Latency = !add(1, LMulLat), ReleaseAtCycles = [!add(12, LMulLat)] in {
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" #eew, [SiFiveP400VST], mx, IsWorstCase>;
+ }
+ }
+ }
+}
+
+// Whole register move/load/store
+foreach LMul = [1, 2, 4, 8] in {
+ let Latency = 8, ReleaseAtCycles = [LMul] in {
+ def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SiFiveP400VLD]>;
+ def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SiFiveP400VST]>;
+ }
+ let Latency = 2, ReleaseAtCycles = [LMul] in {
+ def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SiFiveP400VEXQ0]>;
+ }
+}
+
+// 11. Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVExtV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+
+ let Latency = !if(!lt(LMulLat, 2), 2, LMulLat), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVShiftV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+
+ let Latency = !if(!eq(mx, "M8"), 9, 6), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIMulV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+// Widening
+foreach mx = SchedMxListW in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// Worst case needs 51/45/42/72 * lmul cycles for i8/16/32/64.
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ defvar DivMicroOpLat =
+ !cond(!eq(sew, 8): 51, !eq(sew, 16): 45, !eq(sew, 32): 42,
+ /* SEW=64 */ true: 72);
+ defvar DivLatency = !mul(DivMicroOpLat, LMulLat);
+ let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFiveP400VEXQ0, SiFiveP400VDiv], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFiveP400VEXQ0, SiFiveP400VDiv], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Narrowing Shift and Clips
+foreach mx = SchedMxListW in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// 13. Vector Floating-Point Instructions
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFClassV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListFW in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListFW>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+}
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+}
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Worst case needs around 29/25/37 * LMUL cycles for f16/32/64.
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ defvar DivMicroOpLat =
+ !cond(!eq(sew, 16): 29, !eq(sew, 32): 25, /* SEW=64 */ true: 37);
+ defvar DivLatency = !mul(DivMicroOpLat, LMulLat);
+ let Latency = DivLatency, ReleaseAtCycles = [LMulLat, DivLatency] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFiveP400VEXQ0, SiFiveP400VFloatDiv], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFiveP400VEXQ0, SiFiveP400VFloatDiv], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFiveP400VEXQ0, SiFiveP400VFloatDiv], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// 14. Vector Reduction Operations
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+
+ // Simple reduction
+ defvar SimpleC = SimpleVIReduceCycles<mx>;
+ let Latency = SimpleC.latency, ReleaseAtCycles = [SimpleC.rthroughput] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+
+ // Advanced reduction
+ defvar AdvancedC = AdvancedVIReduceCycles<sew, mx>;
+ let Latency = AdvancedC.latency, ReleaseAtCycles = [AdvancedC.rthroughput] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFiveP400VEXQ0],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, 0, 1>.val in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+ defvar SimpleC = SimpleVIReduceCycles<mx>;
+ let Latency = SimpleC.latency, ReleaseAtCycles = [SimpleC.rthroughput] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFiveP400VEXQ0],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ // Simple reduction.
+ defvar BaseC = VFReduceBaseCycles<sew>.val;
+ let Latency = !add(BaseC, !mul(6, !logtwo(LMulLat))), ReleaseAtCycles = [BaseC] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFiveP400VEXQ0],
+ mx, sew, IsWorstCase>;
+
+ // Advanced reduction.
+ defvar AdvancedC = AdvancedVFReduceCycles<sew, mx>;
+ let Latency = AdvancedC.latency, ReleaseAtCycles = [AdvancedC.rthroughput] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From",
+ [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+
+ defvar OrderedRedCycles = !mul(BaseC, LMulLat);
+ let Latency = OrderedRedCycles, ReleaseAtCycles = [OrderedRedCycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFiveP400VEXQ0],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
+ let Latency = !add(6, !mul(6, LMulLat)), ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFiveP400VEXQ0],
+ mx, sew, IsWorstCase>;
+ }
+
+ defvar OrderedRedCycles = !mul(VFReduceBaseCycles<sew>.val, LMulLat);
+ let Latency = OrderedRedCycles, ReleaseAtCycles = [OrderedRedCycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFiveP400VEXQ0],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+// 15. Vector Mask Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [1] in {
+ defm "" : LMULWriteResMX<"WriteVMALUV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMPopV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVIotaV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// 16. Vector Permutation Instructions
+// Simple Slide
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 2, ReleaseAtCycles = [1] in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// Complex Slide
+foreach mx = ["M2", "M4", "M8"] in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar UpLatAndCycles = !add(8, LMulLat);
+ let Latency = UpLatAndCycles, ReleaseAtCycles = [UpLatAndCycles] in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ defvar DownLatAndCycles = !add(8, !div(!mul(LMulLat, 3), 2));
+ let Latency = DownLatAndCycles, ReleaseAtCycles = [DownLatAndCycles] in {
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+let Latency = 2, ReleaseAtCycles = [2] in {
+ def : WriteRes<WriteVMovXS, [SiFiveP400VEXQ0]>;
+ def : WriteRes<WriteVMovSX, [SiFiveP400VEXQ0]>;
+}
+let Latency = 6, ReleaseAtCycles = [2] in {
+ def : WriteRes<WriteVMovFS, [SiFiveP400VEXQ0]>;
+ def : WriteRes<WriteVMovSF, [SiFiveP400VEXQ0]>;
+}
+
+// Simple Gather and Compress
+foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [1] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [1] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Complex Gather and Compress
+foreach mx = ["M2", "M4", "M8"] in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = ["M2", "M4", "M8"] in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = 6, ReleaseAtCycles = [!add(!mul(LMulLat, 2), 8)] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFiveP400VEXQ0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Simple Vrgather.vi
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
+// Vector Crypto
+foreach mx = SchedMxList in {
+ defvar LMulLat = SiFiveP400GetLMulCycles<mx>.c;
+ defvar IsWorstCase = SiFiveP400IsWorstCaseMX<mx, SchedMxList>.c;
+ // Zvbb
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ // Zvbc
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ // Zvkb
+ // VANDN uses WriteVIALU[V|X|I]
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ // Zvkg
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ // ZvknhaOrZvknhb
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ // Zvkned
+ let Latency = 2, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+ // Zvksed
+ let Latency = 3, ReleaseAtCycles = [SiFiveP400VSM3CCycles<mx>.c] in
+ defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ let Latency = 6, ReleaseAtCycles = [LMulLat] in
+ defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ let Latency = 3, ReleaseAtCycles = [LMulLat] in {
+ defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ }
+}
+
// Others
def : WriteRes<WriteCSR, [SiFiveP400SYS]>;
def : WriteRes<WriteNop, []>;
+def : WriteRes<WriteRdVLENB, [SiFiveP400SYS]>;
+
// FIXME: This could be better modeled by looking at the regclasses of the operands.
def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;
@@ -356,6 +1012,217 @@ def : ReadAdvance<ReadSHXADD32, 0>;
def : ReadAdvance<ReadSingleBit, 0>;
def : ReadAdvance<ReadSingleBitImm, 0>;
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
+// 12. Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 13. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 14. Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+// 15. Vector Reduction Operations
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// 16. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// 17. Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;
+}
+
+// Vector Crypto Extensions
+// Zvbb
+defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
+defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
+defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
+defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
+defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
+defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
+// Zvbc
+defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
+defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
+// Zvkb
+// VANDN uses ReadVIALU[V|X|I]
+defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
+defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
+defm "" : LMULReadAdvance<"ReadVRotV", 0>;
+defm "" : LMULReadAdvance<"ReadVRotX", 0>;
+// Zvkg
+defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
+defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
+// Zvknha or Zvknhb
+defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
+defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
+defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>;
+// Zvkned
+defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
+defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
+defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
+defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
+// Zvksed
+defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
+defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
+// Zbksh
+defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
+defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedZabha;
@@ -364,7 +1231,5 @@ defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedV;
defm : UnsupportedSchedXsfvcp;
-defm : UnsupportedSchedZvk;
}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
index 3cf207b594ad9..216d2f6c9b571 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/load.s
@@ -42,15 +42,20 @@ fld ft0, 0(a0)
# CHECK-NEXT: [5] - SiFiveP400IEXQ2
# CHECK-NEXT: [6] - SiFiveP400Load
# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - - - - - 5.00 -
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - - - 5.00 - - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
-# CHECK-NEXT: - - - - - - 1.00 - lw t0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - ld t0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - flh ft0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - flw ft0, 0(a0)
-# CHECK-NEXT: - - - - - - 1.00 - fld ft0, 0(a0)
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - fld ft0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
new file mode 100644
index 0000000000000..c4934f4ab0209
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vislide-vx.s
@@ -0,0 +1,108 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m2, tu, mu
+vslidedown.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m4, tu, mu
+vslidedown.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m8, tu, mu
+vslidedown.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m2, tu, mu
+vslideup.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m4, tu, mu
+vslideup.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m8, tu, mu
+vslideup.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m2, tu, mu
+vslideup.vx v5, v7, x6, v0.t
+
+vsetvli zero, zero, e32, m4, tu, mu
+vslideup.vx v5, v7, x6, v0.t
+
+vsetvli zero, zero, e32, m8, tu, mu
+vslideup.vx v5, v7, x6, v0.t
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 18
+# CHECK-NEXT: Total Cycles: 125
+# CHECK-NEXT: Total uOps: 18
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.14
+# CHECK-NEXT: IPC: 0.14
+# CHECK-NEXT: Block RThroughput: 121.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 11.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 20 20.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 vslideup.vx v5, v7, t1, v0.t
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 9.00 - - - - 121.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 11.00 - - - vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 20.00 - - - vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vslideup.vx v5, v7, t1, v0.t
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
new file mode 100644
index 0000000000000..aba6b2f3e24a5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
@@ -0,0 +1,9827 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf8, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf8, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, mf4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, mf8, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, mf4, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, mf2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vlseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf8, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf8, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, mf4, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, mf8, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, mf4, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, mf2, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vlseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf8, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf8, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, mf4, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, mf8, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, mf4, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, mf2, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vlseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf8, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf8, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, mf4, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, mf8, tu, mu
+vlseg5e64.v v8,(a0)
+vsetvli zero, zero, e64, mf4, tu, mu
+vlseg5e64.v v8,(a0)
+vsetvli zero, zero, e64, mf2, tu, mu
+vlseg5e64.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg5e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg5e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf8, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf8, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, mf4, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
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+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m4, tu, mu
+vsoxseg6ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m4, tu, mu
+vsoxseg6ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m4, tu, mu
+vsoxseg7ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m4, tu, mu
+vsoxseg7ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m4, tu, mu
+vsoxseg7ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m4, tu, mu
+vsoxseg7ei64.v v8, (a0), v16
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m2, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m4, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m4, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m2, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+vsetvli zero, zero, e64, m4, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 3240
+# CHECK-NEXT: Total Cycles: 217825
+# CHECK-NEXT: Total uOps: 3240
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.01
+# CHECK-NEXT: IPC: 0.01
+# CHECK-NEXT: Block RThroughput: 124596.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 18 18.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 652 652.00 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 332 332.00 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 172 172.00 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 22 22.00 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 92 92.00 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 780 780.00 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 60 60.00 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 396 396.00 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 204 204.00 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 108 108.00 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 908 908.00 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 68 68.00 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 460 460.00 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 236 236.00 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 124 124.00 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1036 1036.00 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 76 76.00 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 524 524.00 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 44 44.00 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 268 268.00 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 4 15.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 4 15.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 4 15.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 6 17.00 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 6 17.00 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 6 17.00 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 8 19.00 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 8 19.00 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 8 19.00 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 3 14.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 3 14.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 3 14.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 4 15.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 4 15.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 4 15.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 5 16.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 641 652.00 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 6 17.00 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 41 52.00 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 321 332.00 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 6 17.00 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 21 32.00 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 161 172.00 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 6 17.00 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 11 22.00 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 81 92.00 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 769 780.00 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 49 60.00 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 385 396.00 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 25 36.00 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 193 204.00 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 7 18.00 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 13 24.00 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 97 108.00 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 897 908.00 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 8 19.00 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 57 68.00 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 449 460.00 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 8 19.00 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 29 40.00 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 225 236.00 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 8 19.00 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 26.00 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 113 124.00 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1025 1036.00 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 65 76.00 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 513 524.00 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 33 44.00 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 257 268.00 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 12.00 * vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 9 20.00 * vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 17 28.00 * vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 129 140.00 * vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 1620.00 - - - - - - 124596.00 96850.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 140.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 268.00 - vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 140.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 140.00 - vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 16.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 20.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 28.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 76.00 - vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 44.00 - vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
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+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 172.00 vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 17.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 22.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 92.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 92.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 60.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 108.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 780.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 780.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 18.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 60.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 396.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 396.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 18.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 36.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 204.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 204.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 18.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 24.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 108.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 108.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 68.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 124.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 908.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 908.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 19.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 68.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 460.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 460.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 19.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 40.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 236.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 236.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 19.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 26.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 124.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 124.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 76.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 140.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1036.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1036.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 20.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 76.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 524.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 524.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 20.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 44.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 268.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 268.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 12.00 vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 20.00 vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 28.00 vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 140.00 vsoxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 140.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
new file mode 100644
index 0000000000000..31178e8e238f1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vmv.s
@@ -0,0 +1,895 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv8r.v v8, v16
+
+vsetvli zero, zero, e64, m1, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m2, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m4, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m8, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 280
+# CHECK-NEXT: Total Cycles: 523
+# CHECK-NEXT: Total uOps: 280
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.54
+# CHECK-NEXT: IPC: 0.54
+# CHECK-NEXT: Block RThroughput: 512.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 2.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 2.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 6 2.00 vfmv.f.s ft7, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 136.00 - - - - 512.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.s.x v8, t0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vmv.x.s t2, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfmv.f.s ft7, v16
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
new file mode 100644
index 0000000000000..0fc0bf03d7ecb
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vreduce.s
@@ -0,0 +1,438 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+# Simple integer reductions: varies by LMUL
+vsetvli zero, zero, e32, m1, tu, mu
+vredsum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vredsum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vredsum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vredsum.vs v5, v7, v8
+
+# Advanced integer reductions: varies by LMUL and SEW
+vsetvli zero, zero, e16, m1, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m2, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m4, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m8, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+# Simple floating point reductions: varies by LMUL and SEW
+vsetvli zero, zero, e16, m1, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m2, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m4, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m8, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+# Advanced floating point reductions: varies by LMUL and SEW
+vsetvli zero, zero, e16, m1, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m2, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m4, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m8, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 116
+# CHECK-NEXT: Total Cycles: 921
+# CHECK-NEXT: Total uOps: 116
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.13
+# CHECK-NEXT: IPC: 0.13
+# CHECK-NEXT: Block RThroughput: 916.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 9.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 10 5.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 12 8.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 12 8.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 15 14.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 15 14.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 6 3.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 10 6.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 13 12.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 6 3.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 5.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 11 10.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 16 16.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 22 16.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 32 32.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 28 16.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 64 64.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 34 16.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 128 128.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 10 10.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 10 10.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 10.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 20 20.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 22 10.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 40 40.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 28 10.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 80 80.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 6 6.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 12 12.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 18 6.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 24 24.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 24 6.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 48 48.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 6 3.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 10 6.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 13 12.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 6 3.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 6.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 10 6.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 13 12.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 13 12.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 6 3.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 5.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 5.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 11 10.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 11 10.00 vfredmax.vs v5, v7, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 40.00 - - - - 916.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 9.00 - - - vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 32.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 64.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 128.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 20.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 40.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 80.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 24.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 48.00 - - - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 6.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 3.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 5.00 - - - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 10.00 - - - vfredmax.vs v5, v7, v8
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
new file mode 100644
index 0000000000000..ef24850957193
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vrgather.s
@@ -0,0 +1,86 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m1, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+vsetvli zero, zero, e32, m2, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+vsetvli zero, zero, e32, m4, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+vsetvli zero, zero, e32, m8, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 12
+# CHECK-NEXT: Total Cycles: 92
+# CHECK-NEXT: Total uOps: 12
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.13
+# CHECK-NEXT: IPC: 0.13
+# CHECK-NEXT: Block RThroughput: 106.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 3 1.00 vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 12.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 6 12.00 vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 16.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 6 16.00 vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 24.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 6 24.00 vcompress.vm v4, v9, v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 4.00 - - - - 106.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 12.00 - - - vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 24.00 - - - vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - 24.00 - - - vcompress.vm v4, v9, v0
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
new file mode 100644
index 0000000000000..7a0cf27f37425
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vshift-vmul.s
@@ -0,0 +1,132 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m1, ta, ma
+
+vsll.vv v1, v2, v5
+vsll.vx v1, v2, t0
+vsll.vi v1, v2, 7
+
+vsrl.vv v1, v2, v5
+vsrl.vx v1, v2, t0
+vsrl.vi v1, v2, 7
+
+vsra.vv v1, v2, v5
+vsra.vx v1, v2, t0
+vsra.vi v1, v2, 7
+
+vsetvli zero, zero, e32, mf4, ta, ma
+
+vsll.vv v1, v2, v5
+vsll.vx v1, v2, t0
+vsll.vi v1, v2, 7
+
+vsrl.vv v1, v2, v5
+vsrl.vx v1, v2, t0
+vsrl.vi v1, v2, 7
+
+vsra.vv v1, v2, v5
+vsra.vx v1, v2, t0
+vsra.vi v1, v2, 7
+
+vsetvli zero, zero, e32, m8, ta, ma
+
+vmul.vv v1, v2, v5
+vmul.vx v1, v2, t1
+
+vmadd.vv v1, v2, v5
+vmadd.vx v1, t1, v2
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 25
+# CHECK-NEXT: Total Cycles: 57
+# CHECK-NEXT: Total uOps: 25
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.44
+# CHECK-NEXT: IPC: 0.44
+# CHECK-NEXT: Block RThroughput: 50.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 1.00 vsll.vv v1, v2, v5
+# CHECK-NEXT: 1 2 1.00 vsll.vx v1, v2, t0
+# CHECK-NEXT: 1 2 1.00 vsll.vi v1, v2, 7
+# CHECK-NEXT: 1 2 1.00 vsrl.vv v1, v2, v5
+# CHECK-NEXT: 1 2 1.00 vsrl.vx v1, v2, t0
+# CHECK-NEXT: 1 2 1.00 vsrl.vi v1, v2, 7
+# CHECK-NEXT: 1 2 1.00 vsra.vv v1, v2, v5
+# CHECK-NEXT: 1 2 1.00 vsra.vx v1, v2, t0
+# CHECK-NEXT: 1 2 1.00 vsra.vi v1, v2, 7
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf4, ta, ma
+# CHECK-NEXT: 1 2 1.00 vsll.vv v1, v2, v5
+# CHECK-NEXT: 1 2 1.00 vsll.vx v1, v2, t0
+# CHECK-NEXT: 1 2 1.00 vsll.vi v1, v2, 7
+# CHECK-NEXT: 1 2 1.00 vsrl.vv v1, v2, v5
+# CHECK-NEXT: 1 2 1.00 vsrl.vx v1, v2, t0
+# CHECK-NEXT: 1 2 1.00 vsrl.vi v1, v2, 7
+# CHECK-NEXT: 1 2 1.00 vsra.vv v1, v2, v5
+# CHECK-NEXT: 1 2 1.00 vsra.vx v1, v2, t0
+# CHECK-NEXT: 1 2 1.00 vsra.vi v1, v2, 7
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 9 8.00 vmul.vv v1, v2, v5
+# CHECK-NEXT: 1 9 8.00 vmul.vx v1, v2, t1
+# CHECK-NEXT: 1 9 8.00 vmadd.vv v1, v2, v5
+# CHECK-NEXT: 1 9 8.00 vmadd.vx v1, t1, v2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 3.00 - - - - 50.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vi v1, v2, 7
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsll.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsrl.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsra.vi v1, v2, 7
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmul.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmul.vx v1, v2, t1
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmadd.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vmadd.vx v1, t1, v2
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s
new file mode 100644
index 0000000000000..236c8f0199f66
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbb.s
@@ -0,0 +1,460 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v4, v8, v12
+vwsll.vx v4, v8, a0
+vwsll.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vandn.vv v8, v16, v24
+vandn.vx v8, v16, a0
+vbrev.v v8, v16
+vbrev8.v v8, v16
+vrev8.v v8, v16
+vclz.v v8, v16
+vctz.v v8, v16
+vcpop.v v8, v16
+vrol.vv v8, v16, v24
+vrol.vx v8, v16, a0
+vror.vv v8, v16, v24
+vror.vx v8, v16, a0
+vror.vi v8, v16, 8
+
+# Show SEW does not matter
+vsetvli zero, zero, e16, m4, tu, mu
+vandn.vv v4, v8, v12
+vandn.vx v4, v8, a0
+vbrev.v v4, v8
+vbrev8.v v4, v8
+vrev8.v v4, v8
+vclz.v v4, v8
+vctz.v v4, v8
+vcpop.v v4, v8
+vrol.vv v4, v8, v12
+vrol.vx v4, v8, a0
+vror.vv v4, v8, v12
+vror.vx v4, v8, a0
+vror.vi v4, v8, 8
+vwsll.vv v8, v4, v12
+vwsll.vx v8, v4, a0
+vwsll.vi v8, v4, 8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 133
+# CHECK-NEXT: Total Cycles: 330
+# CHECK-NEXT: Total uOps: 133
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.40
+# CHECK-NEXT: IPC: 0.40
+# CHECK-NEXT: Block RThroughput: 328.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 1.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 2.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 2.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 2.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 2.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 2.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 2.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 vwsll.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vwsll.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 vwsll.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 4.00 vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 2 4.00 vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 2 4.00 vwsll.vi v8, v4, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vandn.vv v8, v16, v24
+# CHECK-NEXT: 1 2 8.00 vandn.vx v8, v16, a0
+# CHECK-NEXT: 1 2 8.00 vbrev.v v8, v16
+# CHECK-NEXT: 1 2 8.00 vbrev8.v v8, v16
+# CHECK-NEXT: 1 2 8.00 vrev8.v v8, v16
+# CHECK-NEXT: 1 2 8.00 vclz.v v8, v16
+# CHECK-NEXT: 1 2 8.00 vctz.v v8, v16
+# CHECK-NEXT: 1 2 8.00 vcpop.v v8, v16
+# CHECK-NEXT: 1 2 8.00 vrol.vv v8, v16, v24
+# CHECK-NEXT: 1 2 8.00 vrol.vx v8, v16, a0
+# CHECK-NEXT: 1 2 8.00 vror.vv v8, v16, v24
+# CHECK-NEXT: 1 2 8.00 vror.vx v8, v16, a0
+# CHECK-NEXT: 1 2 8.00 vror.vi v8, v16, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vandn.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vandn.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vbrev.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vbrev8.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vrev8.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vclz.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vctz.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vcpop.v v4, v8
+# CHECK-NEXT: 1 2 4.00 vrol.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vrol.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vror.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vror.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vror.vi v4, v8, 8
+# CHECK-NEXT: 1 2 4.00 vwsll.vv v8, v4, v12
+# CHECK-NEXT: 1 2 4.00 vwsll.vx v8, v4, a0
+# CHECK-NEXT: 1 2 4.00 vwsll.vi v8, v4, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 8.00 - - - - 328.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsll.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsll.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vwsll.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsll.vi v8, v4, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vandn.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vandn.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vbrev.v v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vbrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vrev8.v v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vctz.v v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vcpop.v v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vrol.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vrol.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vror.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vror.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vror.vi v8, v16, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vandn.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vandn.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vbrev.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vbrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vrev8.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vctz.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vcpop.v v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vrol.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vrol.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vror.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vror.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vror.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsll.vv v8, v4, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsll.vx v8, v4, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vwsll.vi v8, v4, 8
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
new file mode 100644
index 0000000000000..1e304f6b75a14
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvbc.s
@@ -0,0 +1,112 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+# These instructions only work with e64
+
+vsetvli zero, zero, e64, m1, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m2, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m4, tu, mu
+vclmul.vv v4, v8, v12
+vclmul.vx v4, v8, a0
+vclmulh.vv v4, v8, v12
+vclmulh.vx v4, v8, a0
+
+vsetvli zero, zero, e64, m8, tu, mu
+vclmul.vv v8, v12, v24
+vclmul.vx v8, v12, a0
+vclmulh.vv v8, v12, v24
+vclmulh.vx v8, v12, a0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 20
+# CHECK-NEXT: Total Cycles: 58
+# CHECK-NEXT: Total uOps: 20
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.34
+# CHECK-NEXT: IPC: 0.34
+# CHECK-NEXT: Block RThroughput: 60.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 1.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 2.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vclmul.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vclmul.vx v4, v8, a0
+# CHECK-NEXT: 1 2 4.00 vclmulh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vclmulh.vx v4, v8, a0
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vclmul.vv v8, v12, v24
+# CHECK-NEXT: 1 2 8.00 vclmul.vx v8, v12, a0
+# CHECK-NEXT: 1 2 8.00 vclmulh.vv v8, v12, v24
+# CHECK-NEXT: 1 2 8.00 vclmulh.vx v8, v12, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 4.00 - - - - 60.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmul.vx v4, v8, a0
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vclmulh.vx v4, v8, a0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmul.vx v8, v12, a0
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vv v8, v12, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vclmulh.vx v8, v12, a0
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s
new file mode 100644
index 0000000000000..8e498a6781388
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkg.s
@@ -0,0 +1,127 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vghsh.vv v8, v16, v24
+vgmul.vv v8, v16
+
+# Show SEW does not matter
+vsetvli zero, zero, e64, m4, tu, mu
+vghsh.vv v4, v8, v12
+vgmul.vv v4, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 24
+# CHECK-NEXT: Total Cycles: 76
+# CHECK-NEXT: Total uOps: 24
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.32
+# CHECK-NEXT: IPC: 0.32
+# CHECK-NEXT: Block RThroughput: 72.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 8.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 8.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 8.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 1.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 2.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vgmul.vv v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vghsh.vv v8, v16, v24
+# CHECK-NEXT: 1 2 8.00 vgmul.vv v8, v16
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vghsh.vv v4, v8, v12
+# CHECK-NEXT: 1 2 4.00 vgmul.vv v4, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 8.00 - - - - 72.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vgmul.vv v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vghsh.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vgmul.vv v8, v16
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vghsh.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vgmul.vv v4, v8
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s
new file mode 100644
index 0000000000000..791069b87eee1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvkned.s
@@ -0,0 +1,203 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vaesef.vv v4, v8
+vaesef.vs v4, v8
+vaesem.vv v4, v8
+vaesem.vs v4, v8
+vaesdm.vv v4, v8
+vaesdm.vs v4, v8
+vaeskf1.vi v4, v8, 8
+vaeskf2.vi v4, v8, 8
+vaesz.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vaesef.vv v8, v16
+vaesef.vs v8, v16
+vaesem.vv v8, v16
+vaesem.vs v8, v16
+vaesdm.vv v8, v16
+vaesdm.vs v8, v16
+vaeskf1.vi v8, v16, 8
+vaeskf2.vi v8, v16, 8
+vaesz.vs v8, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 50
+# CHECK-NEXT: Total Cycles: 142
+# CHECK-NEXT: Total uOps: 50
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.35
+# CHECK-NEXT: IPC: 0.35
+# CHECK-NEXT: Block RThroughput: 144.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 1.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 1.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 1.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 2.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 2.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 2.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 2.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 2.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 2.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 2.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 2.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 4.00 vaesef.vv v4, v8
+# CHECK-NEXT: 1 2 4.00 vaesef.vs v4, v8
+# CHECK-NEXT: 1 2 4.00 vaesem.vv v4, v8
+# CHECK-NEXT: 1 2 4.00 vaesem.vs v4, v8
+# CHECK-NEXT: 1 2 4.00 vaesdm.vv v4, v8
+# CHECK-NEXT: 1 2 4.00 vaesdm.vs v4, v8
+# CHECK-NEXT: 1 2 4.00 vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: 1 2 4.00 vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: 1 2 4.00 vaesz.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 8.00 vaesef.vv v8, v16
+# CHECK-NEXT: 1 2 8.00 vaesef.vs v8, v16
+# CHECK-NEXT: 1 2 8.00 vaesem.vv v8, v16
+# CHECK-NEXT: 1 2 8.00 vaesem.vs v8, v16
+# CHECK-NEXT: 1 2 8.00 vaesdm.vv v8, v16
+# CHECK-NEXT: 1 2 8.00 vaesdm.vs v8, v16
+# CHECK-NEXT: 1 2 8.00 vaeskf1.vi v8, v16, 8
+# CHECK-NEXT: 1 2 8.00 vaeskf2.vi v8, v16, 8
+# CHECK-NEXT: 1 2 8.00 vaesz.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 5.00 - - - - 144.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesef.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesef.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesem.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesem.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesdm.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesdm.vs v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaeskf1.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaeskf2.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vaesz.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesef.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesef.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesem.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesem.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesdm.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesdm.vs v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaeskf1.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaeskf2.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vaesz.vs v8, v16
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s
new file mode 100644
index 0000000000000..285d21cbd33d5
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvknhb.s
@@ -0,0 +1,152 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+# SEW is only e32 or e64
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsha2ms.vv v8, v16, v24
+vsha2ch.vv v8, v16, v24
+vsha2cl.vv v8, v16, v24
+
+vsetvli zero, zero, e64, m1, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m2, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m4, tu, mu
+vsha2ms.vv v4, v8, v12
+vsha2ch.vv v4, v8, v12
+vsha2cl.vv v4, v8, v12
+
+vsetvli zero, zero, e64, m8, tu, mu
+vsha2ms.vv v8, v16, v24
+vsha2ch.vv v8, v16, v24
+vsha2cl.vv v8, v16, v24
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 32
+# CHECK-NEXT: Total Cycles: 102
+# CHECK-NEXT: Total uOps: 32
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.31
+# CHECK-NEXT: IPC: 0.31
+# CHECK-NEXT: Block RThroughput: 90.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 vsha2cl.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: 1 3 4.00 vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: 1 3 8.00 vsha2cl.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 8.00 - - - - 90.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2cl.vv v8, v16, v24
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ms.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2ch.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsha2cl.vv v4, v8, v12
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ms.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2ch.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsha2cl.vv v8, v16, v24
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s
new file mode 100644
index 0000000000000..127998f34aa38
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksed.s
@@ -0,0 +1,113 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm4k.vi v4, v8, 8
+vsm4r.vv v4, v8
+vsm4r.vs v4, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm4k.vi v8, v16, 8
+vsm4r.vv v8, v16
+vsm4r.vs v8, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 20
+# CHECK-NEXT: Total Cycles: 47
+# CHECK-NEXT: Total uOps: 20
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.43
+# CHECK-NEXT: IPC: 0.43
+# CHECK-NEXT: Block RThroughput: 48.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 1.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 1.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 1.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 1.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 2.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 2.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 4.00 vsm4k.vi v4, v8, 8
+# CHECK-NEXT: 1 3 4.00 vsm4r.vv v4, v8
+# CHECK-NEXT: 1 3 4.00 vsm4r.vs v4, v8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 8.00 vsm4k.vi v8, v16, 8
+# CHECK-NEXT: 1 3 8.00 vsm4r.vv v8, v16
+# CHECK-NEXT: 1 3 8.00 vsm4r.vs v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 5.00 - - - - 48.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm4k.vi v4, v8, 8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm4r.vv v4, v8
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm4r.vs v4, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm4k.vi v8, v16, 8
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm4r.vv v8, v16
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm4r.vs v8, v16
+
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s
new file mode 100644
index 0000000000000..4c7b4dce8b6f4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP400/zvksh.s
@@ -0,0 +1,98 @@
+
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s
+
+# These instructions only support e32
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vsm3me.vv v4, v8, v12
+vsm3c.vi v4, v8, 8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vsm3me.vv v8, v16, v24
+vsm3c.vi v8, v16, 8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 15
+# CHECK-NEXT: Total Cycles: 28
+# CHECK-NEXT: Total uOps: 15
+
+# CHECK: Dispatch Width: 3
+# CHECK-NEXT: uOps Per Cycle: 0.54
+# CHECK-NEXT: IPC: 0.54
+# CHECK-NEXT: Block RThroughput: 25.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 1.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 1.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 4.00 vsm3me.vv v4, v8, v12
+# CHECK-NEXT: 1 3 2.00 vsm3c.vi v4, v8, 8
+# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 8.00 vsm3me.vv v8, v16, v24
+# CHECK-NEXT: 1 3 4.00 vsm3c.vi v8, v16, 8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SiFiveP400Div
+# CHECK-NEXT: [1] - SiFiveP400FEXQ0
+# CHECK-NEXT: [2] - SiFiveP400FloatDiv
+# CHECK-NEXT: [3] - SiFiveP400IEXQ0
+# CHECK-NEXT: [4] - SiFiveP400IEXQ1
+# CHECK-NEXT: [5] - SiFiveP400IEXQ2
+# CHECK-NEXT: [6] - SiFiveP400Load
+# CHECK-NEXT: [7] - SiFiveP400Store
+# CHECK-NEXT: [8] - SiFiveP400VDiv
+# CHECK-NEXT: [9] - SiFiveP400VEXQ0
+# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
+# CHECK-NEXT: [11] - SiFiveP400VLD
+# CHECK-NEXT: [12] - SiFiveP400VST
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
+# CHECK-NEXT: - - - - 5.00 - - - - 25.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm3me.vv v4, v8, v12
+# CHECK-NEXT: - - - - - - - - - 2.00 - - - vsm3c.vi v4, v8, 8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 8.00 - - - vsm3me.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - 4.00 - - - vsm3c.vi v8, v16, 8
+
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