[clang] 3d5cc7e - [X86][AVX10.2] Support AVX10.2-MINMAX new instructions. (#101598)
via cfe-commits
cfe-commits at lists.llvm.org
Sun Aug 4 20:06:06 PDT 2024
Author: Freddy Ye
Date: 2024-08-05T11:06:02+08:00
New Revision: 3d5cc7e1e632b74119af13824dabc346bd248c93
URL: https://github.com/llvm/llvm-project/commit/3d5cc7e1e632b74119af13824dabc346bd248c93
DIFF: https://github.com/llvm/llvm-project/commit/3d5cc7e1e632b74119af13824dabc346bd248c93.diff
LOG: [X86][AVX10.2] Support AVX10.2-MINMAX new instructions. (#101598)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Added:
clang/lib/Headers/avx10_2_512minmaxintrin.h
clang/lib/Headers/avx10_2minmaxintrin.h
clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c
clang/test/CodeGen/X86/avx10_2_512minmax-error.c
clang/test/CodeGen/X86/avx10_2minmax-builtins.c
llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll
llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll
llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt
llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt
llvm/test/MC/X86/avx10.2minmax-32-att.s
llvm/test/MC/X86/avx10.2minmax-32-intel.s
llvm/test/MC/X86/avx10.2minmax-64-att.s
llvm/test/MC/X86/avx10.2minmax-64-intel.s
Modified:
clang/docs/ReleaseNotes.rst
clang/include/clang/Basic/BuiltinsX86.def
clang/lib/Headers/CMakeLists.txt
clang/lib/Headers/immintrin.h
clang/lib/Sema/SemaX86.cpp
llvm/include/llvm/IR/IntrinsicsX86.td
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX10.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86IntrinsicsInfo.h
llvm/test/TableGen/x86-fold-tables.inc
Removed:
################################################################################
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index dcef930b4e4ef..17696ee9ca484 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -230,6 +230,8 @@ X86 Support
found in the file ``clang/www/builtins.py``.
- Support ISA of ``AVX10.2``.
+ * Supported MINMAX intrinsics of ``*_(mask(z)))_minmax(ne)_p[s|d|h|bh]`` and
+ ``*_(mask(z)))_minmax_s[s|d|h]``.
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def
index b117c6d6d9340..c49b5c36da4fc 100644
--- a/clang/include/clang/Basic/BuiltinsX86.def
+++ b/clang/include/clang/Basic/BuiltinsX86.def
@@ -2142,6 +2142,22 @@ TARGET_BUILTIN(__builtin_ia32_vsm4key4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4128, "V4UiV4UiV4Ui", "nV:128:", "sm4")
TARGET_BUILTIN(__builtin_ia32_vsm4rnds4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")
+// AVX10 MINMAX
+TARGET_BUILTIN(__builtin_ia32_vminmaxnepbf16128, "V8yV8yV8yIi", "nV:128:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxnepbf16256, "V16yV16yV16yIi", "nV:256:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxnepbf16512, "V32yV32yV32yIi", "nV:512:", "avx10.2-512")
+TARGET_BUILTIN(__builtin_ia32_vminmaxpd128_mask, "V2dV2dV2dIiV2dUc", "nV:128:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxpd256_round_mask, "V4dV4dV4dIiV4dUcIi", "nV:256:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxpd512_round_mask, "V8dV8dV8dIiV8dUcIi", "nV:512:", "avx10.2-512")
+TARGET_BUILTIN(__builtin_ia32_vminmaxph128_mask, "V8xV8xV8xIiV8xUc", "nV:128:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxph256_round_mask, "V16xV16xV16xIiV16xUsIi", "nV:256:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxph512_round_mask, "V32xV32xV32xIiV32xUiIi", "nV:512:", "avx10.2-512")
+TARGET_BUILTIN(__builtin_ia32_vminmaxps128_mask, "V4fV4fV4fIiV4fUc", "nV:128:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxps256_round_mask, "V8fV8fV8fIiV8fUcIi", "nV:256:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxps512_round_mask, "V16fV16fV16fIiV16fUsIi", "nV:512:", "avx10.2-512")
+TARGET_BUILTIN(__builtin_ia32_vminmaxsd_round_mask, "V2dV2dV2dIiV2dUcIi", "nV:128:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxsh_round_mask, "V8xV8xV8xIiV8xUcIi", "nV:128:", "avx10.2-256")
+TARGET_BUILTIN(__builtin_ia32_vminmaxss_round_mask, "V4fV4fV4fIiV4fUcIi", "nV:128:", "avx10.2-256")
#undef BUILTIN
#undef TARGET_BUILTIN
#undef TARGET_HEADER_BUILTIN
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index b17ab24d625a0..f3d19e38f8f2b 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -147,7 +147,9 @@ set(x86_files
amxcomplexintrin.h
amxfp16intrin.h
amxintrin.h
+ avx10_2_512minmaxintrin.h
avx10_2_512niintrin.h
+ avx10_2minmaxintrin.h
avx10_2niintrin.h
avx2intrin.h
avx512bf16intrin.h
diff --git a/clang/lib/Headers/avx10_2_512minmaxintrin.h b/clang/lib/Headers/avx10_2_512minmaxintrin.h
new file mode 100644
index 0000000000000..e175365d11df8
--- /dev/null
+++ b/clang/lib/Headers/avx10_2_512minmaxintrin.h
@@ -0,0 +1,127 @@
+/*===---- avx10_2_512minmaxintrin.h - AVX10_2_512MINMAX intrinsics ---------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+#ifndef __IMMINTRIN_H
+#error \
+ "Never use <avx10_2_512minmaxintrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __AVX10_2_512MINMAXINTRIN_H
+#define __AVX10_2_512MINMAXINTRIN_H
+
+#define _mm512_minmaxne_pbh(A, B, C) \
+ ((__m512bh)__builtin_ia32_vminmaxnepbf16512( \
+ (__v32bf)(__m512bh)(A), (__v32bf)(__m512bh)(A), (int)(C)))
+
+#define _mm512_mask_minmaxne_pbh(W, U, A, B, C) \
+ ((__m512bh)__builtin_ia32_selectpbf_512( \
+ (__mmask32)(U), \
+ (__v32bf)_mm512_minmaxne_pbh((__v32bf)(__m512bh)(A), \
+ (__v32bf)(__m512bh)(B), (int)(C)), \
+ (__v32bf)(__m512bh)(W)))
+
+#define _mm512_maskz_minmaxne_pbh(U, A, B, C) \
+ ((__m512bh)__builtin_ia32_selectpbf_512( \
+ (__mmask32)(U), \
+ (__v32bf)_mm512_minmaxne_pbh((__v32bf)(__m512bh)(A), \
+ (__v32bf)(__m512bh)(B), (int)(C)), \
+ (__v32bf) __builtin_bit_cast(__m512bh, _mm512_setzero_ps())))
+
+#define _mm512_minmax_pd(A, B, C) \
+ ((__m512d)__builtin_ia32_vminmaxpd512_round_mask( \
+ (__v8df)(__m512d)(A), (__v8df)(__m512d)(B), (int)(C), \
+ (__v8df)_mm512_undefined_pd(), (__mmask8)-1, \
+ _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_mask_minmax_pd(W, U, A, B, C) \
+ ((__m512d)__builtin_ia32_vminmaxpd512_round_mask( \
+ (__v8df)(__m512d)(A), (__v8df)(__m512d)(B), (int)(C), \
+ (__v8df)(__m512d)(W), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_maskz_minmax_pd(U, A, B, C) \
+ ((__m512d)__builtin_ia32_vminmaxpd512_round_mask( \
+ (__v8df)(__m512d)(A), (__v8df)(__m512d)(B), (int)(C), \
+ (__v8df)_mm512_setzero_pd(), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_minmax_round_pd(A, B, C, R) \
+ ((__m512d)__builtin_ia32_vminmaxpd512_round_mask( \
+ (__v8df)(__m512d)(A), (__v8df)(__m512d)(B), (int)(C), \
+ (__v8df)_mm512_undefined_pd(), (__mmask8)-1, (int)(R)))
+
+#define _mm512_mask_minmax_round_pd(W, U, A, B, C, R) \
+ ((__m512d)__builtin_ia32_vminmaxpd512_round_mask( \
+ (__v8df)(__m512d)(A), (__v8df)(__m512d)(B), (int)(C), \
+ (__v8df)(__m512d)(W), (__mmask8)(U), (int)(R)))
+
+#define _mm512_maskz_minmax_round_pd(U, A, B, C, R) \
+ ((__m512d)__builtin_ia32_vminmaxpd512_round_mask( \
+ (__v8df)(__m512d)(A), (__v8df)(__m512d)(B), (int)(C), \
+ (__v8df)_mm512_setzero_pd(), (__mmask8)(U), (int)(R)))
+
+#define _mm512_minmax_ph(A, B, C) \
+ ((__m512h)__builtin_ia32_vminmaxph512_round_mask( \
+ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (int)(C), \
+ (__v32hf)_mm512_undefined_ph(), (__mmask32)-1, \
+ _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_mask_minmax_ph(W, U, A, B, C) \
+ ((__m512h)__builtin_ia32_vminmaxph512_round_mask( \
+ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (int)(C), \
+ (__v32hf)(__m512h)(W), (__mmask32)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_maskz_minmax_ph(U, A, B, C) \
+ ((__m512h)__builtin_ia32_vminmaxph512_round_mask( \
+ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (int)(C), \
+ (__v32hf)_mm512_setzero_ph(), (__mmask32)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_minmax_round_ph(A, B, C, R) \
+ ((__m512h)__builtin_ia32_vminmaxph512_round_mask( \
+ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (int)(C), \
+ (__v32hf)_mm512_undefined_ph(), (__mmask32)-1, (int)(R)))
+
+#define _mm512_mask_minmax_round_ph(W, U, A, B, C, R) \
+ ((__m512h)__builtin_ia32_vminmaxph512_round_mask( \
+ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (int)(C), \
+ (__v32hf)(__m512h)(W), (__mmask32)(U), (int)(R)))
+
+#define _mm512_maskz_minmax_round_ph(U, A, B, C, R) \
+ ((__m512h)__builtin_ia32_vminmaxph512_round_mask( \
+ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (int)(C), \
+ (__v32hf)_mm512_setzero_ph(), (__mmask32)(U), (int)(R)))
+
+#define _mm512_minmax_ps(A, B, C) \
+ ((__m512)__builtin_ia32_vminmaxps512_round_mask( \
+ (__v16sf)(__m512)(A), (__v16sf)(__m512)(B), (int)(C), \
+ (__v16sf)_mm512_undefined_ps(), (__mmask16)-1, \
+ _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_mask_minmax_ps(W, U, A, B, C) \
+ ((__m512)__builtin_ia32_vminmaxps512_round_mask( \
+ (__v16sf)(__m512)(A), (__v16sf)(__m512)(B), (int)(C), (__v16sf)(W), \
+ (__mmask16)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_maskz_minmax_ps(U, A, B, C) \
+ ((__m512)__builtin_ia32_vminmaxps512_round_mask( \
+ (__v16sf)(__m512)(A), (__v16sf)(__m512)(B), (int)(C), \
+ (__v16sf)_mm512_setzero_ps(), (__mmask16)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm512_minmax_round_ps(A, B, C, R) \
+ ((__m512)__builtin_ia32_vminmaxps512_round_mask( \
+ (__v16sf)(__m512)(A), (__v16sf)(__m512)(B), (int)(C), \
+ (__v16sf)_mm512_undefined_ps(), (__mmask16)-1, (int)(R)))
+
+#define _mm512_mask_minmax_round_ps(W, U, A, B, C, R) \
+ ((__m512)__builtin_ia32_vminmaxps512_round_mask( \
+ (__v16sf)(__m512)(A), (__v16sf)(__m512)(B), (int)(C), (__v16sf)(W), \
+ (__mmask16)(U), (int)(R)))
+
+#define _mm512_maskz_minmax_round_ps(U, A, B, C, R) \
+ ((__m512)__builtin_ia32_vminmaxps512_round_mask( \
+ (__v16sf)(__m512)(A), (__v16sf)(__m512)(B), (int)(C), \
+ (__v16sf)_mm512_setzero_ps(), (__mmask16)(U), (int)(R)))
+#endif // __AVX10_2_512MINMAXINTRIN_H
diff --git a/clang/lib/Headers/avx10_2minmaxintrin.h b/clang/lib/Headers/avx10_2minmaxintrin.h
new file mode 100644
index 0000000000000..a9367e7424658
--- /dev/null
+++ b/clang/lib/Headers/avx10_2minmaxintrin.h
@@ -0,0 +1,277 @@
+/*===-------- avx10_2minmaxintrin.h - AVX10_2MINMAX intrinsics -------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+#ifndef __IMMINTRIN_H
+#error \
+ "Never use <avx10_2minmaxintrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __AVX10_2MINMAXINTRIN_H
+#define __AVX10_2MINMAXINTRIN_H
+
+#define _mm_minmaxne_pbh(A, B, C) \
+ ((__m128bh)__builtin_ia32_vminmaxnepbf16128( \
+ (__m128bh)(__v8bf)(A), (__m128bh)(__v8bf)(B), (int)(C)))
+
+#define _mm_mask_minmaxne_pbh(W, U, A, B, C) \
+ ((__m128bh)__builtin_ia32_selectpbf_128( \
+ (__mmask8)(U), \
+ (__v8bf)_mm_minmaxne_pbh((__m128bh)(__v8bf)(A), (__m128bh)(__v8bf)(B), \
+ (int)(C)), \
+ (__v8bf)(W)))
+
+#define _mm_maskz_minmaxne_pbh(U, A, B, C) \
+ ((__m128bh)__builtin_ia32_selectpbf_128( \
+ (__mmask8)(U), \
+ (__v8bf)_mm_minmaxne_pbh((__m128bh)(__v8bf)(A), (__m128bh)(__v8bf)(B), \
+ (int)(C)), \
+ (__v8bf) __builtin_bit_cast(__m128bh, _mm_setzero_ps())))
+
+#define _mm256_minmaxne_pbh(A, B, C) \
+ ((__m256bh)__builtin_ia32_vminmaxnepbf16256( \
+ (__m256bh)(__v16bf)(A), (__m256bh)(__v16bf)(B), (int)(C)))
+
+#define _mm256_mask_minmaxne_pbh(W, U, A, B, C) \
+ ((__m256bh)__builtin_ia32_selectpbf_256( \
+ (__mmask16)(U), \
+ (__v16bf)_mm256_minmaxne_pbh((__m256bh)(__v16bf)(A), \
+ (__m256bh)(__v16bf)(B), (int)(C)), \
+ (__v16bf)(W)))
+
+#define _mm256_maskz_minmaxne_pbh(U, A, B, C) \
+ ((__m256bh)__builtin_ia32_selectpbf_256( \
+ (__mmask16)(U), \
+ (__v16bf)_mm256_minmaxne_pbh((__m256bh)(__v16bf)(A), \
+ (__m256bh)(__v16bf)(B), (int)(C)), \
+ (__v16bf) __builtin_bit_cast(__m256bh, _mm256_setzero_ps())))
+
+#define _mm_minmax_pd(A, B, C) \
+ ((__m128d)__builtin_ia32_vminmaxpd128_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)_mm_setzero_pd(), (__mmask8)-1))
+
+#define _mm_mask_minmax_pd(W, U, A, B, C) \
+ ((__m128d)__builtin_ia32_vminmaxpd128_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)(__m128d)(W), (__mmask8)(U)))
+
+#define _mm_maskz_minmax_pd(U, A, B, C) \
+ ((__m128d)__builtin_ia32_vminmaxpd128_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)_mm_setzero_pd(), (__mmask8)(U)))
+
+#define _mm256_minmax_pd(A, B, C) \
+ ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
+ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
+ (__v4df)_mm256_setzero_pd(), (__mmask8)-1, _MM_FROUND_NO_EXC))
+
+#define _mm256_mask_minmax_pd(W, U, A, B, C) \
+ ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
+ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
+ (__v4df)(__m256d)(W), (__mmask8)(U), _MM_FROUND_NO_EXC))
+
+#define _mm256_maskz_minmax_pd(U, A, B, C) \
+ ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
+ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
+ (__v4df)_mm256_setzero_pd(), (__mmask8)(U), _MM_FROUND_NO_EXC))
+
+#define _mm256_minmax_round_pd(A, B, C, R) \
+ ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
+ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
+ (__v4df)_mm256_undefined_pd(), (__mmask8)-1, (int)(R)))
+
+#define _mm256_mask_minmax_round_pd(W, U, A, B, C, R) \
+ ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
+ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
+ (__v4df)(__m256d)(W), (__mmask8)(U), (int)(R)))
+
+#define _mm256_maskz_minmax_round_pd(U, A, B, C, R) \
+ ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
+ (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
+ (__v4df)_mm256_setzero_pd(), (__mmask8)(U), (int)(R)))
+
+#define _mm_minmax_ph(A, B, C) \
+ ((__m128h)__builtin_ia32_vminmaxph128_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)_mm_setzero_ph(), (__mmask8)-1))
+
+#define _mm_mask_minmax_ph(W, U, A, B, C) \
+ ((__m128h)__builtin_ia32_vminmaxph128_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)(__m128h)(W), (__mmask16)-1))
+
+#define _mm_maskz_minmax_ph(U, A, B, C) \
+ ((__m128h)__builtin_ia32_vminmaxph128_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)_mm_setzero_ph(), (__mmask8)(U)))
+
+#define _mm256_minmax_ph(A, B, C) \
+ ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
+ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
+ (__v16hf)_mm256_setzero_ph(), (__mmask16)-1, _MM_FROUND_NO_EXC))
+
+#define _mm256_mask_minmax_ph(W, U, A, B, C) \
+ ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
+ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
+ (__v16hf)(__m256h)(W), (__mmask16)(U), _MM_FROUND_NO_EXC))
+
+#define _mm256_maskz_minmax_ph(U, A, B, C) \
+ ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
+ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
+ (__v16hf)_mm256_setzero_ph(), (__mmask16)(U), _MM_FROUND_NO_EXC))
+
+#define _mm256_minmax_round_ph(A, B, C, R) \
+ ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
+ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
+ (__v16hf)_mm256_undefined_ph(), (__mmask16)-1, (int)(R)))
+
+#define _mm256_mask_minmax_round_ph(W, U, A, B, C, R) \
+ ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
+ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (C), \
+ (__v16hf)(__m256h)(W), (__mmask16)(U), (int)(R)))
+
+#define _mm256_maskz_minmax_round_ph(U, A, B, C, R) \
+ ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
+ (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
+ (__v16hf)_mm256_setzero_ph(), (__mmask16)(U), (int)(R)))
+
+#define _mm_minmax_ps(A, B, C) \
+ ((__m128)__builtin_ia32_vminmaxps128_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
+ (__v4sf)_mm_setzero_ps(), (__mmask8)-1))
+
+#define _mm_mask_minmax_ps(W, U, A, B, C) \
+ ((__m128)__builtin_ia32_vminmaxps128_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), (__v4sf)(__m128)(W), \
+ (__mmask8)(U)))
+
+#define _mm_maskz_minmax_ps(U, A, B, C) \
+ ((__m128)__builtin_ia32_vminmaxps128_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
+ (__v4sf)_mm_setzero_ps(), (__mmask8)(U)))
+
+#define _mm256_minmax_ps(A, B, C) \
+ ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
+ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
+ (__v8sf)_mm256_setzero_ps(), (__mmask8)-1, _MM_FROUND_NO_EXC))
+
+#define _mm256_mask_minmax_ps(W, U, A, B, C) \
+ ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
+ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), (__v8sf)(__m256)(W), \
+ (__mmask8)(U), _MM_FROUND_NO_EXC))
+
+#define _mm256_maskz_minmax_ps(U, A, B, C) \
+ ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
+ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
+ (__v8sf)_mm256_setzero_ps(), (__mmask8)(U), _MM_FROUND_NO_EXC))
+
+#define _mm256_minmax_round_ps(A, B, C, R) \
+ ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
+ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
+ (__v8sf)_mm256_undefined_ps(), (__mmask8)-1, (int)(R)))
+
+#define _mm256_mask_minmax_round_ps(W, U, A, B, C, R) \
+ ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
+ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), (__v8sf)(__m256)(W), \
+ (__mmask8)(U), (int)(R)))
+
+#define _mm256_maskz_minmax_round_ps(U, A, B, C, R) \
+ ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
+ (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
+ (__v8sf)_mm256_setzero_ps(), (__mmask8)(U), (int)(R)))
+
+#define _mm_minmax_sd(A, B, C) \
+ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)_mm_undefined_pd(), (__mmask8)-1, _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_mask_minmax_sd(W, U, A, B, C) \
+ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)(__m128d)(W), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_maskz_minmax_sd(U, A, B, C) \
+ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)_mm_setzero_pd(), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_minmax_round_sd(A, B, C, R) \
+ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)_mm_undefined_pd(), (__mmask8)-1, (int)(R)))
+
+#define _mm_mask_minmax_round_sd(W, U, A, B, C, R) \
+ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)(__m128d)(W), (__mmask8)(U), (int)(R)))
+
+#define _mm_maskz_minmax_round_sd(U, A, B, C, R) \
+ ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
+ (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \
+ (__v2df)_mm_setzero_pd(), (__mmask8)(U), (int)(R)))
+
+#define _mm_minmax_sh(A, B, C) \
+ ((__m128h)__builtin_ia32_vminmaxsh_round_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)_mm_undefined_ph(), (__mmask8)-1, _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_mask_minmax_sh(W, U, A, B, C) \
+ ((__m128h)__builtin_ia32_vminmaxsh_round_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)(__m128h)(W), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_maskz_minmax_sh(U, A, B, C) \
+ ((__m128h)__builtin_ia32_vminmaxsh_round_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)_mm_setzero_ph(), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_minmax_round_sh(A, B, C, R) \
+ ((__m128h)__builtin_ia32_vminmaxsh_round_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)_mm_undefined_ph(), (__mmask8)-1, (int)(R)))
+
+#define _mm_mask_minmax_round_sh(W, U, A, B, C, R) \
+ ((__m128h)__builtin_ia32_vminmaxsh_round_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)(__m128h)(W), (__mmask8)(U), (int)(R)))
+
+#define _mm_maskz_minmax_round_sh(U, A, B, C, R) \
+ ((__m128h)__builtin_ia32_vminmaxsh_round_mask( \
+ (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
+ (__v8hf)_mm_setzero_ph(), (__mmask8)(U), (int)(R)))
+
+#define _mm_minmax_ss(A, B, C) \
+ ((__m128)__builtin_ia32_vminmaxss_round_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
+ (__v4sf)_mm_undefined_ps(), (__mmask8)-1, _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_mask_minmax_ss(W, U, A, B, C) \
+ ((__m128)__builtin_ia32_vminmaxss_round_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), (__v4sf)(W), \
+ (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_maskz_minmax_ss(U, A, B, C) \
+ ((__m128)__builtin_ia32_vminmaxss_round_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
+ (__v4sf)_mm_setzero_ps(), (__mmask8)(U), _MM_FROUND_CUR_DIRECTION))
+
+#define _mm_minmax_round_ss(A, B, C, R) \
+ ((__m128)__builtin_ia32_vminmaxss_round_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
+ (__v4sf)_mm_undefined_ps(), (__mmask8)-1, (int)(R)))
+
+#define _mm_mask_minmax_round_ss(W, U, A, B, C, R) \
+ ((__m128)__builtin_ia32_vminmaxss_round_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), (__v4sf)(W), \
+ (__mmask8)(U), (int)(R)))
+
+#define _mm_maskz_minmax_round_ss(U, A, B, C, R) \
+ ((__m128)__builtin_ia32_vminmaxss_round_mask( \
+ (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
+ (__v4sf)_mm_setzero_ps(), (__mmask8)(U), (int)(R)))
+#endif // __AVX10_2MINMAXINTRIN_H
diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h
index e0957257ed5c7..6d46bdee20a0d 100644
--- a/clang/lib/Headers/immintrin.h
+++ b/clang/lib/Headers/immintrin.h
@@ -649,10 +649,12 @@ _storebe_i64(void * __P, long long __D) {
#endif
#if !defined(__SCE__) || __has_feature(modules) || defined(__AVX10_2__)
+#include <avx10_2minmaxintrin.h>
#include <avx10_2niintrin.h>
#endif
#if !defined(__SCE__) || __has_feature(modules) || defined(__AVX10_2_512__)
+#include <avx10_2_512minmaxintrin.h>
#include <avx10_2_512niintrin.h>
#endif
diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp
index 5547e980d4bbb..f36b5ea1b01d7 100644
--- a/clang/lib/Sema/SemaX86.cpp
+++ b/clang/lib/Sema/SemaX86.cpp
@@ -158,6 +158,15 @@ bool SemaX86::CheckBuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
case X86::BI__builtin_ia32_rndscalesd_round_mask:
case X86::BI__builtin_ia32_rndscaless_round_mask:
case X86::BI__builtin_ia32_rndscalesh_round_mask:
+ case X86::BI__builtin_ia32_vminmaxpd256_round_mask:
+ case X86::BI__builtin_ia32_vminmaxps256_round_mask:
+ case X86::BI__builtin_ia32_vminmaxph256_round_mask:
+ case X86::BI__builtin_ia32_vminmaxpd512_round_mask:
+ case X86::BI__builtin_ia32_vminmaxps512_round_mask:
+ case X86::BI__builtin_ia32_vminmaxph512_round_mask:
+ case X86::BI__builtin_ia32_vminmaxsd_round_mask:
+ case X86::BI__builtin_ia32_vminmaxsh_round_mask:
+ case X86::BI__builtin_ia32_vminmaxss_round_mask:
ArgNum = 5;
break;
case X86::BI__builtin_ia32_vcvtsd2si64:
@@ -952,6 +961,21 @@ bool SemaX86::CheckBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
case X86::BI__builtin_ia32_vpshrdw128:
case X86::BI__builtin_ia32_vpshrdw256:
case X86::BI__builtin_ia32_vpshrdw512:
+ case X86::BI__builtin_ia32_vminmaxnepbf16128:
+ case X86::BI__builtin_ia32_vminmaxnepbf16256:
+ case X86::BI__builtin_ia32_vminmaxnepbf16512:
+ case X86::BI__builtin_ia32_vminmaxpd128_mask:
+ case X86::BI__builtin_ia32_vminmaxpd256_round_mask:
+ case X86::BI__builtin_ia32_vminmaxph128_mask:
+ case X86::BI__builtin_ia32_vminmaxph256_round_mask:
+ case X86::BI__builtin_ia32_vminmaxps128_mask:
+ case X86::BI__builtin_ia32_vminmaxps256_round_mask:
+ case X86::BI__builtin_ia32_vminmaxpd512_round_mask:
+ case X86::BI__builtin_ia32_vminmaxps512_round_mask:
+ case X86::BI__builtin_ia32_vminmaxph512_round_mask:
+ case X86::BI__builtin_ia32_vminmaxsd_round_mask:
+ case X86::BI__builtin_ia32_vminmaxsh_round_mask:
+ case X86::BI__builtin_ia32_vminmaxss_round_mask:
i = 2;
l = 0;
u = 255;
diff --git a/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c b/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c
new file mode 100644
index 0000000000000..4e80d8b36e194
--- /dev/null
+++ b/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+
+__m512bh test_mm512_minmaxne_pbh(__m512bh __A, __m512bh __B) {
+ // CHECK-LABEL: @test_mm512_minmaxne_pbh(
+ // CHECK: call <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(
+ return _mm512_minmaxne_pbh(__A, __B, 127);
+}
+
+__m512bh test_mm512_mask_minmaxne_pbh(__m512bh __A, __mmask32 __B, __m512bh __C, __m512bh __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmaxne_pbh(
+ // CHECK: call <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(
+ // CHECK: select <32 x i1> %{{.*}}, <32 x bfloat> %{{.*}}, <32 x bfloat> %{{.*}}
+ return _mm512_mask_minmaxne_pbh(__A, __B, __C, __D, 127);
+}
+
+__m512bh test_mm512_maskz_minmaxne_pbh(__mmask32 __A, __m512bh __B, __m512bh __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmaxne_pbh(
+ // CHECK: call <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(
+ // CHECK: zeroinitializer
+ // CHECK: select <32 x i1> %{{.*}}, <32 x bfloat> %{{.*}}, <32 x bfloat> %{{.*}}
+ return _mm512_maskz_minmaxne_pbh(__A, __B, __C, 127);
+}
+
+__m512d test_mm512_minmax_pd(__m512d __A, __m512d __B) {
+ // CHECK-LABEL: @test_mm512_minmax_pd(
+ // CHECK: call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(
+ return _mm512_minmax_pd(__A, __B, 127);
+}
+
+__m512d test_mm512_mask_minmax_pd(__m512d __A, __mmask8 __B, __m512d __C, __m512d __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmax_pd(
+ // CHECK: call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(
+ return _mm512_mask_minmax_pd(__A, __B, __C, __D, 127);
+}
+
+__m512d test_mm512_maskz_minmax_pd(__mmask8 __A, __m512d __B, __m512d __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmax_pd(
+ // CHECK: call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(
+ return _mm512_maskz_minmax_pd(__A, __B, __C, 127);
+}
+
+__m512d test_mm512_minmax_round_pd(__m512d __A, __m512d __B) {
+ // CHECK-LABEL: @test_mm512_minmax_round_pd(
+ // CHECK: call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(
+ return _mm512_minmax_round_pd(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512d test_mm512_mask_minmax_round_pd(__m512d __A, __mmask8 __B, __m512d __C, __m512d __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmax_round_pd(
+ // CHECK: call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(
+ return _mm512_mask_minmax_round_pd(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512d test_mm512_maskz_minmax_round_pd(__mmask8 __A, __m512d __B, __m512d __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmax_round_pd(
+ // CHECK: call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(
+ return _mm512_maskz_minmax_round_pd(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512h test_mm512_minmax_ph(__m512h __A, __m512h __B) {
+ // CHECK-LABEL: @test_mm512_minmax_ph(
+ // CHECK: call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(
+ return _mm512_minmax_ph(__A, __B, 127);
+}
+
+__m512h test_mm512_mask_minmax_ph(__m512h __A, __mmask32 __B, __m512h __C, __m512h __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmax_ph(
+ // CHECK: call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(
+ return _mm512_mask_minmax_ph(__A, __B, __C, __D, 127);
+}
+
+__m512h test_mm512_maskz_minmax_ph(__mmask32 __A, __m512h __B, __m512h __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmax_ph(
+ // CHECK: call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(
+ return _mm512_maskz_minmax_ph(__A, __B, __C, 127);
+}
+
+__m512h test_mm512_minmax_round_ph(__m512h __A, __m512h __B) {
+ // CHECK-LABEL: @test_mm512_minmax_round_ph(
+ // CHECK: call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(
+ return _mm512_minmax_round_ph(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512h test_mm512_mask_minmax_round_ph(__m512h __A, __mmask32 __B, __m512h __C, __m512h __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmax_round_ph(
+ // CHECK: call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(
+ return _mm512_mask_minmax_round_ph(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512h test_mm512_maskz_minmax_round_ph(__mmask32 __A, __m512h __B, __m512h __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmax_round_ph(
+ // CHECK: call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(
+ return _mm512_maskz_minmax_round_ph(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512 test_mm512_minmax_ps(__m512 __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_minmax_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(
+ return _mm512_minmax_ps(__A, __B, 127);
+}
+
+__m512 test_mm512_mask_minmax_ps(__m512 __A, __mmask16 __B, __m512 __C, __m512 __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmax_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(
+ return _mm512_mask_minmax_ps(__A, __B, __C, __D, 127);
+}
+
+__m512 test_mm512_maskz_minmax_ps(__mmask16 __A, __m512 __B, __m512 __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmax_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(
+ return _mm512_maskz_minmax_ps(__A, __B, __C, 127);
+}
+
+__m512 test_mm512_minmax_round_ps(__m512 __A, __m512 __B) {
+ // CHECK-LABEL: @test_mm512_minmax_round_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(
+ return _mm512_minmax_round_ps(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512 test_mm512_mask_minmax_round_ps(__m512 __A, __mmask16 __B, __m512 __C, __m512 __D) {
+ // CHECK-LABEL: @test_mm512_mask_minmax_round_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(
+ return _mm512_mask_minmax_round_ps(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m512 test_mm512_maskz_minmax_round_ps(__mmask16 __A, __m512 __B, __m512 __C) {
+ // CHECK-LABEL: @test_mm512_maskz_minmax_round_ps(
+ // CHECK: call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(
+ return _mm512_maskz_minmax_round_ps(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
diff --git a/clang/test/CodeGen/X86/avx10_2_512minmax-error.c b/clang/test/CodeGen/X86/avx10_2_512minmax-error.c
new file mode 100644
index 0000000000000..15ed7a0b35d82
--- /dev/null
+++ b/clang/test/CodeGen/X86/avx10_2_512minmax-error.c
@@ -0,0 +1,137 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \
+// RUN: -Wno-invalid-feature-combination -emit-llvm -verify
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \
+// RUN: -Wno-invalid-feature-combination -emit-llvm -verify
+
+#include <immintrin.h>
+
+__m128bh test_mm_minmaxne_pbh(__m128bh __A, __m128bh __B) {
+ return _mm_minmaxne_pbh(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128bh test_mm_mask_minmaxne_pbh(__m128bh __A, __mmask8 __B, __m128bh __C, __m128bh __D) {
+ return _mm_mask_minmaxne_pbh(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256bh test_mm256_minmaxne_pbh(__m256bh __A, __m256bh __B) {
+ return _mm256_minmaxne_pbh(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256bh test_mm256_mask_minmaxne_pbh(__m256bh __A, __mmask16 __B, __m256bh __C, __m256bh __D) {
+ return _mm256_mask_minmaxne_pbh(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128d test_mm_minmax_pd(__m128d __A, __m128d __B) {
+ return _mm_minmax_pd(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128d test_mm_mask_minmax_pd(__m128d __A, __mmask8 __B, __m128d __C, __m128d __D) {
+ return _mm_mask_minmax_pd(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256d test_mm256_minmax_pd(__m256d __A, __m256d __B) {
+ return _mm256_minmax_pd(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256d test_mm256_mask_minmax_pd(__m256d __A, __mmask8 __B, __m256d __C, __m256d __D) {
+ return _mm256_mask_minmax_pd(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128h test_mm_minmax_ph(__m128h __A, __m128h __B) {
+ return _mm_minmax_ph(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128h test_mm_mask_minmax_ph(__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) {
+ return _mm_mask_minmax_ph(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256h test_mm256_minmax_ph(__m256h __A, __m256h __B) {
+ return _mm256_minmax_ph(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256h test_mm256_mask_minmax_ph(__m256h __A, __mmask16 __B, __m256h __C, __m256h __D) {
+ return _mm256_mask_minmax_ph(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128 test_mm_minmax_ps(__m128 __A, __m128 __B) {
+ return _mm_minmax_ps(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128 test_mm_mask_minmax_ps(__m128 __A, __mmask8 __B, __m128 __C, __m128 __D) {
+ return _mm_mask_minmax_ps(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256 test_mm256_minmax_ps(__m256 __A, __m256 __B) {
+ return _mm256_minmax_ps(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m256 test_mm256_mask_minmax_ps(__m256 __A, __mmask8 __B, __m256 __C, __m256 __D) {
+ return _mm256_mask_minmax_ps(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m512bh test_mm512_minmaxne_pbh(__m512bh __A, __m512bh __B) {
+ return _mm512_minmaxne_pbh(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m512bh test_mm512_mask_minmaxne_pbh(__m512bh __A, __mmask32 __B, __m512bh __C, __m512bh __D) {
+ return _mm512_mask_minmaxne_pbh(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m512d test_mm512_minmax_pd(__m512d __A, __m512d __B) {
+ return _mm512_minmax_pd(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m512h test_mm512_mask_minmax_ph(__m512h __A, __mmask32 __B, __m512h __C, __m512h __D) {
+ return _mm512_mask_minmax_ph(__A, __B, __C, __D, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m512 test_mm512_minmax_ps(__m512 __A, __m512 __B) {
+ return _mm512_minmax_ps(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128d test_mm_minmax_sd(__m128d __A, __m128d __B) {
+ return _mm_minmax_sd(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128h test_mm_minmax_sh(__m128h __A, __m128h __B) {
+ return _mm_minmax_sh(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m128 test_mm_minmax_ss(__m128 __A, __m128 __B) {
+ return _mm_minmax_ss(__A, __B, 256); // expected-error {{argument value 256 is outside the valid range [0, 255]}}
+}
+
+__m512d test_mm512_minmax_round_pd(__m512d __A, __m512d __B) {
+ return _mm512_minmax_round_pd(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m512h test_mm512_minmax_round_ph(__m512h __A, __m512h __B) {
+ return _mm512_minmax_round_ph(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m512 test_mm512_minmax_round_ps(__m512 __A, __m512 __B) {
+ return _mm512_minmax_round_ps(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m256d test_mm256_minmax_round_pd(__m256d __A, __m256d __B) {
+ return _mm256_minmax_round_pd(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m256h test_mm256_minmax_round_ph(__m256h __A, __m256h __B) {
+ return _mm256_minmax_round_ph(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m256 test_mm256_minmax_round_ps(__m256 __A, __m256 __B) {
+ return _mm256_minmax_round_ps(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+__m128d test_mm_minmax_round_sd(__m128d __A, __m128d __B) {
+ return _mm_minmax_round_sd(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m128h test_mm_minmax_round_sh(__m128h __A, __m128h __B) {
+ return _mm_minmax_round_sh(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
+
+__m128 test_mm_minmax_round_ss(__m128 __A, __m128 __B) {
+ return _mm_minmax_round_ss(__A, __B, 127, 11); // expected-error {{invalid rounding argument}}
+}
diff --git a/clang/test/CodeGen/X86/avx10_2minmax-builtins.c b/clang/test/CodeGen/X86/avx10_2minmax-builtins.c
new file mode 100644
index 0000000000000..1efafe24ab125
--- /dev/null
+++ b/clang/test/CodeGen/X86/avx10_2minmax-builtins.c
@@ -0,0 +1,318 @@
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-256 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-256 \
+// RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+
+__m128bh test_mm_minmaxne_pbh(__m128bh __A, __m128bh __B) {
+ // CHECK-LABEL: @test_mm_minmaxne_pbh(
+ // CHECK: call <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(
+ return _mm_minmaxne_pbh(__A, __B, 127);
+}
+
+__m128bh test_mm_mask_minmaxne_pbh(__m128bh __A, __mmask8 __B, __m128bh __C, __m128bh __D) {
+ // CHECK-LABEL: @test_mm_mask_minmaxne_pbh(
+ // CHECK: call <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(
+ // CHECK: select <8 x i1> %{{.*}}, <8 x bfloat> %{{.*}}, <8 x bfloat> %{{.*}}
+ return _mm_mask_minmaxne_pbh(__A, __B, __C, __D, 127);
+}
+
+__m128bh test_mm_maskz_minmaxne_pbh(__mmask8 __A, __m128bh __B, __m128bh __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmaxne_pbh(
+ // CHECK: call <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(
+ // CHECK: zeroinitializer
+ // CHECK: select <8 x i1> %{{.*}}, <8 x bfloat> %{{.*}}, <8 x bfloat> %{{.*}}
+ return _mm_maskz_minmaxne_pbh(__A, __B, __C, 127);
+}
+
+__m256bh test_mm256_minmaxne_pbh(__m256bh __A, __m256bh __B) {
+ // CHECK-LABEL: @test_mm256_minmaxne_pbh(
+ // CHECK: call <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(
+ return _mm256_minmaxne_pbh(__A, __B, 127);
+}
+
+__m256bh test_mm256_mask_minmaxne_pbh(__m256bh __A, __mmask16 __B, __m256bh __C, __m256bh __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmaxne_pbh(
+ // CHECK: call <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(
+ // CHECK: select <16 x i1> %{{.*}}, <16 x bfloat> %{{.*}}, <16 x bfloat> %{{.*}}
+ return _mm256_mask_minmaxne_pbh(__A, __B, __C, __D, 127);
+}
+
+__m256bh test_mm256_maskz_minmaxne_pbh(__mmask16 __A, __m256bh __B, __m256bh __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmaxne_pbh(
+ // CHECK: call <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(
+ // CHECK: zeroinitializer
+ // CHECK: select <16 x i1> %{{.*}}, <16 x bfloat> %{{.*}}, <16 x bfloat> %{{.*}}
+ return _mm256_maskz_minmaxne_pbh(__A, __B, __C, 127);
+}
+
+__m128d test_mm_minmax_pd(__m128d __A, __m128d __B) {
+ // CHECK-LABEL: @test_mm_minmax_pd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(
+ return _mm_minmax_pd(__A, __B, 127);
+}
+
+__m128d test_mm_mask_minmax_pd(__m128d __A, __mmask8 __B, __m128d __C, __m128d __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_pd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(
+ return _mm_mask_minmax_pd(__A, __B, __C, __D, 127);
+}
+
+__m128d test_mm_maskz_minmax_pd(__mmask8 __A, __m128d __B, __m128d __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_pd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(
+ return _mm_maskz_minmax_pd(__A, __B, __C, 127);
+}
+
+__m256d test_mm256_minmax_pd(__m256d __A, __m256d __B) {
+ // CHECK-LABEL: @test_mm256_minmax_pd(
+ // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(
+ return _mm256_minmax_pd(__A, __B, 127);
+}
+
+__m256d test_mm256_mask_minmax_pd(__m256d __A, __mmask8 __B, __m256d __C, __m256d __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmax_pd(
+ // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(
+ return _mm256_mask_minmax_pd(__A, __B, __C, __D, 127);
+}
+
+__m256d test_mm256_maskz_minmax_pd(__mmask8 __A, __m256d __B, __m256d __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmax_pd(
+ // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(
+ return _mm256_maskz_minmax_pd(__A, __B, __C, 127);
+}
+
+__m256d test_mm256_minmax_round_pd(__m256d __A, __m256d __B) {
+ // CHECK-LABEL: @test_mm256_minmax_round_pd(
+ // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(
+ return _mm256_minmax_round_pd(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m256d test_mm256_mask_minmax_round_pd(__m256d __A, __mmask8 __B, __m256d __C, __m256d __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmax_round_pd(
+ // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(
+ return _mm256_mask_minmax_round_pd(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m256d test_mm256_maskz_minmax_round_pd(__mmask8 __A, __m256d __B, __m256d __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmax_round_pd(
+ // CHECK: call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(
+ return _mm256_maskz_minmax_round_pd(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128h test_mm_minmax_ph(__m128h __A, __m128h __B) {
+ // CHECK-LABEL: @test_mm_minmax_ph(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxph128(
+ return _mm_minmax_ph(__A, __B, 127);
+}
+
+__m128h test_mm_mask_minmax_ph(__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_ph(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxph128(
+ return _mm_mask_minmax_ph(__A, __B, __C, __D, 127);
+}
+
+__m128h test_mm_maskz_minmax_ph(__mmask8 __A, __m128h __B, __m128h __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_ph(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxph128(
+ return _mm_maskz_minmax_ph(__A, __B, __C, 127);
+}
+
+__m256h test_mm256_minmax_ph(__m256h __A, __m256h __B) {
+ // CHECK-LABEL: @test_mm256_minmax_ph(
+ // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(
+ return _mm256_minmax_ph(__A, __B, 127);
+}
+
+__m256h test_mm256_mask_minmax_ph(__m256h __A, __mmask16 __B, __m256h __C, __m256h __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmax_ph(
+ // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(
+ return _mm256_mask_minmax_ph(__A, __B, __C, __D, 127);
+}
+
+__m256h test_mm256_maskz_minmax_ph(__mmask16 __A, __m256h __B, __m256h __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmax_ph(
+ // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(
+ return _mm256_maskz_minmax_ph(__A, __B, __C, 127);
+}
+
+__m256h test_mm256_minmax_round_ph(__m256h __A, __m256h __B) {
+ // CHECK-LABEL: @test_mm256_minmax_round_ph(
+ // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(
+ return _mm256_minmax_round_ph(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m256h test_mm256_mask_minmax_round_ph(__m256h __A, __mmask16 __B, __m256h __C, __m256h __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmax_round_ph(
+ // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(
+ return _mm256_mask_minmax_round_ph(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m256h test_mm256_maskz_minmax_round_ph(__mmask16 __A, __m256h __B, __m256h __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmax_round_ph(
+ // CHECK: call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(
+ return _mm256_maskz_minmax_round_ph(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128 test_mm_minmax_ps(__m128 __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_minmax_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxps128(
+ return _mm_minmax_ps(__A, __B, 127);
+}
+
+__m128 test_mm_mask_minmax_ps(__m128 __A, __mmask8 __B, __m128 __C, __m128 __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxps128(
+ return _mm_mask_minmax_ps(__A, __B, __C, __D, 127);
+}
+
+__m128 test_mm_maskz_minmax_ps(__mmask8 __A, __m128 __B, __m128 __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_ps(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxps128(
+ return _mm_maskz_minmax_ps(__A, __B, __C, 127);
+}
+
+__m256 test_mm256_minmax_ps(__m256 __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_minmax_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(
+ return _mm256_minmax_ps(__A, __B, 127);
+}
+
+__m256 test_mm256_mask_minmax_ps(__m256 __A, __mmask8 __B, __m256 __C, __m256 __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmax_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(
+ return _mm256_mask_minmax_ps(__A, __B, __C, __D, 127);
+}
+
+__m256 test_mm256_maskz_minmax_ps(__mmask8 __A, __m256 __B, __m256 __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmax_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(
+ return _mm256_maskz_minmax_ps(__A, __B, __C, 127);
+}
+
+__m256 test_mm256_minmax_round_ps(__m256 __A, __m256 __B) {
+ // CHECK-LABEL: @test_mm256_minmax_round_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(
+ return _mm256_minmax_round_ps(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m256 test_mm256_mask_minmax_round_ps(__m256 __A, __mmask8 __B, __m256 __C, __m256 __D) {
+ // CHECK-LABEL: @test_mm256_mask_minmax_round_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(
+ return _mm256_mask_minmax_round_ps(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m256 test_mm256_maskz_minmax_round_ps(__mmask8 __A, __m256 __B, __m256 __C) {
+ // CHECK-LABEL: @test_mm256_maskz_minmax_round_ps(
+ // CHECK: call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(
+ return _mm256_maskz_minmax_round_ps(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128d test_mm_minmax_sd(__m128d __A, __m128d __B) {
+ // CHECK-LABEL: @test_mm_minmax_sd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(
+ return _mm_minmax_sd(__A, __B, 127);
+}
+
+__m128d test_mm_mask_minmax_sd(__m128d __A, __mmask8 __B, __m128d __C, __m128d __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_sd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(
+ return _mm_mask_minmax_sd(__A, __B, __C, __D, 127);
+}
+
+__m128d test_mm_maskz_minmax_sd(__mmask8 __A, __m128d __B, __m128d __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_sd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(
+ return _mm_maskz_minmax_sd(__A, __B, __C, 127);
+}
+
+__m128d test_mm_minmax_round_sd(__m128d __A, __m128d __B) {
+ // CHECK-LABEL: @test_mm_minmax_round_sd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(
+ return _mm_minmax_round_sd(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128d test_mm_mask_minmax_round_sd(__m128d __A, __mmask8 __B, __m128d __C, __m128d __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_round_sd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(
+ return _mm_mask_minmax_round_sd(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128d test_mm_maskz_minmax_round_sd(__mmask8 __A, __m128d __B, __m128d __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_round_sd(
+ // CHECK: call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(
+ return _mm_maskz_minmax_round_sd(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128h test_mm_minmax_sh(__m128h __A, __m128h __B) {
+ // CHECK-LABEL: @test_mm_minmax_sh(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(
+ return _mm_minmax_sh(__A, __B, 127);
+}
+
+__m128h test_mm_mask_minmax_sh(__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_sh(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(
+ return _mm_mask_minmax_sh(__A, __B, __C, __D, 127);
+}
+
+__m128h test_mm_maskz_minmax_sh(__mmask8 __A, __m128h __B, __m128h __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_sh(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(
+ return _mm_maskz_minmax_sh(__A, __B, __C, 127);
+}
+
+__m128h test_mm_minmax_round_sh(__m128h __A, __m128h __B) {
+ // CHECK-LABEL: @test_mm_minmax_round_sh(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(
+ return _mm_minmax_round_sh(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128h test_mm_mask_minmax_round_sh(__m128h __A, __mmask8 __B, __m128h __C, __m128h __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_round_sh(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(
+ return _mm_mask_minmax_round_sh(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128h test_mm_maskz_minmax_round_sh(__mmask8 __A, __m128h __B, __m128h __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_round_sh(
+ // CHECK: call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(
+ return _mm_maskz_minmax_round_sh(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128 test_mm_minmax_ss(__m128 __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_minmax_ss(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(
+ return _mm_minmax_ss(__A, __B, 127);
+}
+
+__m128 test_mm_mask_minmax_ss(__m128 __A, __mmask8 __B, __m128 __C, __m128 __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_ss(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(
+ return _mm_mask_minmax_ss(__A, __B, __C, __D, 127);
+}
+
+__m128 test_mm_maskz_minmax_ss(__mmask8 __A, __m128 __B, __m128 __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_ss(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(
+ return _mm_maskz_minmax_ss(__A, __B, __C, 127);
+}
+
+__m128 test_mm_minmax_round_ss(__m128 __A, __m128 __B) {
+ // CHECK-LABEL: @test_mm_minmax_round_ss(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(
+ return _mm_minmax_round_ss(__A, __B, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128 test_mm_mask_minmax_round_ss(__m128 __A, __mmask8 __B, __m128 __C, __m128 __D) {
+ // CHECK-LABEL: @test_mm_mask_minmax_round_ss(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(
+ return _mm_mask_minmax_round_ss(__A, __B, __C, __D, 127, _MM_FROUND_NO_EXC);
+}
+
+__m128 test_mm_maskz_minmax_round_ss(__mmask8 __A, __m128 __B, __m128 __C) {
+ // CHECK-LABEL: @test_mm_maskz_minmax_round_ss(
+ // CHECK: call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(
+ return _mm_maskz_minmax_round_ss(__A, __B, __C, 127, _MM_FROUND_NO_EXC);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td
index 4b80ef2189989..7160c8dfa7600 100644
--- a/llvm/include/llvm/IR/IntrinsicsX86.td
+++ b/llvm/include/llvm/IR/IntrinsicsX86.td
@@ -6832,3 +6832,69 @@ let TargetPrefix = "x86" in {
llvm_i8_ty, llvm_i32_ty ],
[ IntrNoMem, ImmArg<ArgIndex<4>> ]>;
}
+
+let TargetPrefix = "x86" in {
+def int_x86_avx10_vminmaxnepbf16128 : ClangBuiltin<"__builtin_ia32_vminmaxnepbf16128">,
+ Intrinsic<[llvm_v8bf16_ty], [llvm_v8bf16_ty, llvm_v8bf16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_vminmaxnepbf16256 : ClangBuiltin<"__builtin_ia32_vminmaxnepbf16256">,
+ Intrinsic<[llvm_v16bf16_ty], [llvm_v16bf16_ty, llvm_v16bf16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_vminmaxnepbf16512 : ClangBuiltin<"__builtin_ia32_vminmaxnepbf16512">,
+ Intrinsic<[llvm_v32bf16_ty], [llvm_v32bf16_ty, llvm_v32bf16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_vminmaxpd128 : ClangBuiltin<"__builtin_ia32_vminmaxpd128">,
+ Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxpd128 : ClangBuiltin<"__builtin_ia32_vminmaxpd128_mask">,
+ Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_vminmaxpd256 : ClangBuiltin<"__builtin_ia32_vminmaxpd256">,
+ Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxpd256_round : ClangBuiltin<"__builtin_ia32_vminmaxpd256_round_mask">,
+ Intrinsic<[llvm_v4f64_ty], [llvm_v4f64_ty, llvm_v4f64_ty, llvm_i32_ty, llvm_v4f64_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_mask_vminmaxpd_round : ClangBuiltin<"__builtin_ia32_vminmaxpd512_round_mask">,
+ Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty, llvm_i32_ty, llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_vminmaxph128 : ClangBuiltin<"__builtin_ia32_vminmaxph128">,
+ Intrinsic<[llvm_v8f16_ty], [llvm_v8f16_ty, llvm_v8f16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxph128 : ClangBuiltin<"__builtin_ia32_vminmaxph128_mask">,
+ Intrinsic<[llvm_v8f16_ty], [llvm_v8f16_ty, llvm_v8f16_ty, llvm_i32_ty, llvm_v8f16_ty, llvm_i8_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_vminmaxph256 : ClangBuiltin<"__builtin_ia32_vminmaxph256">,
+ Intrinsic<[llvm_v16f16_ty], [llvm_v16f16_ty, llvm_v16f16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxph256_round : ClangBuiltin<"__builtin_ia32_vminmaxph256_round_mask">,
+ Intrinsic<[llvm_v16f16_ty], [llvm_v16f16_ty, llvm_v16f16_ty, llvm_i32_ty, llvm_v16f16_ty, llvm_i16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxph_round : ClangBuiltin<"__builtin_ia32_vminmaxph512_round_mask">,
+ Intrinsic<[llvm_v32f16_ty], [llvm_v32f16_ty, llvm_v32f16_ty, llvm_i32_ty, llvm_v32f16_ty, llvm_i32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_vminmaxps128 : ClangBuiltin<"__builtin_ia32_vminmaxps128">,
+ Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxps128 : ClangBuiltin<"__builtin_ia32_vminmaxps128_mask">,
+ Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_vminmaxps256 : ClangBuiltin<"__builtin_ia32_vminmaxps256">,
+ Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>]>;
+def int_x86_avx10_mask_vminmaxps256_round : ClangBuiltin<"__builtin_ia32_vminmaxps256_round_mask">,
+ Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_v8f32_ty, llvm_i32_ty, llvm_v8f32_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_mask_vminmaxps_round : ClangBuiltin<"__builtin_ia32_vminmaxps512_round_mask">,
+ Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_v16f32_ty, llvm_i32_ty, llvm_v16f32_ty, llvm_i16_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_mask_vminmaxsd_round : ClangBuiltin<"__builtin_ia32_vminmaxsd_round_mask">,
+ Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty, llvm_v2f64_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_mask_vminmaxsh_round : ClangBuiltin<"__builtin_ia32_vminmaxsh_round_mask">,
+ Intrinsic<[llvm_v8f16_ty], [llvm_v8f16_ty, llvm_v8f16_ty, llvm_i32_ty, llvm_v8f16_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+def int_x86_avx10_mask_vminmaxss_round : ClangBuiltin<"__builtin_ia32_vminmaxss_round_mask">,
+ Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_v4f32_ty, llvm_i8_ty, llvm_i32_ty],
+ [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]>;
+}
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 97ac6af00ad6d..fe1865409a265 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34058,6 +34058,10 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(VPDPBUUDS)
NODE_NAME_CASE(VPDPBSSD)
NODE_NAME_CASE(VPDPBSSDS)
+ NODE_NAME_CASE(VMINMAX)
+ NODE_NAME_CASE(VMINMAX_SAE)
+ NODE_NAME_CASE(VMINMAXS)
+ NODE_NAME_CASE(VMINMAXS_SAE)
NODE_NAME_CASE(AESENC128KL)
NODE_NAME_CASE(AESDEC128KL)
NODE_NAME_CASE(AESENC256KL)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 4fd320885d608..7642a528fb22e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -595,6 +595,11 @@ namespace llvm {
VPDPBSSD,
VPDPBSSDS,
+ VMINMAX,
+ VMINMAX_SAE,
+ VMINMAXS,
+ VMINMAXS_SAE,
+
MPSADBW,
// Compress and expand.
diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td
index 24d86ec2e41f6..920317ded15c6 100644
--- a/llvm/lib/Target/X86/X86InstrAVX10.td
+++ b/llvm/lib/Target/X86/X86InstrAVX10.td
@@ -305,3 +305,115 @@ let Predicates = [HasAVX10_2], hasEVEX_U = 1, OpEnc = EncEVEX in {
defm VFCMADDCPHZ256 : avx512_cfmaop_round<0x56, "vfcmaddcph", x86vfcmaddcRnd,
v8f32x_info>, T_MAP6,XD, EVEX_CD8<32, CD8VF>, Sched<[WriteFMAY]>;
}
+
+//-------------------------------------------------
+// AVX10 MINMAX instructions
+//-------------------------------------------------
+
+multiclass avx10_minmax_packed_base<string OpStr, X86VectorVTInfo VTI, SDNode OpNode> {
+ let ExeDomain = VTI.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in {
+ defm rri : AVX512_maskable<0x52, MRMSrcReg, VTI, (outs VTI.RC:$dst),
+ (ins VTI.RC:$src1, VTI.RC:$src2, i32u8imm:$src3), OpStr,
+ "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (VTI.VT (OpNode VTI.RC:$src1, VTI.RC:$src2,
+ (i32 timm:$src3)))>,
+ EVEX, VVVV, Sched<[WriteFMAX]>;
+ defm rmi : AVX512_maskable<0x52, MRMSrcMem, VTI, (outs VTI.RC:$dst),
+ (ins VTI.RC:$src1, VTI.MemOp:$src2, i32u8imm:$src3), OpStr,
+ "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (VTI.VT (OpNode VTI.RC:$src1, (VTI.LdFrag addr:$src2),
+ (i32 timm:$src3)))>,
+ EVEX, VVVV,
+ Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
+ defm rmbi : AVX512_maskable<0x52, MRMSrcMem, VTI, (outs VTI.RC:$dst),
+ (ins VTI.RC:$src1, VTI.ScalarMemOp:$src2, i32u8imm:$src3),
+ OpStr, "$src3, ${src2}"#VTI.BroadcastStr#", $src1",
+ "$src1, ${src2}"#VTI.BroadcastStr#", $src3",
+ (VTI.VT (OpNode VTI.RC:$src1, (VTI.BroadcastLdFrag addr:$src2),
+ (i32 timm:$src3)))>,
+ EVEX, VVVV, EVEX_B,
+ Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
+ }
+}
+
+multiclass avx10_minmax_packed_sae<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> {
+ let Uses = []<Register>, mayRaiseFPException = 0 in {
+ defm Zrrib : AVX512_maskable<0x52, MRMSrcReg, VTI.info512, (outs VTI.info512.RC:$dst),
+ (ins VTI.info512.RC:$src1, VTI.info512.RC:$src2, i32u8imm:$src3), OpStr,
+ "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
+ (VTI.info512.VT (OpNode (VTI.info512.VT VTI.info512.RC:$src1),
+ (VTI.info512.VT VTI.info512.RC:$src2),
+ (i32 timm:$src3)))>,
+ EVEX, VVVV, EVEX_B, EVEX_V512, Sched<[WriteFMAX]>;
+ let hasEVEX_U = 1 in
+ defm Z256rrib : AVX512_maskable<0x52, MRMSrcReg, VTI.info256, (outs VTI.info256.RC:$dst),
+ (ins VTI.info256.RC:$src1, VTI.info256.RC:$src2, i32u8imm:$src3), OpStr,
+ "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
+ (VTI.info256.VT (OpNode (VTI.info256.VT VTI.info256.RC:$src1),
+ (VTI.info256.VT VTI.info256.RC:$src2),
+ (i32 timm:$src3)))>,
+ EVEX, VVVV, EVEX_B, EVEX_V256, Sched<[WriteFMAX]>;
+ }
+}
+
+multiclass avx10_minmax_packed<string OpStr, AVX512VLVectorVTInfo VTI, SDNode OpNode> {
+ let Predicates = [HasAVX10_2_512] in
+ defm Z : avx10_minmax_packed_base<OpStr, VTI.info512, OpNode>, EVEX_V512;
+ let Predicates = [HasAVX10_2] in {
+ defm Z256 : avx10_minmax_packed_base<OpStr, VTI.info256, OpNode>, EVEX_V256;
+ defm Z128 : avx10_minmax_packed_base<OpStr, VTI.info128, OpNode>, EVEX_V128;
+ }
+}
+
+multiclass avx10_minmax_scalar<string OpStr, X86VectorVTInfo _, SDNode OpNode,
+ SDNode OpNodeSAE> {
+ let ExeDomain = _.ExeDomain, Predicates = [HasAVX10_2] in {
+ let mayRaiseFPException = 1 in {
+ defm rri : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
+ (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
+ OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (_.VT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
+ (i32 timm:$src3)))>,
+ Sched<[WriteFMAX]>;
+
+ defm rmi : AVX512_maskable<0x53, MRMSrcMem, _, (outs VR128X:$dst),
+ (ins VR128X:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
+ OpStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
+ (_.VT (OpNode (_.VT _.RC:$src1), (_.ScalarIntMemFrags addr:$src2),
+ (i32 timm:$src3)))>,
+ Sched<[WriteFMAX.Folded, WriteFMAX.ReadAfterFold]>;
+ }
+ let Uses = []<Register>, mayRaiseFPException = 0 in
+ defm rrib : AVX512_maskable<0x53, MRMSrcReg, _, (outs VR128X:$dst),
+ (ins VR128X:$src1, VR128X:$src2, i32u8imm:$src3),
+ OpStr, "$src3, {sae}, $src2, $src1",
+ "$src1, $src2, {sae}, $src3",
+ (_.VT (OpNodeSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
+ (i32 timm:$src3)))>,
+ Sched<[WriteFMAX]>, EVEX_B;
+ }
+}
+
+
+let mayRaiseFPException = 0 in
+defm VMINMAXNEPBF16 : avx10_minmax_packed<"vminmaxnepbf16", avx512vl_bf16_info, X86vminmax>,
+ AVX512XDIi8Base, EVEX_CD8<16, CD8VF>, TA;
+
+defm VMINMAXPD : avx10_minmax_packed<"vminmaxpd", avx512vl_f64_info, X86vminmax>,
+ avx10_minmax_packed_sae<"vminmaxpd", avx512vl_f64_info, X86vminmaxSae>,
+ AVX512PDIi8Base, REX_W, TA, EVEX_CD8<64, CD8VF>;
+
+defm VMINMAXPH : avx10_minmax_packed<"vminmaxph", avx512vl_f16_info, X86vminmax>,
+ avx10_minmax_packed_sae<"vminmaxph", avx512vl_f16_info, X86vminmaxSae>,
+ AVX512PSIi8Base, TA, EVEX_CD8<16, CD8VF>;
+
+defm VMINMAXPS : avx10_minmax_packed<"vminmaxps", avx512vl_f32_info, X86vminmax>,
+ avx10_minmax_packed_sae<"vminmaxps", avx512vl_f32_info, X86vminmaxSae>,
+ AVX512PDIi8Base, TA, EVEX_CD8<32, CD8VF>;
+
+defm VMINMAXSD : avx10_minmax_scalar<"vminmaxsd", v2f64x_info, X86vminmaxs, X86vminmaxsSae>,
+ AVX512AIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<64, CD8VT1>, REX_W;
+defm VMINMAXSH : avx10_minmax_scalar<"vminmaxsh", v8f16x_info, X86vminmaxs, X86vminmaxsSae>,
+ AVX512PSIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<16, CD8VT1>, TA;
+defm VMINMAXSS : avx10_minmax_scalar<"vminmaxss", v4f32x_info, X86vminmaxs, X86vminmaxsSae>,
+ AVX512AIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<32, CD8VT1>;
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 74596cec5c5ef..11b75240b2504 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -772,6 +772,16 @@ def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
SDTCisOpSmallerThanOp<0, 1>,
SDTCisVT<2, i32>]>>;
+def X86vminmax : SDNode<"X86ISD::VMINMAX", SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
+ SDTCisSameAs<0,2>, SDTCisInt<3>]>>;
+def X86vminmaxSae : SDNode<"X86ISD::VMINMAX_SAE", SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
+ SDTCisSameAs<0,2>, SDTCisInt<3>]>>;
+
+def X86vminmaxs : SDNode<"X86ISD::VMINMAXS", SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
+ SDTCisSameAs<0,2>, SDTCisInt<3>]>>;
+def X86vminmaxsSae : SDNode<"X86ISD::VMINMAXS_SAE", SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
+ SDTCisSameAs<0,2>, SDTCisInt<3>]>>;
+
// cvt fp to bfloat16
def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16",
SDTypeProfile<1, 2, [SDTCVecEltisVT<0, bf16>,
diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
index 70b9adeb7418f..a7473e495330b 100644
--- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h
+++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h
@@ -486,6 +486,30 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::VGETMANT, X86ISD::VGETMANT_SAE),
X86_INTRINSIC_DATA(avx10_mask_vgetmantps256, INTR_TYPE_2OP_MASK_SAE,
X86ISD::VGETMANT, X86ISD::VGETMANT_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxpd_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, X86ISD::VMINMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxpd128, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxpd256_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, X86ISD::VMINMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxph_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, X86ISD::VMINMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxph128, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxph256_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, X86ISD::VMINMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxps_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, X86ISD::VMINMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxps128, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, 0),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxps256_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAX, X86ISD::VMINMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxsd_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAXS, X86ISD::VMINMAXS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxsh_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAXS, X86ISD::VMINMAXS_SAE),
+ X86_INTRINSIC_DATA(avx10_mask_vminmaxss_round, INTR_TYPE_3OP_MASK_SAE,
+ X86ISD::VMINMAXS, X86ISD::VMINMAXS_SAE),
X86_INTRINSIC_DATA(avx10_mask_vrangepd256, INTR_TYPE_3OP_MASK_SAE,
X86ISD::VRANGE, X86ISD::VRANGE_SAE),
X86_INTRINSIC_DATA(avx10_mask_vrangeps256, INTR_TYPE_3OP_MASK_SAE,
@@ -546,6 +570,12 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
X86ISD::FMAX_SAE),
X86_INTRINSIC_DATA(avx10_vmaxps256, INTR_TYPE_2OP_SAE, X86ISD::FMAX,
X86ISD::FMAX_SAE),
+ X86_INTRINSIC_DATA(avx10_vminmaxnepbf16128, INTR_TYPE_3OP, X86ISD::VMINMAX,
+ 0),
+ X86_INTRINSIC_DATA(avx10_vminmaxnepbf16256, INTR_TYPE_3OP, X86ISD::VMINMAX,
+ 0),
+ X86_INTRINSIC_DATA(avx10_vminmaxnepbf16512, INTR_TYPE_3OP, X86ISD::VMINMAX,
+ 0),
X86_INTRINSIC_DATA(avx10_vminpd256, INTR_TYPE_2OP_SAE, X86ISD::FMIN,
X86ISD::FMIN_SAE),
X86_INTRINSIC_DATA(avx10_vminph256, INTR_TYPE_2OP_SAE, X86ISD::FMIN,
diff --git a/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll
new file mode 100644
index 0000000000000..260451f0f6822
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll
@@ -0,0 +1,353 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=X86
+
+define <32 x bfloat> @test_int_x86_avx10_vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxnepbf16512:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxnepbf16 $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7f,0x48,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxnepbf16512:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxnepbf16 $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7f,0x48,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B, i32 127)
+ ret <32 x bfloat> %ret
+}
+
+define <32 x bfloat> @test_int_x86_avx10_mask_vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B, <32 x bfloat> %C, i32 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxnepbf16512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxnepbf16 $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7f,0x49,0x52,0xd1,0x7f]
+; X64-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxnepbf16512:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxnepbf16 $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7f,0x49,0x52,0xd1,0x7f]
+; X86-NEXT: vmovdqa64 %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %0 = call <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B, i32 127)
+ %1 = bitcast i32 %D to <32 x i1>
+ %2 = select reassoc nsz arcp contract afn <32 x i1> %1, <32 x bfloat> %0, <32 x bfloat> %C
+ ret <32 x bfloat> %2
+}
+
+declare <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B, i32 %C)
+
+define <32 x bfloat> @test_int_x86_avx10_maskz_vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B, i32 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxnepbf16512:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxnepbf16 $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7f,0xc9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxnepbf16512:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxnepbf16 $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7f,0xc9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %0 = call <32 x bfloat> @llvm.x86.avx10.vminmaxnepbf16512(<32 x bfloat> %A, <32 x bfloat> %B, i32 127)
+ %1 = bitcast i32 %C to <32 x i1>
+ %2 = select reassoc nsz arcp contract afn <32 x i1> %1, <32 x bfloat> %0, <32 x bfloat> zeroinitializer
+ ret <32 x bfloat> %2
+}
+
+define <8 x double>@test_int_x86_vminmaxpd(<8 x double> %A, <8 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxpd:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxpd $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0xfd,0x48,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxpd:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxpd $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0xfd,0x48,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 127, <8 x double> undef, i8 -1, i32 4)
+ ret <8 x double> %ret
+}
+
+define <8 x double>@test_int_x86_mask_vminmaxpd(<8 x double> %A, <8 x double> %B, <8 x double> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxpd:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxpd:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 127, <8 x double> %C, i8 %D, i32 4)
+ ret <8 x double> %ret
+}
+
+define <8 x double>@test_int_x86_maskz_vminmaxpd(<8 x double> %A, <8 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxpd:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0xc9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxpd:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0xc9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 127, <8 x double> zeroinitializer, i8 %C, i32 4)
+ ret <8 x double> %ret
+}
+
+define <8 x double>@test_int_x86_vminmaxpd_round(<8 x double> %A, <8 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxpd_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxpd $127, {sae}, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0xfd,0x18,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxpd_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxpd $127, {sae}, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0xfd,0x18,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 127, <8 x double> undef, i8 -1, i32 8)
+ ret <8 x double> %ret
+}
+
+define <8 x double>@test_int_x86_mask_vminmaxpd_round(<8 x double> %A, <8 x double> %B, <8 x double> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxpd_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, {sae}, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x19,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxpd_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, {sae}, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x19,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 127, <8 x double> %C, i8 %D, i32 8)
+ ret <8 x double> %ret
+}
+
+define <8 x double>@test_int_x86_maskz_vminmaxpd_round(<8 x double> %A, <8 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxpd_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x99,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxpd_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x99,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 127, <8 x double> zeroinitializer, i8 %C, i32 8)
+ ret <8 x double> %ret
+}
+
+declare<8 x double> @llvm.x86.avx10.mask.vminmaxpd.round(<8 x double> %A, <8 x double> %B, i32 %C, <8 x double> %D, i8 %E, i32 %F)
+
+define <32 x half>@test_int_x86_vminmaxph(<32 x half> %A, <32 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxph:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxph $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7c,0x48,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxph:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxph $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7c,0x48,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 127, <32 x half> undef, i32 -1, i32 4)
+ ret <32 x half> %ret
+}
+
+define <32 x half>@test_int_x86_mask_vminmaxph(<32 x half> %A, <32 x half> %B, <32 x half> %C, i32 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxph:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x49,0x52,0xd1,0x7f]
+; X64-NEXT: vmovaps %zmm2, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxph:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x49,0x52,0xd1,0x7f]
+; X86-NEXT: vmovaps %zmm2, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 127, <32 x half> %C, i32 %D, i32 4)
+ ret <32 x half> %ret
+}
+
+define <32 x half>@test_int_x86_maskz_vminmaxph(<32 x half> %A, <32 x half> %B, i32 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxph:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0xc9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxph:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0xc9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 127, <32 x half> zeroinitializer, i32 %C, i32 4)
+ ret <32 x half> %ret
+}
+
+define <32 x half>@test_int_x86_vminmaxph_round(<32 x half> %A, <32 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxph_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxph $127, {sae}, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7c,0x18,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxph_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxph $127, {sae}, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7c,0x18,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 127, <32 x half> undef, i32 -1, i32 8)
+ ret <32 x half> %ret
+}
+
+define <32 x half>@test_int_x86_mask_vminmaxph_round(<32 x half> %A, <32 x half> %B, <32 x half> %C, i32 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxph_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, {sae}, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x19,0x52,0xd1,0x7f]
+; X64-NEXT: vmovaps %zmm2, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxph_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, {sae}, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x19,0x52,0xd1,0x7f]
+; X86-NEXT: vmovaps %zmm2, %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 127, <32 x half> %C, i32 %D, i32 8)
+ ret <32 x half> %ret
+}
+
+define <32 x half>@test_int_x86_maskz_vminmaxph_round(<32 x half> %A, <32 x half> %B, i32 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxph_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x99,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxph_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x99,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 127, <32 x half> zeroinitializer, i32 %C, i32 8)
+ ret <32 x half> %ret
+}
+
+declare<32 x half> @llvm.x86.avx10.mask.vminmaxph.round(<32 x half> %A, <32 x half> %B, i32 %C, <32 x half> %D, i32 %E, i32 %F)
+
+define <16 x float>@test_int_x86_vminmaxps(<16 x float> %A, <16 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxps:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxps $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7d,0x48,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxps:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxps $127, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7d,0x48,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 127, <16 x float> undef, i16 -1, i32 4)
+ ret <16 x float> %ret
+}
+
+define <16 x float>@test_int_x86_mask_vminmaxps(<16 x float> %A, <16 x float> %B, <16 x float> %C, i16 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxps:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxps:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 127, <16 x float> %C, i16 %D, i32 4)
+ ret <16 x float> %ret
+}
+
+define <16 x float>@test_int_x86_maskz_vminmaxps(<16 x float> %A, <16 x float> %B, i16 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxps:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xc9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxps:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xc9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 127, <16 x float> zeroinitializer, i16 %C, i32 4)
+ ret <16 x float> %ret
+}
+
+define <16 x float>@test_int_x86_vminmaxps_round(<16 x float> %A, <16 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxps_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxps $127, {sae}, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7d,0x18,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxps_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxps $127, {sae}, %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf3,0x7d,0x18,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 127, <16 x float> undef, i16 -1, i32 8)
+ ret <16 x float> %ret
+}
+
+define <16 x float>@test_int_x86_mask_vminmaxps_round(<16 x float> %A, <16 x float> %B, <16 x float> %C, i16 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxps_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, {sae}, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x19,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxps_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, {sae}, %zmm1, %zmm0, %zmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x19,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %zmm2, %zmm0 # encoding: [0x62,0xf1,0xfd,0x48,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 127, <16 x float> %C, i16 %D, i32 8)
+ ret <16 x float> %ret
+}
+
+define <16 x float>@test_int_x86_maskz_vminmaxps_round(<16 x float> %A, <16 x float> %B, i16 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxps_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x99,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxps_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, {sae}, %zmm1, %zmm0, %zmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x99,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 127, <16 x float> zeroinitializer, i16 %C, i32 8)
+ ret <16 x float> %ret
+}
+
+declare<16 x float> @llvm.x86.avx10.mask.vminmaxps.round(<16 x float> %A, <16 x float> %B, i32 %C, <16 x float> %D, i16 %E, i32 %F)
diff --git a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll
new file mode 100644
index 0000000000000..fd6a01a4a3b69
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll
@@ -0,0 +1,852 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=X86
+
+define <8 x bfloat> @test_int_x86_avx10_vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxnepbf16128:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxnepbf16 $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7f,0x08,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxnepbf16128:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxnepbf16 $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7f,0x08,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B, i32 127)
+ ret <8 x bfloat> %ret
+}
+
+define <8 x bfloat> @test_int_x86_avx10_mask_vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B, <8 x bfloat> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxnepbf16128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxnepbf16 $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7f,0x09,0x52,0xd1,0x7f]
+; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxnepbf16128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxnepbf16 $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7f,0x09,0x52,0xd1,0x7f]
+; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %0 = call <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B, i32 127)
+ %1 = bitcast i8 %D to <8 x i1>
+ %2 = select reassoc nsz arcp contract afn <8 x i1> %1, <8 x bfloat> %0, <8 x bfloat> %C
+ ret <8 x bfloat> %2
+}
+
+declare <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B, i32 %C)
+
+define <8 x bfloat> @test_int_x86_avx10_maskz_vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxnepbf16128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxnepbf16 $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7f,0x89,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxnepbf16128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxnepbf16 $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7f,0x89,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %0 = call <8 x bfloat> @llvm.x86.avx10.vminmaxnepbf16128(<8 x bfloat> %A, <8 x bfloat> %B, i32 127)
+ %1 = bitcast i8 %C to <8 x i1>
+ %2 = select reassoc nsz arcp contract afn <8 x i1> %1, <8 x bfloat> %0, <8 x bfloat> zeroinitializer
+ ret <8 x bfloat> %2
+}
+
+define <16 x bfloat> @test_int_x86_avx10_vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxnepbf16256:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxnepbf16 $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7f,0x28,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxnepbf16256:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxnepbf16 $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7f,0x28,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %ret = call <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B, i32 127)
+ ret <16 x bfloat> %ret
+}
+
+define <16 x bfloat> @test_int_x86_avx10_mask_vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B, <16 x bfloat> %C, i16 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxnepbf16256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxnepbf16 $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7f,0x29,0x52,0xd1,0x7f]
+; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxnepbf16256:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxnepbf16 $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7f,0x29,0x52,0xd1,0x7f]
+; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %0 = call <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B, i32 127)
+ %1 = bitcast i16 %D to <16 x i1>
+ %2 = select reassoc nsz arcp contract afn <16 x i1> %1, <16 x bfloat> %0, <16 x bfloat> %C
+ ret <16 x bfloat> %2
+}
+
+declare <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B, i32 %C)
+
+define <16 x bfloat> @test_int_x86_avx10_maskz_vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B, i16 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxnepbf16256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxnepbf16 $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7f,0xa9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxnepbf16256:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxnepbf16 $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7f,0xa9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+entry:
+ %0 = call <16 x bfloat> @llvm.x86.avx10.vminmaxnepbf16256(<16 x bfloat> %A, <16 x bfloat> %B, i32 127)
+ %1 = bitcast i16 %C to <16 x i1>
+ %2 = select reassoc nsz arcp contract afn <16 x i1> %1, <16 x bfloat> %0, <16 x bfloat> zeroinitializer
+ ret <16 x bfloat> %2
+}
+
+define <2 x double> @test_int_x86_avx10_vminmaxpd128(<2 x double> %A, <2 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxpd128:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxpd $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxpd128:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxpd $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> zeroinitializer, i8 -1)
+ ret <2 x double> %ret
+}
+
+define <2 x double> @test_int_x86_avx10_mask_vminmaxpd128(<2 x double> %A, <2 x double> %B, <2 x double> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxpd128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxpd128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> %C, i8 %D)
+ ret <2 x double> %ret
+}
+
+declare <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(<2 x double> %A, <2 x double> %B, i32 %C, <2 x double> %D, i8 %E)
+
+define <2 x double> @test_int_x86_avx10_maskz_vminmaxpd128(<2 x double> %A, <2 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxpd128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x89,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxpd128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x89,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxpd128(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> zeroinitializer, i8 %C)
+ ret <2 x double> %ret
+}
+
+define <4 x double> @test_int_x86_avx10_vminmaxpd256(<4 x double> %A, <4 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxpd256:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xfd,0x28,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxpd256:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xfd,0x28,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 -1, i32 4)
+ ret <4 x double> %ret
+}
+
+define <4 x double> @test_int_x86_avx10_mask_vminmaxpd256(<4 x double> %A, <4 x double> %B, <4 x double> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxpd256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxpd256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> %C, i8 %D, i32 4)
+ ret <4 x double> %ret
+}
+
+declare <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 %C, <4 x double> %D, i8 %E, i32 %F)
+
+define <4 x double> @test_int_x86_avx10_maskz_vminmaxpd256(<4 x double> %A, <4 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxpd256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0xa9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxpd256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0xa9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 %C, i32 4)
+ ret <4 x double> %ret
+}
+
+define <4 x double>@test_int_x86_vminmaxpd256_round(<4 x double> %A, <4 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxpd256_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xf9,0x18,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxpd256_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0xf9,0x18,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> undef, i8 -1, i32 8)
+ ret <4 x double> %ret
+}
+
+define <4 x double>@test_int_x86_mask_vminmaxpd256_round(<4 x double> %C, <4 x double> %A, <4 x double> %B, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxpd256_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0xf1,0x19,0x52,0xc2,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxpd256_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0xf1,0x19,0x52,0xc2,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> %C, i8 %D, i32 8)
+ ret <4 x double> %ret
+}
+
+define <4 x double>@test_int_x86_maskz_vminmaxpd256_round(<4 x double> %A, <4 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxpd256_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xf9,0x99,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxpd256_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxpd $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0xf9,0x99,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x double> @llvm.x86.avx10.mask.vminmaxpd256.round(<4 x double> %A, <4 x double> %B, i32 127, <4 x double> zeroinitializer, i8 %C, i32 8)
+ ret <4 x double> %ret
+}
+
+define <8 x half> @test_int_x86_avx10_vminmaxph128(<8 x half> %A, <8 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxph128:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxph $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x08,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxph128:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxph $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x08,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxph128(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> zeroinitializer, i8 -1)
+ ret <8 x half> %ret
+}
+
+
+define <8 x half> @test_int_x86_avx10_mask_vminmaxph128(<8 x half> %A, <8 x half> %B, <8 x half> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxph128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x09,0x52,0xd1,0x7f]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxph128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x09,0x52,0xd1,0x7f]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxph128(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> %C, i8 %D)
+ ret <8 x half> %ret
+}
+
+declare <8 x half> @llvm.x86.avx10.mask.vminmaxph128(<8 x half> %A, <8 x half> %B, i32 %C, <8 x half> %D, i8 %E)
+
+define <8 x half> @test_int_x86_avx10_maskz_vminmaxph128(<8 x half> %A, <8 x half> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxph128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x89,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxph128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x89,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxph128(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> zeroinitializer, i8 %C)
+ ret <8 x half> %ret
+}
+
+define <16 x half> @test_int_x86_avx10_vminmaxph256(<16 x half> %A, <16 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxph256:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7c,0x28,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxph256:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7c,0x28,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 -1, i32 4)
+ ret <16 x half> %ret
+}
+
+declare <16 x half> @llvm.x86.avx10.vminmaxph256(<16 x half> %A, <16 x half> %B, i32 %C)
+
+define <16 x half> @test_int_x86_avx10_mask_vminmaxph256(<16 x half> %A, <16 x half> %B, <16 x half> %C, i16 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxph256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x29,0x52,0xd1,0x7f]
+; X64-NEXT: vmovaps %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxph256:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x29,0x52,0xd1,0x7f]
+; X86-NEXT: vmovaps %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> %C, i16 %D, i32 4)
+ ret <16 x half> %ret
+}
+
+declare <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 %C, <16 x half> %D, i16 %E, i32 %F)
+
+define <16 x half> @test_int_x86_avx10_maskz_vminmaxph256(<16 x half> %A, <16 x half> %B, i16 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxph256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0xa9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxph256:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0xa9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 %C, i32 4)
+ ret <16 x half> %ret
+}
+
+define <16 x half> @test_int_x86_vminmaxph256_round(<16 x half> %A, <16 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxph256_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x78,0x18,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxph256_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x78,0x18,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> undef, i16 -1, i32 8)
+ ret <16 x half> %ret
+}
+
+define <16 x half> @test_int_x86_mask_vminmaxph256_round(<16 x half> %C, <16 x half> %A, <16 x half> %B, i16 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxph256_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x70,0x19,0x52,0xc2,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxph256_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, {sae}, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x70,0x19,0x52,0xc2,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> %C, i16 %D, i32 8)
+ ret <16 x half> %ret
+}
+
+define <16 x half> @test_int_x86_maskz_vminmaxph256_round(<16 x half> %A, <16 x half> %B, i16 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxph256_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x78,0x99,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxph256_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxph $127, {sae}, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x78,0x99,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <16 x half> @llvm.x86.avx10.mask.vminmaxph256.round(<16 x half> %A, <16 x half> %B, i32 127, <16 x half> zeroinitializer, i16 %C, i32 8)
+ ret <16 x half> %ret
+}
+
+define <4 x float> @test_int_x86_avx10_vminmaxps128(<4 x float> %A, <4 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxps128:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxps $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x08,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxps128:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxps $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x08,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxps128(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> zeroinitializer, i8 -1)
+ ret <4 x float> %ret
+}
+
+
+define <4 x float> @test_int_x86_avx10_mask_vminmaxps128(<4 x float> %A, <4 x float> %B, <4 x float> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxps128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxps128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxps128(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> %C, i8 %D)
+ ret <4 x float> %ret
+}
+
+declare <4 x float> @llvm.x86.avx10.mask.vminmaxps128(<4 x float> %A, <4 x float> %B, i32 %C, <4 x float> %D, i8 %E)
+
+define <4 x float> @test_int_x86_avx10_maskz_vminmaxps128(<4 x float> %A, <4 x float> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxps128:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x89,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxps128:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x89,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxps128(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> zeroinitializer, i8 %C)
+ ret <4 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_vminmaxps256(<8 x float> %A, <8 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_avx10_vminmaxps256:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_vminmaxps256:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 -1, i32 4)
+ ret <8 x float> %ret
+}
+
+define <8 x float> @test_int_x86_avx10_mask_vminmaxps256(<8 x float> %A, <8 x float> %B, <8 x float> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_avx10_mask_vminmaxps256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x52,0xd1,0x7f]
+; X64-NEXT: vmovapd %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_mask_vminmaxps256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x52,0xd1,0x7f]
+; X86-NEXT: vmovapd %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> %C, i8 %D, i32 4)
+ ret <8 x float> %ret
+}
+
+declare <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 %C, <8 x float> %D, i8 %E, i32 %F)
+
+define <8 x float> @test_int_x86_avx10_maskz_vminmaxps256(<8 x float> %A, <8 x float> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_avx10_maskz_vminmaxps256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_avx10_maskz_vminmaxps256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 %C, i32 4)
+ ret <8 x float> %ret
+}
+
+define <8 x float >@test_int_x86_vminmaxps256(<8 x float> %A, <8 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxps256:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxps256:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf3,0x7d,0x28,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> undef, i8 -1, i32 4)
+ ret <8 x float> %ret
+}
+
+define <8 x float> @test_int_x86_mask_vminmaxps256(<8 x float> %C, <8 x float> %A, <8 x float> %B, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxps256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x75,0x29,0x52,0xc2,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxps256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %ymm2, %ymm1, %ymm0 {%k1} # encoding: [0x62,0xf3,0x75,0x29,0x52,0xc2,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> %C, i8 %D, i32 4)
+ ret <8 x float> %ret
+}
+
+define <8 x float> @test_int_x86_maskz_vminmaxps256(<8 x float> %A, <8 x float> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxps256:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x52,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxps256:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxps $127, %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x52,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x float> @llvm.x86.avx10.mask.vminmaxps256.round(<8 x float> %A, <8 x float> %B, i32 127, <8 x float> zeroinitializer, i8 %C, i32 4)
+ ret <8 x float> %ret
+}
+
+define <2 x double>@test_int_x86_vminmaxsd(<2 x double> %A, <2 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxsd:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxsd:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> undef, i8 -1, i32 4)
+ ret <2 x double> %ret
+}
+
+define <2 x double>@test_int_x86_mask_vminmaxsd(<2 x double> %A, <2 x double> %B, <2 x double> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxsd:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x53,0xd1,0x7f]
+; X64-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxsd:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x53,0xd1,0x7f]
+; X86-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> %C, i8 %D, i32 4)
+ ret <2 x double> %ret
+}
+
+define <2 x double>@test_int_x86_maskz_vminmaxsd(<2 x double> %A, <2 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxsd:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x89,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxsd:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsd $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x89,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> zeroinitializer, i8 %C, i32 4)
+ ret <2 x double> %ret
+}
+
+define <2 x double>@test_int_x86_vminmaxsd_round(<2 x double> %A, <2 x double> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxsd_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x18,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxsd_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x18,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> undef, i8 -1, i32 8)
+ ret <2 x double> %ret
+}
+
+define <2 x double>@test_int_x86_mask_vminmaxsd_round(<2 x double> %A, <2 x double> %B, <2 x double> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxsd_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x19,0x53,0xd1,0x7f]
+; X64-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxsd_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0xfd,0x19,0x53,0xd1,0x7f]
+; X86-NEXT: vmovapd %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> %C, i8 %D, i32 8)
+ ret <2 x double> %ret
+}
+
+define <2 x double>@test_int_x86_maskz_vminmaxsd_round(<2 x double> %A, <2 x double> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxsd_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x99,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxsd_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsd $127, {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0xfd,0x99,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 127, <2 x double> zeroinitializer, i8 %C, i32 8)
+ ret <2 x double> %ret
+}
+
+declare<2 x double> @llvm.x86.avx10.mask.vminmaxsd.round(<2 x double> %A, <2 x double> %B, i32 %C, <2 x double> %D, i8 %E, i32 %F)
+
+define <8 x half>@test_int_x86_vminmaxsh(<8 x half> %A, <8 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxsh:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x08,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxsh:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x08,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> undef, i8 -1, i32 4)
+ ret <8 x half> %ret
+}
+
+define <8 x half>@test_int_x86_mask_vminmaxsh(<8 x half> %A, <8 x half> %B, <8 x half> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxsh:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x09,0x53,0xd1,0x7f]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxsh:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x09,0x53,0xd1,0x7f]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> %C, i8 %D, i32 4)
+ ret <8 x half> %ret
+}
+
+define <8 x half>@test_int_x86_maskz_vminmaxsh(<8 x half> %A, <8 x half> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxsh:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x89,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxsh:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsh $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x89,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> zeroinitializer, i8 %C, i32 4)
+ ret <8 x half> %ret
+}
+
+define <8 x half>@test_int_x86_vminmaxsh_round(<8 x half> %A, <8 x half> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxsh_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x18,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxsh_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7c,0x18,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> undef, i8 -1, i32 8)
+ ret <8 x half> %ret
+}
+
+define <8 x half>@test_int_x86_mask_vminmaxsh_round(<8 x half> %A, <8 x half> %B, <8 x half> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxsh_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x19,0x53,0xd1,0x7f]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxsh_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7c,0x19,0x53,0xd1,0x7f]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> %C, i8 %D, i32 8)
+ ret <8 x half> %ret
+}
+
+define <8 x half>@test_int_x86_maskz_vminmaxsh_round(<8 x half> %A, <8 x half> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxsh_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x99,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxsh_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxsh $127, {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7c,0x99,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 127, <8 x half> zeroinitializer, i8 %C, i32 8)
+ ret <8 x half> %ret
+}
+
+declare<8 x half> @llvm.x86.avx10.mask.vminmaxsh.round(<8 x half> %A, <8 x half> %B, i32 %C, <8 x half> %D, i8 %E, i32 %F)
+
+define <4 x float>@test_int_x86_vminmaxss(<4 x float> %A, <4 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxss:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x08,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxss:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x08,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> undef, i8 -1, i32 4)
+ ret <4 x float> %ret
+}
+
+define <4 x float>@test_int_x86_mask_vminmaxss(<4 x float> %A, <4 x float> %B, <4 x float> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxss:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x53,0xd1,0x7f]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxss:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x53,0xd1,0x7f]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> %C, i8 %D, i32 4)
+ ret <4 x float> %ret
+}
+
+define <4 x float>@test_int_x86_maskz_vminmaxss(<4 x float> %A, <4 x float> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxss:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x89,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxss:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxss $127, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x89,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> zeroinitializer, i8 %C, i32 4)
+ ret <4 x float> %ret
+}
+
+define <4 x float>@test_int_x86_vminmaxss_round(<4 x float> %A, <4 x float> %B) nounwind {
+; X64-LABEL: test_int_x86_vminmaxss_round:
+; X64: # %bb.0:
+; X64-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x18,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_vminmaxss_round:
+; X86: # %bb.0:
+; X86-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf3,0x7d,0x18,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> undef, i8 -1, i32 8)
+ ret <4 x float> %ret
+}
+
+define <4 x float>@test_int_x86_mask_vminmaxss_round(<4 x float> %A, <4 x float> %B, <4 x float> %C, i8 %D) nounwind {
+; X64-LABEL: test_int_x86_mask_vminmaxss_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x19,0x53,0xd1,0x7f]
+; X64-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_mask_vminmaxss_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf3,0x7d,0x19,0x53,0xd1,0x7f]
+; X86-NEXT: vmovaps %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0xc2]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> %C, i8 %D, i32 8)
+ ret <4 x float> %ret
+}
+
+define <4 x float>@test_int_x86_maskz_vminmaxss_round(<4 x float> %A, <4 x float> %B, i8 %C) nounwind {
+; X64-LABEL: test_int_x86_maskz_vminmaxss_round:
+; X64: # %bb.0:
+; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
+; X64-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x99,0x53,0xc1,0x7f]
+; X64-NEXT: retq # encoding: [0xc3]
+;
+; X86-LABEL: test_int_x86_maskz_vminmaxss_round:
+; X86: # %bb.0:
+; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
+; X86-NEXT: vminmaxss $127, {sae}, %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x99,0x53,0xc1,0x7f]
+; X86-NEXT: retl # encoding: [0xc3]
+ %ret = call <4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 127, <4 x float> zeroinitializer, i8 %C, i32 8)
+ ret <4 x float> %ret
+}
+
+declare<4 x float> @llvm.x86.avx10.mask.vminmaxss.round(<4 x float> %A, <4 x float> %B, i32 %C, <4 x float> %D, i8 %E, i32 %F)
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt b/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt
new file mode 100644
index 0000000000000..532128c19768b
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/avx10.2minmax-32.txt
@@ -0,0 +1,579 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxnepbf16 xmm2, xmm3, xmm4, 123
+0x62,0xf3,0x67,0x08,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxnepbf16 xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0x67,0x0f,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 xmm2 {k7} {z}, xmm3, xmm4, 123
+0x62,0xf3,0x67,0x8f,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxnepbf16 zmm2, zmm3, zmm4, 123
+0x62,0xf3,0x67,0x48,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxnepbf16 zmm2 {k7}, zmm3, zmm4, 123
+0x62,0xf3,0x67,0x4f,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 zmm2 {k7} {z}, zmm3, zmm4, 123
+0x62,0xf3,0x67,0xcf,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxnepbf16 ymm2, ymm3, ymm4, 123
+0x62,0xf3,0x67,0x28,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxnepbf16 ymm2 {k7}, ymm3, ymm4, 123
+0x62,0xf3,0x67,0x2f,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 ymm2 {k7} {z}, ymm3, ymm4, 123
+0x62,0xf3,0x67,0xaf,0x52,0xd4,0x7b
+
+# ATT: vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+# INTEL: vminmaxnepbf16 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x67,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxnepbf16 ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x67,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, (%eax){1to16}, %ymm3, %ymm2
+# INTEL: vminmaxnepbf16 ymm2, ymm3, word ptr [eax]{1to16}, 123
+0x62,0xf3,0x67,0x38,0x52,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, -1024(,%ebp,2), %ymm3, %ymm2
+# INTEL: vminmaxnepbf16 ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+0x62,0xf3,0x67,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxnepbf16 $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+0x62,0xf3,0x67,0xaf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxnepbf16 $123, -256(%edx){1to16}, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 ymm2 {k7} {z}, ymm3, word ptr [edx - 256]{1to16}, 123
+0x62,0xf3,0x67,0xbf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxnepbf16 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x67,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxnepbf16 xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x67,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, (%eax){1to8}, %xmm3, %xmm2
+# INTEL: vminmaxnepbf16 xmm2, xmm3, word ptr [eax]{1to8}, 123
+0x62,0xf3,0x67,0x18,0x52,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxnepbf16 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0x62,0xf3,0x67,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxnepbf16 $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+0x62,0xf3,0x67,0x8f,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxnepbf16 $123, -256(%edx){1to8}, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 xmm2 {k7} {z}, xmm3, word ptr [edx - 256]{1to8}, 123
+0x62,0xf3,0x67,0x9f,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+# INTEL: vminmaxnepbf16 zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x67,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxnepbf16 zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x67,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, (%eax){1to32}, %zmm3, %zmm2
+# INTEL: vminmaxnepbf16 zmm2, zmm3, word ptr [eax]{1to32}, 123
+0x62,0xf3,0x67,0x58,0x52,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, -2048(,%ebp,2), %zmm3, %zmm2
+# INTEL: vminmaxnepbf16 zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+0x62,0xf3,0x67,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxnepbf16 $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+0x62,0xf3,0x67,0xcf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxnepbf16 $123, -256(%edx){1to32}, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxnepbf16 zmm2 {k7} {z}, zmm3, word ptr [edx - 256]{1to32}, 123
+0x62,0xf3,0x67,0xdf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxpd $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxpd xmm2, xmm3, xmm4, 123
+0x62,0xf3,0xe5,0x08,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxpd xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0xe5,0x0f,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxpd xmm2 {k7} {z}, xmm3, xmm4, 123
+0x62,0xf3,0xe5,0x8f,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxpd zmm2, zmm3, zmm4, 123
+0x62,0xf3,0xe5,0x48,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxpd zmm2, zmm3, zmm4, {sae}, 123
+0x62,0xf3,0xe5,0x18,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, %zmm4, %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxpd zmm2 {k7}, zmm3, zmm4, 123
+0x62,0xf3,0xe5,0x4f,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxpd zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+0x62,0xf3,0xe5,0x9f,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxpd ymm2, ymm3, ymm4, 123
+0x62,0xf3,0xe5,0x28,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxpd ymm2, ymm3, ymm4, {sae}, 123
+0x62,0xf3,0xe1,0x18,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, %ymm4, %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxpd ymm2 {k7}, ymm3, ymm4, 123
+0x62,0xf3,0xe5,0x2f,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxpd ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+0x62,0xf3,0xe1,0x9f,0x52,0xd4,0x7b
+
+# ATT: vminmaxpd $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+# INTEL: vminmaxpd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0xe5,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxpd $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxpd ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0xe5,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, (%eax){1to4}, %ymm3, %ymm2
+# INTEL: vminmaxpd ymm2, ymm3, qword ptr [eax]{1to4}, 123
+0x62,0xf3,0xe5,0x38,0x52,0x10,0x7b
+
+# ATT: vminmaxpd $123, -1024(,%ebp,2), %ymm3, %ymm2
+# INTEL: vminmaxpd ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+0x62,0xf3,0xe5,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxpd $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxpd ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+0x62,0xf3,0xe5,0xaf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxpd $123, -1024(%edx){1to4}, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxpd ymm2 {k7} {z}, ymm3, qword ptr [edx - 1024]{1to4}, 123
+0x62,0xf3,0xe5,0xbf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxpd $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxpd xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0xe5,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxpd $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxpd xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0xe5,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, (%eax){1to2}, %xmm3, %xmm2
+# INTEL: vminmaxpd xmm2, xmm3, qword ptr [eax]{1to2}, 123
+0x62,0xf3,0xe5,0x18,0x52,0x10,0x7b
+
+# ATT: vminmaxpd $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxpd xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0x62,0xf3,0xe5,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxpd $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxpd xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+0x62,0xf3,0xe5,0x8f,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxpd $123, -1024(%edx){1to2}, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxpd xmm2 {k7} {z}, xmm3, qword ptr [edx - 1024]{1to2}, 123
+0x62,0xf3,0xe5,0x9f,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxpd $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+# INTEL: vminmaxpd zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0xe5,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxpd $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxpd zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0xe5,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, (%eax){1to8}, %zmm3, %zmm2
+# INTEL: vminmaxpd zmm2, zmm3, qword ptr [eax]{1to8}, 123
+0x62,0xf3,0xe5,0x58,0x52,0x10,0x7b
+
+# ATT: vminmaxpd $123, -2048(,%ebp,2), %zmm3, %zmm2
+# INTEL: vminmaxpd zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+0x62,0xf3,0xe5,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxpd $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxpd zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+0x62,0xf3,0xe5,0xcf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxpd $123, -1024(%edx){1to8}, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxpd zmm2 {k7} {z}, zmm3, qword ptr [edx - 1024]{1to8}, 123
+0x62,0xf3,0xe5,0xdf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxph $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxph xmm2, xmm3, xmm4, 123
+0x62,0xf3,0x64,0x08,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxph xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0x64,0x0f,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxph xmm2 {k7} {z}, xmm3, xmm4, 123
+0x62,0xf3,0x64,0x8f,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxph zmm2, zmm3, zmm4, 123
+0x62,0xf3,0x64,0x48,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, {sae}, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxph zmm2, zmm3, zmm4, {sae}, 123
+0x62,0xf3,0x64,0x18,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, %zmm4, %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxph zmm2 {k7}, zmm3, zmm4, 123
+0x62,0xf3,0x64,0x4f,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxph zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+0x62,0xf3,0x64,0x9f,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxph ymm2, ymm3, ymm4, 123
+0x62,0xf3,0x64,0x28,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxph ymm2, ymm3, ymm4, {sae}, 123
+0x62,0xf3,0x60,0x18,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, %ymm4, %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxph ymm2 {k7}, ymm3, ymm4, 123
+0x62,0xf3,0x64,0x2f,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxph ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+0x62,0xf3,0x60,0x9f,0x52,0xd4,0x7b
+
+# ATT: vminmaxph $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+# INTEL: vminmaxph ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x64,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxph $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxph ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x64,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, (%eax){1to16}, %ymm3, %ymm2
+# INTEL: vminmaxph ymm2, ymm3, word ptr [eax]{1to16}, 123
+0x62,0xf3,0x64,0x38,0x52,0x10,0x7b
+
+# ATT: vminmaxph $123, -1024(,%ebp,2), %ymm3, %ymm2
+# INTEL: vminmaxph ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+0x62,0xf3,0x64,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxph $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxph ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+0x62,0xf3,0x64,0xaf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxph $123, -256(%edx){1to16}, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxph ymm2 {k7} {z}, ymm3, word ptr [edx - 256]{1to16}, 123
+0x62,0xf3,0x64,0xbf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxph $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxph xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x64,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxph $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxph xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x64,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, (%eax){1to8}, %xmm3, %xmm2
+# INTEL: vminmaxph xmm2, xmm3, word ptr [eax]{1to8}, 123
+0x62,0xf3,0x64,0x18,0x52,0x10,0x7b
+
+# ATT: vminmaxph $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxph xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0x62,0xf3,0x64,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxph $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxph xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+0x62,0xf3,0x64,0x8f,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxph $123, -256(%edx){1to8}, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxph xmm2 {k7} {z}, xmm3, word ptr [edx - 256]{1to8}, 123
+0x62,0xf3,0x64,0x9f,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxph $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+# INTEL: vminmaxph zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x64,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxph $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxph zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x64,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, (%eax){1to32}, %zmm3, %zmm2
+# INTEL: vminmaxph zmm2, zmm3, word ptr [eax]{1to32}, 123
+0x62,0xf3,0x64,0x58,0x52,0x10,0x7b
+
+# ATT: vminmaxph $123, -2048(,%ebp,2), %zmm3, %zmm2
+# INTEL: vminmaxph zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+0x62,0xf3,0x64,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxph $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxph zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+0x62,0xf3,0x64,0xcf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxph $123, -256(%edx){1to32}, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxph zmm2 {k7} {z}, zmm3, word ptr [edx - 256]{1to32}, 123
+0x62,0xf3,0x64,0xdf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxps $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxps xmm2, xmm3, xmm4, 123
+0x62,0xf3,0x65,0x08,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxps xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0x65,0x0f,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxps xmm2 {k7} {z}, xmm3, xmm4, 123
+0x62,0xf3,0x65,0x8f,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxps zmm2, zmm3, zmm4, 123
+0x62,0xf3,0x65,0x48,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, {sae}, %zmm4, %zmm3, %zmm2
+# INTEL: vminmaxps zmm2, zmm3, zmm4, {sae}, 123
+0x62,0xf3,0x65,0x18,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, %zmm4, %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxps zmm2 {k7}, zmm3, zmm4, 123
+0x62,0xf3,0x65,0x4f,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxps zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+0x62,0xf3,0x65,0x9f,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxps ymm2, ymm3, ymm4, 123
+0x62,0xf3,0x65,0x28,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2
+# INTEL: vminmaxps ymm2, ymm3, ymm4, {sae}, 123
+0x62,0xf3,0x61,0x18,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, %ymm4, %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxps ymm2 {k7}, ymm3, ymm4, 123
+0x62,0xf3,0x65,0x2f,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxps ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+0x62,0xf3,0x61,0x9f,0x52,0xd4,0x7b
+
+# ATT: vminmaxps $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+# INTEL: vminmaxps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x65,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxps $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+# INTEL: vminmaxps ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x65,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, (%eax){1to8}, %ymm3, %ymm2
+# INTEL: vminmaxps ymm2, ymm3, dword ptr [eax]{1to8}, 123
+0x62,0xf3,0x65,0x38,0x52,0x10,0x7b
+
+# ATT: vminmaxps $123, -1024(,%ebp,2), %ymm3, %ymm2
+# INTEL: vminmaxps ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+0x62,0xf3,0x65,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxps $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxps ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+0x62,0xf3,0x65,0xaf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxps $123, -512(%edx){1to8}, %ymm3, %ymm2 {%k7} {z}
+# INTEL: vminmaxps ymm2 {k7} {z}, ymm3, dword ptr [edx - 512]{1to8}, 123
+0x62,0xf3,0x65,0xbf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxps $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxps xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x65,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxps $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxps xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x65,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, (%eax){1to4}, %xmm3, %xmm2
+# INTEL: vminmaxps xmm2, xmm3, dword ptr [eax]{1to4}, 123
+0x62,0xf3,0x65,0x18,0x52,0x10,0x7b
+
+# ATT: vminmaxps $123, -512(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxps xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+0x62,0xf3,0x65,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxps $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxps xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+0x62,0xf3,0x65,0x8f,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxps $123, -512(%edx){1to4}, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxps xmm2 {k7} {z}, xmm3, dword ptr [edx - 512]{1to4}, 123
+0x62,0xf3,0x65,0x9f,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxps $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+# INTEL: vminmaxps zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x65,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxps $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+# INTEL: vminmaxps zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x65,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, (%eax){1to16}, %zmm3, %zmm2
+# INTEL: vminmaxps zmm2, zmm3, dword ptr [eax]{1to16}, 123
+0x62,0xf3,0x65,0x58,0x52,0x10,0x7b
+
+# ATT: vminmaxps $123, -2048(,%ebp,2), %zmm3, %zmm2
+# INTEL: vminmaxps zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+0x62,0xf3,0x65,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxps $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxps zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+0x62,0xf3,0x65,0xcf,0x52,0x51,0x7f,0x7b
+
+# ATT: vminmaxps $123, -512(%edx){1to16}, %zmm3, %zmm2 {%k7} {z}
+# INTEL: vminmaxps zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16}, 123
+0x62,0xf3,0x65,0xdf,0x52,0x52,0x80,0x7b
+
+# ATT: vminmaxsd $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxsd xmm2, xmm3, xmm4, 123
+0x62,0xf3,0xe5,0x08,0x53,0xd4,0x7b
+
+# ATT: vminmaxsd $123, {sae}, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxsd xmm2, xmm3, xmm4, {sae}, 123
+0x62,0xf3,0xe5,0x18,0x53,0xd4,0x7b
+
+# ATT: vminmaxsd $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxsd xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0xe5,0x0f,0x53,0xd4,0x7b
+
+# ATT: vminmaxsd $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxsd xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+0x62,0xf3,0xe5,0x9f,0x53,0xd4,0x7b
+
+# ATT: vminmaxsd $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxsd xmm2, xmm3, qword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0xe5,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxsd $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxsd xmm2 {k7}, xmm3, qword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0xe5,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxsd $123, (%eax), %xmm3, %xmm2
+# INTEL: vminmaxsd xmm2, xmm3, qword ptr [eax], 123
+0x62,0xf3,0xe5,0x08,0x53,0x10,0x7b
+
+# ATT: vminmaxsd $123, -256(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxsd xmm2, xmm3, qword ptr [2*ebp - 256], 123
+0x62,0xf3,0xe5,0x08,0x53,0x14,0x6d,0x00,0xff,0xff,0xff,0x7b
+
+# ATT: vminmaxsd $123, 1016(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxsd xmm2 {k7} {z}, xmm3, qword ptr [ecx + 1016], 123
+0x62,0xf3,0xe5,0x8f,0x53,0x51,0x7f,0x7b
+
+# ATT: vminmaxsd $123, -1024(%edx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxsd xmm2 {k7} {z}, xmm3, qword ptr [edx - 1024], 123
+0x62,0xf3,0xe5,0x8f,0x53,0x52,0x80,0x7b
+
+# ATT: vminmaxsh $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxsh xmm2, xmm3, xmm4, 123
+0x62,0xf3,0x64,0x08,0x53,0xd4,0x7b
+
+# ATT: vminmaxsh $123, {sae}, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxsh xmm2, xmm3, xmm4, {sae}, 123
+0x62,0xf3,0x64,0x18,0x53,0xd4,0x7b
+
+# ATT: vminmaxsh $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxsh xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0x64,0x0f,0x53,0xd4,0x7b
+
+# ATT: vminmaxsh $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxsh xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+0x62,0xf3,0x64,0x9f,0x53,0xd4,0x7b
+
+# ATT: vminmaxsh $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxsh xmm2, xmm3, word ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x64,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxsh $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxsh xmm2 {k7}, xmm3, word ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x64,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxsh $123, (%eax), %xmm3, %xmm2
+# INTEL: vminmaxsh xmm2, xmm3, word ptr [eax], 123
+0x62,0xf3,0x64,0x08,0x53,0x10,0x7b
+
+# ATT: vminmaxsh $123, -64(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxsh xmm2, xmm3, word ptr [2*ebp - 64], 123
+0x62,0xf3,0x64,0x08,0x53,0x14,0x6d,0xc0,0xff,0xff,0xff,0x7b
+
+# ATT: vminmaxsh $123, 254(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxsh xmm2 {k7} {z}, xmm3, word ptr [ecx + 254], 123
+0x62,0xf3,0x64,0x8f,0x53,0x51,0x7f,0x7b
+
+# ATT: vminmaxsh $123, -256(%edx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxsh xmm2 {k7} {z}, xmm3, word ptr [edx - 256], 123
+0x62,0xf3,0x64,0x8f,0x53,0x52,0x80,0x7b
+
+# ATT: vminmaxss $123, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxss xmm2, xmm3, xmm4, 123
+0x62,0xf3,0x65,0x08,0x53,0xd4,0x7b
+
+# ATT: vminmaxss $123, {sae}, %xmm4, %xmm3, %xmm2
+# INTEL: vminmaxss xmm2, xmm3, xmm4, {sae}, 123
+0x62,0xf3,0x65,0x18,0x53,0xd4,0x7b
+
+# ATT: vminmaxss $123, %xmm4, %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxss xmm2 {k7}, xmm3, xmm4, 123
+0x62,0xf3,0x65,0x0f,0x53,0xd4,0x7b
+
+# ATT: vminmaxss $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxss xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+0x62,0xf3,0x65,0x9f,0x53,0xd4,0x7b
+
+# ATT: vminmaxss $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL: vminmaxss xmm2, xmm3, dword ptr [esp + 8*esi + 268435456], 123
+0x62,0xf3,0x65,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxss $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+# INTEL: vminmaxss xmm2 {k7}, xmm3, dword ptr [edi + 4*eax + 291], 123
+0x62,0xf3,0x65,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxss $123, (%eax), %xmm3, %xmm2
+# INTEL: vminmaxss xmm2, xmm3, dword ptr [eax], 123
+0x62,0xf3,0x65,0x08,0x53,0x10,0x7b
+
+# ATT: vminmaxss $123, -128(,%ebp,2), %xmm3, %xmm2
+# INTEL: vminmaxss xmm2, xmm3, dword ptr [2*ebp - 128], 123
+0x62,0xf3,0x65,0x08,0x53,0x14,0x6d,0x80,0xff,0xff,0xff,0x7b
+
+# ATT: vminmaxss $123, 508(%ecx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxss xmm2 {k7} {z}, xmm3, dword ptr [ecx + 508], 123
+0x62,0xf3,0x65,0x8f,0x53,0x51,0x7f,0x7b
+
+# ATT: vminmaxss $123, -512(%edx), %xmm3, %xmm2 {%k7} {z}
+# INTEL: vminmaxss xmm2 {k7} {z}, xmm3, dword ptr [edx - 512], 123
+0x62,0xf3,0x65,0x8f,0x53,0x52,0x80,0x7b
+
diff --git a/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt b/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt
new file mode 100644
index 0000000000000..fdb2f6877806e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/avx10.2minmax-64.txt
@@ -0,0 +1,579 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxnepbf16 xmm22, xmm23, xmm24, 123
+0x62,0x83,0x47,0x00,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxnepbf16 xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0x47,0x07,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 xmm22 {k7} {z}, xmm23, xmm24, 123
+0x62,0x83,0x47,0x87,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxnepbf16 zmm22, zmm23, zmm24, 123
+0x62,0x83,0x47,0x40,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxnepbf16 zmm22 {k7}, zmm23, zmm24, 123
+0x62,0x83,0x47,0x47,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 zmm22 {k7} {z}, zmm23, zmm24, 123
+0x62,0x83,0x47,0xc7,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxnepbf16 ymm22, ymm23, ymm24, 123
+0x62,0x83,0x47,0x20,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxnepbf16 ymm22 {k7}, ymm23, ymm24, 123
+0x62,0x83,0x47,0x27,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 ymm22 {k7} {z}, ymm23, ymm24, 123
+0x62,0x83,0x47,0xa7,0x52,0xf0,0x7b
+
+# ATT: vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+# INTEL: vminmaxnepbf16 ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x47,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxnepbf16 ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x47,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, (%rip){1to16}, %ymm23, %ymm22
+# INTEL: vminmaxnepbf16 ymm22, ymm23, word ptr [rip]{1to16}, 123
+0x62,0xe3,0x47,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, -1024(,%rbp,2), %ymm23, %ymm22
+# INTEL: vminmaxnepbf16 ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+0x62,0xe3,0x47,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxnepbf16 $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+0x62,0xe3,0x47,0xa7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxnepbf16 $123, -256(%rdx){1to16}, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 ymm22 {k7} {z}, ymm23, word ptr [rdx - 256]{1to16}, 123
+0x62,0xe3,0x47,0xb7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxnepbf16 xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x47,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxnepbf16 xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x47,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, (%rip){1to8}, %xmm23, %xmm22
+# INTEL: vminmaxnepbf16 xmm22, xmm23, word ptr [rip]{1to8}, 123
+0x62,0xe3,0x47,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, -512(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxnepbf16 xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+0x62,0xe3,0x47,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxnepbf16 $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+0x62,0xe3,0x47,0x87,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxnepbf16 $123, -256(%rdx){1to8}, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 xmm22 {k7} {z}, xmm23, word ptr [rdx - 256]{1to8}, 123
+0x62,0xe3,0x47,0x97,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+# INTEL: vminmaxnepbf16 zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x47,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxnepbf16 $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxnepbf16 zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x47,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, (%rip){1to32}, %zmm23, %zmm22
+# INTEL: vminmaxnepbf16 zmm22, zmm23, word ptr [rip]{1to32}, 123
+0x62,0xe3,0x47,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxnepbf16 $123, -2048(,%rbp,2), %zmm23, %zmm22
+# INTEL: vminmaxnepbf16 zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+0x62,0xe3,0x47,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxnepbf16 $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+0x62,0xe3,0x47,0xc7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxnepbf16 $123, -256(%rdx){1to32}, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxnepbf16 zmm22 {k7} {z}, zmm23, word ptr [rdx - 256]{1to32}, 123
+0x62,0xe3,0x47,0xd7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxpd $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxpd xmm22, xmm23, xmm24, 123
+0x62,0x83,0xc5,0x00,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxpd xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0xc5,0x07,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxpd xmm22 {k7} {z}, xmm23, xmm24, 123
+0x62,0x83,0xc5,0x87,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxpd zmm22, zmm23, zmm24, 123
+0x62,0x83,0xc5,0x40,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxpd zmm22, zmm23, zmm24, {sae}, 123
+0x62,0x83,0xc5,0x10,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, %zmm24, %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxpd zmm22 {k7}, zmm23, zmm24, 123
+0x62,0x83,0xc5,0x47,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxpd zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+0x62,0x83,0xc5,0x97,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxpd ymm22, ymm23, ymm24, 123
+0x62,0x83,0xc5,0x20,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxpd ymm22, ymm23, ymm24, {sae}, 123
+0x62,0x83,0xc1,0x10,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, %ymm24, %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxpd ymm22 {k7}, ymm23, ymm24, 123
+0x62,0x83,0xc5,0x27,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+0x62,0x83,0xc1,0x97,0x52,0xf0,0x7b
+
+# ATT: vminmaxpd $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+# INTEL: vminmaxpd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0xc5,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxpd $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxpd ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0xc5,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, (%rip){1to4}, %ymm23, %ymm22
+# INTEL: vminmaxpd ymm22, ymm23, qword ptr [rip]{1to4}, 123
+0x62,0xe3,0xc5,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, -1024(,%rbp,2), %ymm23, %ymm22
+# INTEL: vminmaxpd ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+0x62,0xe3,0xc5,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxpd $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxpd ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+0x62,0xe3,0xc5,0xa7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxpd $123, -1024(%rdx){1to4}, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxpd ymm22 {k7} {z}, ymm23, qword ptr [rdx - 1024]{1to4}, 123
+0x62,0xe3,0xc5,0xb7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxpd $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxpd xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0xc5,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxpd $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxpd xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0xc5,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, (%rip){1to2}, %xmm23, %xmm22
+# INTEL: vminmaxpd xmm22, xmm23, qword ptr [rip]{1to2}, 123
+0x62,0xe3,0xc5,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, -512(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxpd xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+0x62,0xe3,0xc5,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxpd $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxpd xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+0x62,0xe3,0xc5,0x87,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxpd $123, -1024(%rdx){1to2}, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxpd xmm22 {k7} {z}, xmm23, qword ptr [rdx - 1024]{1to2}, 123
+0x62,0xe3,0xc5,0x97,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxpd $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+# INTEL: vminmaxpd zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0xc5,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxpd $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxpd zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0xc5,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, (%rip){1to8}, %zmm23, %zmm22
+# INTEL: vminmaxpd zmm22, zmm23, qword ptr [rip]{1to8}, 123
+0x62,0xe3,0xc5,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxpd $123, -2048(,%rbp,2), %zmm23, %zmm22
+# INTEL: vminmaxpd zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+0x62,0xe3,0xc5,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxpd $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxpd zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+0x62,0xe3,0xc5,0xc7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxpd $123, -1024(%rdx){1to8}, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxpd zmm22 {k7} {z}, zmm23, qword ptr [rdx - 1024]{1to8}, 123
+0x62,0xe3,0xc5,0xd7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxph $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxph xmm22, xmm23, xmm24, 123
+0x62,0x83,0x44,0x00,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxph xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0x44,0x07,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxph xmm22 {k7} {z}, xmm23, xmm24, 123
+0x62,0x83,0x44,0x87,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxph zmm22, zmm23, zmm24, 123
+0x62,0x83,0x44,0x40,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, {sae}, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxph zmm22, zmm23, zmm24, {sae}, 123
+0x62,0x83,0x44,0x10,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, %zmm24, %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxph zmm22 {k7}, zmm23, zmm24, 123
+0x62,0x83,0x44,0x47,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxph zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+0x62,0x83,0x44,0x97,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxph ymm22, ymm23, ymm24, 123
+0x62,0x83,0x44,0x20,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxph ymm22, ymm23, ymm24, {sae}, 123
+0x62,0x83,0x40,0x10,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, %ymm24, %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxph ymm22 {k7}, ymm23, ymm24, 123
+0x62,0x83,0x44,0x27,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+0x62,0x83,0x40,0x97,0x52,0xf0,0x7b
+
+# ATT: vminmaxph $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+# INTEL: vminmaxph ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxph $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxph ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x44,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, (%rip){1to16}, %ymm23, %ymm22
+# INTEL: vminmaxph ymm22, ymm23, word ptr [rip]{1to16}, 123
+0x62,0xe3,0x44,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, -1024(,%rbp,2), %ymm23, %ymm22
+# INTEL: vminmaxph ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+0x62,0xe3,0x44,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxph $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxph ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+0x62,0xe3,0x44,0xa7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxph $123, -256(%rdx){1to16}, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxph ymm22 {k7} {z}, ymm23, word ptr [rdx - 256]{1to16}, 123
+0x62,0xe3,0x44,0xb7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxph $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxph xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x44,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxph $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxph xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x44,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, (%rip){1to8}, %xmm23, %xmm22
+# INTEL: vminmaxph xmm22, xmm23, word ptr [rip]{1to8}, 123
+0x62,0xe3,0x44,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, -512(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxph xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+0x62,0xe3,0x44,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxph $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxph xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+0x62,0xe3,0x44,0x87,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxph $123, -256(%rdx){1to8}, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxph xmm22 {k7} {z}, xmm23, word ptr [rdx - 256]{1to8}, 123
+0x62,0xe3,0x44,0x97,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxph $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+# INTEL: vminmaxph zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x44,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxph $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxph zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x44,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, (%rip){1to32}, %zmm23, %zmm22
+# INTEL: vminmaxph zmm22, zmm23, word ptr [rip]{1to32}, 123
+0x62,0xe3,0x44,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxph $123, -2048(,%rbp,2), %zmm23, %zmm22
+# INTEL: vminmaxph zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+0x62,0xe3,0x44,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxph $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxph zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+0x62,0xe3,0x44,0xc7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxph $123, -256(%rdx){1to32}, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxph zmm22 {k7} {z}, zmm23, word ptr [rdx - 256]{1to32}, 123
+0x62,0xe3,0x44,0xd7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxps $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxps xmm22, xmm23, xmm24, 123
+0x62,0x83,0x45,0x00,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxps xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0x45,0x07,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxps xmm22 {k7} {z}, xmm23, xmm24, 123
+0x62,0x83,0x45,0x87,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxps zmm22, zmm23, zmm24, 123
+0x62,0x83,0x45,0x40,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, {sae}, %zmm24, %zmm23, %zmm22
+# INTEL: vminmaxps zmm22, zmm23, zmm24, {sae}, 123
+0x62,0x83,0x45,0x10,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, %zmm24, %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxps zmm22 {k7}, zmm23, zmm24, 123
+0x62,0x83,0x45,0x47,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxps zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+0x62,0x83,0x45,0x97,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxps ymm22, ymm23, ymm24, 123
+0x62,0x83,0x45,0x20,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22
+# INTEL: vminmaxps ymm22, ymm23, ymm24, {sae}, 123
+0x62,0x83,0x41,0x10,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, %ymm24, %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxps ymm22 {k7}, ymm23, ymm24, 123
+0x62,0x83,0x45,0x27,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+0x62,0x83,0x41,0x97,0x52,0xf0,0x7b
+
+# ATT: vminmaxps $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+# INTEL: vminmaxps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x45,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxps $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+# INTEL: vminmaxps ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x45,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, (%rip){1to8}, %ymm23, %ymm22
+# INTEL: vminmaxps ymm22, ymm23, dword ptr [rip]{1to8}, 123
+0x62,0xe3,0x45,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, -1024(,%rbp,2), %ymm23, %ymm22
+# INTEL: vminmaxps ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+0x62,0xe3,0x45,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b
+
+# ATT: vminmaxps $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxps ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+0x62,0xe3,0x45,0xa7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxps $123, -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
+# INTEL: vminmaxps ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}, 123
+0x62,0xe3,0x45,0xb7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxps $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxps xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x45,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxps $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxps xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x45,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, (%rip){1to4}, %xmm23, %xmm22
+# INTEL: vminmaxps xmm22, xmm23, dword ptr [rip]{1to4}, 123
+0x62,0xe3,0x45,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, -512(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxps xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+0x62,0xe3,0x45,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b
+
+# ATT: vminmaxps $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxps xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+0x62,0xe3,0x45,0x87,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxps $123, -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxps xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}, 123
+0x62,0xe3,0x45,0x97,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxps $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+# INTEL: vminmaxps zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x45,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxps $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+# INTEL: vminmaxps zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x45,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, (%rip){1to16}, %zmm23, %zmm22
+# INTEL: vminmaxps zmm22, zmm23, dword ptr [rip]{1to16}, 123
+0x62,0xe3,0x45,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxps $123, -2048(,%rbp,2), %zmm23, %zmm22
+# INTEL: vminmaxps zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+0x62,0xe3,0x45,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b
+
+# ATT: vminmaxps $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxps zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+0x62,0xe3,0x45,0xc7,0x52,0x71,0x7f,0x7b
+
+# ATT: vminmaxps $123, -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
+# INTEL: vminmaxps zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}, 123
+0x62,0xe3,0x45,0xd7,0x52,0x72,0x80,0x7b
+
+# ATT: vminmaxsd $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxsd xmm22, xmm23, xmm24, 123
+0x62,0x83,0xc5,0x00,0x53,0xf0,0x7b
+
+# ATT: vminmaxsd $123, {sae}, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxsd xmm22, xmm23, xmm24, {sae}, 123
+0x62,0x83,0xc5,0x10,0x53,0xf0,0x7b
+
+# ATT: vminmaxsd $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxsd xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0xc5,0x07,0x53,0xf0,0x7b
+
+# ATT: vminmaxsd $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxsd xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+0x62,0x83,0xc5,0x97,0x53,0xf0,0x7b
+
+# ATT: vminmaxsd $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxsd xmm22, xmm23, qword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0xc5,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxsd $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxsd xmm22 {k7}, xmm23, qword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0xc5,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxsd $123, (%rip), %xmm23, %xmm22
+# INTEL: vminmaxsd xmm22, xmm23, qword ptr [rip], 123
+0x62,0xe3,0xc5,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxsd $123, -256(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxsd xmm22, xmm23, qword ptr [2*rbp - 256], 123
+0x62,0xe3,0xc5,0x00,0x53,0x34,0x6d,0x00,0xff,0xff,0xff,0x7b
+
+# ATT: vminmaxsd $123, 1016(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxsd xmm22 {k7} {z}, xmm23, qword ptr [rcx + 1016], 123
+0x62,0xe3,0xc5,0x87,0x53,0x71,0x7f,0x7b
+
+# ATT: vminmaxsd $123, -1024(%rdx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxsd xmm22 {k7} {z}, xmm23, qword ptr [rdx - 1024], 123
+0x62,0xe3,0xc5,0x87,0x53,0x72,0x80,0x7b
+
+# ATT: vminmaxsh $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxsh xmm22, xmm23, xmm24, 123
+0x62,0x83,0x44,0x00,0x53,0xf0,0x7b
+
+# ATT: vminmaxsh $123, {sae}, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxsh xmm22, xmm23, xmm24, {sae}, 123
+0x62,0x83,0x44,0x10,0x53,0xf0,0x7b
+
+# ATT: vminmaxsh $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxsh xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0x44,0x07,0x53,0xf0,0x7b
+
+# ATT: vminmaxsh $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxsh xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+0x62,0x83,0x44,0x97,0x53,0xf0,0x7b
+
+# ATT: vminmaxsh $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxsh xmm22, xmm23, word ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x44,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxsh $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxsh xmm22 {k7}, xmm23, word ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x44,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxsh $123, (%rip), %xmm23, %xmm22
+# INTEL: vminmaxsh xmm22, xmm23, word ptr [rip], 123
+0x62,0xe3,0x44,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxsh $123, -64(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxsh xmm22, xmm23, word ptr [2*rbp - 64], 123
+0x62,0xe3,0x44,0x00,0x53,0x34,0x6d,0xc0,0xff,0xff,0xff,0x7b
+
+# ATT: vminmaxsh $123, 254(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxsh xmm22 {k7} {z}, xmm23, word ptr [rcx + 254], 123
+0x62,0xe3,0x44,0x87,0x53,0x71,0x7f,0x7b
+
+# ATT: vminmaxsh $123, -256(%rdx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxsh xmm22 {k7} {z}, xmm23, word ptr [rdx - 256], 123
+0x62,0xe3,0x44,0x87,0x53,0x72,0x80,0x7b
+
+# ATT: vminmaxss $123, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxss xmm22, xmm23, xmm24, 123
+0x62,0x83,0x45,0x00,0x53,0xf0,0x7b
+
+# ATT: vminmaxss $123, {sae}, %xmm24, %xmm23, %xmm22
+# INTEL: vminmaxss xmm22, xmm23, xmm24, {sae}, 123
+0x62,0x83,0x45,0x10,0x53,0xf0,0x7b
+
+# ATT: vminmaxss $123, %xmm24, %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxss xmm22 {k7}, xmm23, xmm24, 123
+0x62,0x83,0x45,0x07,0x53,0xf0,0x7b
+
+# ATT: vminmaxss $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxss xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+0x62,0x83,0x45,0x97,0x53,0xf0,0x7b
+
+# ATT: vminmaxss $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+# INTEL: vminmaxss xmm22, xmm23, dword ptr [rbp + 8*r14 + 268435456], 123
+0x62,0xa3,0x45,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b
+
+# ATT: vminmaxss $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+# INTEL: vminmaxss xmm22 {k7}, xmm23, dword ptr [r8 + 4*rax + 291], 123
+0x62,0xc3,0x45,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b
+
+# ATT: vminmaxss $123, (%rip), %xmm23, %xmm22
+# INTEL: vminmaxss xmm22, xmm23, dword ptr [rip], 123
+0x62,0xe3,0x45,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b
+
+# ATT: vminmaxss $123, -128(,%rbp,2), %xmm23, %xmm22
+# INTEL: vminmaxss xmm22, xmm23, dword ptr [2*rbp - 128], 123
+0x62,0xe3,0x45,0x00,0x53,0x34,0x6d,0x80,0xff,0xff,0xff,0x7b
+
+# ATT: vminmaxss $123, 508(%rcx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxss xmm22 {k7} {z}, xmm23, dword ptr [rcx + 508], 123
+0x62,0xe3,0x45,0x87,0x53,0x71,0x7f,0x7b
+
+# ATT: vminmaxss $123, -512(%rdx), %xmm23, %xmm22 {%k7} {z}
+# INTEL: vminmaxss xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512], 123
+0x62,0xe3,0x45,0x87,0x53,0x72,0x80,0x7b
+
diff --git a/llvm/test/MC/X86/avx10.2minmax-32-att.s b/llvm/test/MC/X86/avx10.2minmax-32-att.s
new file mode 100644
index 0000000000000..f6900899af28e
--- /dev/null
+++ b/llvm/test/MC/X86/avx10.2minmax-32-att.s
@@ -0,0 +1,578 @@
+// RUN: llvm-mc -triple i386 --show-encoding %s | FileCheck %s
+
+// CHECK: vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x08,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x67,0x0f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0x8f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x48,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x67,0x4f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0xcf,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %zmm4, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x28,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x67,0x2f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0xaf,0x52,0xd4,0x7b]
+ vminmaxnepbf16 $123, %ymm4, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+
+// CHECK: vminmaxnepbf16 $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x67,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, (%eax){1to16}, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x38,0x52,0x10,0x7b]
+ vminmaxnepbf16 $123, (%eax){1to16}, %ymm3, %ymm2
+
+// CHECK: vminmaxnepbf16 $123, -1024(,%ebp,2), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxnepbf16 $123, -1024(,%ebp,2), %ymm3, %ymm2
+
+// CHECK: vminmaxnepbf16 $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxnepbf16 $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, -256(%edx){1to16}, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxnepbf16 $123, -256(%edx){1to16}, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxnepbf16 $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x67,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, (%eax){1to8}, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x18,0x52,0x10,0x7b]
+ vminmaxnepbf16 $123, (%eax){1to8}, %xmm3, %xmm2
+
+// CHECK: vminmaxnepbf16 $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxnepbf16 $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxnepbf16 $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxnepbf16 $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, -256(%edx){1to8}, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxnepbf16 $123, -256(%edx){1to8}, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+
+// CHECK: vminmaxnepbf16 $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x67,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, (%eax){1to32}, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x58,0x52,0x10,0x7b]
+ vminmaxnepbf16 $123, (%eax){1to32}, %zmm3, %zmm2
+
+// CHECK: vminmaxnepbf16 $123, -2048(,%ebp,2), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x67,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxnepbf16 $123, -2048(,%ebp,2), %zmm3, %zmm2
+
+// CHECK: vminmaxnepbf16 $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxnepbf16 $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, -256(%edx){1to32}, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x67,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxnepbf16 $123, -256(%edx){1to32}, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x52,0xd4,0x7b]
+ vminmaxpd $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxpd $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x52,0xd4,0x7b]
+ vminmaxpd $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxpd $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x52,0xd4,0x7b]
+ vminmaxpd $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x48,0x52,0xd4,0x7b]
+ vminmaxpd $123, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxpd $123, {sae}, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x18,0x52,0xd4,0x7b]
+ vminmaxpd $123, {sae}, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxpd $123, %zmm4, %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x4f,0x52,0xd4,0x7b]
+ vminmaxpd $123, %zmm4, %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxpd $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x9f,0x52,0xd4,0x7b]
+ vminmaxpd $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0xd4,0x7b]
+ vminmaxpd $123, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0xe1,0x18,0x52,0xd4,0x7b]
+ vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxpd $123, %ymm4, %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x2f,0x52,0xd4,0x7b]
+ vminmaxpd $123, %ymm4, %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe1,0x9f,0x52,0xd4,0x7b]
+ vminmaxpd $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+
+// CHECK: vminmaxpd $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxpd $123, (%eax){1to4}, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x38,0x52,0x10,0x7b]
+ vminmaxpd $123, (%eax){1to4}, %ymm3, %ymm2
+
+// CHECK: vminmaxpd $123, -1024(,%ebp,2), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxpd $123, -1024(,%ebp,2), %ymm3, %ymm2
+
+// CHECK: vminmaxpd $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxpd $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, -1024(%edx){1to4}, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxpd $123, -1024(%edx){1to4}, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxpd $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxpd $123, (%eax){1to2}, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x18,0x52,0x10,0x7b]
+ vminmaxpd $123, (%eax){1to2}, %xmm3, %xmm2
+
+// CHECK: vminmaxpd $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxpd $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxpd $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxpd $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, -1024(%edx){1to2}, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxpd $123, -1024(%edx){1to2}, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+
+// CHECK: vminmaxpd $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxpd $123, (%eax){1to8}, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x58,0x52,0x10,0x7b]
+ vminmaxpd $123, (%eax){1to8}, %zmm3, %zmm2
+
+// CHECK: vminmaxpd $123, -2048(,%ebp,2), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxpd $123, -2048(,%ebp,2), %zmm3, %zmm2
+
+// CHECK: vminmaxpd $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxpd $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxpd $123, -1024(%edx){1to8}, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxpd $123, -1024(%edx){1to8}, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x52,0xd4,0x7b]
+ vminmaxph $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxph $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x52,0xd4,0x7b]
+ vminmaxph $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxph $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x52,0xd4,0x7b]
+ vminmaxph $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x48,0x52,0xd4,0x7b]
+ vminmaxph $123, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxph $123, {sae}, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x18,0x52,0xd4,0x7b]
+ vminmaxph $123, {sae}, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxph $123, %zmm4, %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x4f,0x52,0xd4,0x7b]
+ vminmaxph $123, %zmm4, %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxph $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x9f,0x52,0xd4,0x7b]
+ vminmaxph $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0xd4,0x7b]
+ vminmaxph $123, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x60,0x18,0x52,0xd4,0x7b]
+ vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxph $123, %ymm4, %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x2f,0x52,0xd4,0x7b]
+ vminmaxph $123, %ymm4, %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x60,0x9f,0x52,0xd4,0x7b]
+ vminmaxph $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+
+// CHECK: vminmaxph $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxph $123, (%eax){1to16}, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x38,0x52,0x10,0x7b]
+ vminmaxph $123, (%eax){1to16}, %ymm3, %ymm2
+
+// CHECK: vminmaxph $123, -1024(,%ebp,2), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxph $123, -1024(,%ebp,2), %ymm3, %ymm2
+
+// CHECK: vminmaxph $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxph $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, -256(%edx){1to16}, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxph $123, -256(%edx){1to16}, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxph $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxph $123, (%eax){1to8}, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x18,0x52,0x10,0x7b]
+ vminmaxph $123, (%eax){1to8}, %xmm3, %xmm2
+
+// CHECK: vminmaxph $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxph $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxph $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxph $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, -256(%edx){1to8}, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxph $123, -256(%edx){1to8}, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+
+// CHECK: vminmaxph $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxph $123, (%eax){1to32}, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x58,0x52,0x10,0x7b]
+ vminmaxph $123, (%eax){1to32}, %zmm3, %zmm2
+
+// CHECK: vminmaxph $123, -2048(,%ebp,2), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxph $123, -2048(,%ebp,2), %zmm3, %zmm2
+
+// CHECK: vminmaxph $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxph $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxph $123, -256(%edx){1to32}, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxph $123, -256(%edx){1to32}, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x52,0xd4,0x7b]
+ vminmaxps $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxps $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x52,0xd4,0x7b]
+ vminmaxps $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxps $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x52,0xd4,0x7b]
+ vminmaxps $123, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x48,0x52,0xd4,0x7b]
+ vminmaxps $123, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxps $123, {sae}, %zmm4, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x18,0x52,0xd4,0x7b]
+ vminmaxps $123, {sae}, %zmm4, %zmm3, %zmm2
+
+// CHECK: vminmaxps $123, %zmm4, %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x4f,0x52,0xd4,0x7b]
+ vminmaxps $123, %zmm4, %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxps $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x9f,0x52,0xd4,0x7b]
+ vminmaxps $123, {sae}, %zmm4, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0xd4,0x7b]
+ vminmaxps $123, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x61,0x18,0x52,0xd4,0x7b]
+ vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2
+
+// CHECK: vminmaxps $123, %ymm4, %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x2f,0x52,0xd4,0x7b]
+ vminmaxps $123, %ymm4, %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x61,0x9f,0x52,0xd4,0x7b]
+ vminmaxps $123, {sae}, %ymm4, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps $123, 268435456(%esp,%esi,8), %ymm3, %ymm2
+
+// CHECK: vminmaxps $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps $123, 291(%edi,%eax,4), %ymm3, %ymm2 {%k7}
+
+// CHECK: vminmaxps $123, (%eax){1to8}, %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x38,0x52,0x10,0x7b]
+ vminmaxps $123, (%eax){1to8}, %ymm3, %ymm2
+
+// CHECK: vminmaxps $123, -1024(,%ebp,2), %ymm3, %ymm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxps $123, -1024(,%ebp,2), %ymm3, %ymm2
+
+// CHECK: vminmaxps $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxps $123, 4064(%ecx), %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, -512(%edx){1to8}, %ymm3, %ymm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxps $123, -512(%edx){1to8}, %ymm3, %ymm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxps $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxps $123, (%eax){1to4}, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x18,0x52,0x10,0x7b]
+ vminmaxps $123, (%eax){1to4}, %xmm3, %xmm2
+
+// CHECK: vminmaxps $123, -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxps $123, -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxps $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxps $123, 2032(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, -512(%edx){1to4}, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxps $123, -512(%edx){1to4}, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps $123, 268435456(%esp,%esi,8), %zmm3, %zmm2
+
+// CHECK: vminmaxps $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps $123, 291(%edi,%eax,4), %zmm3, %zmm2 {%k7}
+
+// CHECK: vminmaxps $123, (%eax){1to16}, %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x58,0x52,0x10,0x7b]
+ vminmaxps $123, (%eax){1to16}, %zmm3, %zmm2
+
+// CHECK: vminmaxps $123, -2048(,%ebp,2), %zmm3, %zmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxps $123, -2048(,%ebp,2), %zmm3, %zmm2
+
+// CHECK: vminmaxps $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxps $123, 8128(%ecx), %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxps $123, -512(%edx){1to16}, %zmm3, %zmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxps $123, -512(%edx){1to16}, %zmm3, %zmm2 {%k7} {z}
+
+// CHECK: vminmaxsd $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0xd4,0x7b]
+ vminmaxsd $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxsd $123, {sae}, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x18,0x53,0xd4,0x7b]
+ vminmaxsd $123, {sae}, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxsd $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x53,0xd4,0x7b]
+ vminmaxsd $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxsd $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x9f,0x53,0xd4,0x7b]
+ vminmaxsd $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxsd $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsd $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxsd $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsd $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxsd $123, (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0x10,0x7b]
+ vminmaxsd $123, (%eax), %xmm3, %xmm2
+
+// CHECK: vminmaxsd $123, -256(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0x14,0x6d,0x00,0xff,0xff,0xff,0x7b]
+ vminmaxsd $123, -256(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxsd $123, 1016(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x53,0x51,0x7f,0x7b]
+ vminmaxsd $123, 1016(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxsd $123, -1024(%edx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x53,0x52,0x80,0x7b]
+ vminmaxsd $123, -1024(%edx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxsh $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0xd4,0x7b]
+ vminmaxsh $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxsh $123, {sae}, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x18,0x53,0xd4,0x7b]
+ vminmaxsh $123, {sae}, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxsh $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x53,0xd4,0x7b]
+ vminmaxsh $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxsh $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x9f,0x53,0xd4,0x7b]
+ vminmaxsh $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxsh $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsh $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxsh $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsh $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxsh $123, (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0x10,0x7b]
+ vminmaxsh $123, (%eax), %xmm3, %xmm2
+
+// CHECK: vminmaxsh $123, -64(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0x14,0x6d,0xc0,0xff,0xff,0xff,0x7b]
+ vminmaxsh $123, -64(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxsh $123, 254(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x53,0x51,0x7f,0x7b]
+ vminmaxsh $123, 254(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxsh $123, -256(%edx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x53,0x52,0x80,0x7b]
+ vminmaxsh $123, -256(%edx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxss $123, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0xd4,0x7b]
+ vminmaxss $123, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxss $123, {sae}, %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x18,0x53,0xd4,0x7b]
+ vminmaxss $123, {sae}, %xmm4, %xmm3, %xmm2
+
+// CHECK: vminmaxss $123, %xmm4, %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x53,0xd4,0x7b]
+ vminmaxss $123, %xmm4, %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxss $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x9f,0x53,0xd4,0x7b]
+ vminmaxss $123, {sae}, %xmm4, %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxss $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxss $123, 268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK: vminmaxss $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxss $123, 291(%edi,%eax,4), %xmm3, %xmm2 {%k7}
+
+// CHECK: vminmaxss $123, (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0x10,0x7b]
+ vminmaxss $123, (%eax), %xmm3, %xmm2
+
+// CHECK: vminmaxss $123, -128(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0x14,0x6d,0x80,0xff,0xff,0xff,0x7b]
+ vminmaxss $123, -128(,%ebp,2), %xmm3, %xmm2
+
+// CHECK: vminmaxss $123, 508(%ecx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x53,0x51,0x7f,0x7b]
+ vminmaxss $123, 508(%ecx), %xmm3, %xmm2 {%k7} {z}
+
+// CHECK: vminmaxss $123, -512(%edx), %xmm3, %xmm2 {%k7} {z}
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x53,0x52,0x80,0x7b]
+ vminmaxss $123, -512(%edx), %xmm3, %xmm2 {%k7} {z}
+
diff --git a/llvm/test/MC/X86/avx10.2minmax-32-intel.s b/llvm/test/MC/X86/avx10.2minmax-32-intel.s
new file mode 100644
index 0000000000000..1d668ee15a409
--- /dev/null
+++ b/llvm/test/MC/X86/avx10.2minmax-32-intel.s
@@ -0,0 +1,578 @@
+// RUN: llvm-mc -triple i386 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vminmaxnepbf16 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x08,0x52,0xd4,0x7b]
+ vminmaxnepbf16 xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxnepbf16 xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x0f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxnepbf16 xmm2 {k7} {z}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x8f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 xmm2 {k7} {z}, xmm3, xmm4, 123
+
+// CHECK: vminmaxnepbf16 zmm2, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x48,0x52,0xd4,0x7b]
+ vminmaxnepbf16 zmm2, zmm3, zmm4, 123
+
+// CHECK: vminmaxnepbf16 zmm2 {k7}, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x4f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 zmm2 {k7}, zmm3, zmm4, 123
+
+// CHECK: vminmaxnepbf16 zmm2 {k7} {z}, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0xcf,0x52,0xd4,0x7b]
+ vminmaxnepbf16 zmm2 {k7} {z}, zmm3, zmm4, 123
+
+// CHECK: vminmaxnepbf16 ymm2, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x28,0x52,0xd4,0x7b]
+ vminmaxnepbf16 ymm2, ymm3, ymm4, 123
+
+// CHECK: vminmaxnepbf16 ymm2 {k7}, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x2f,0x52,0xd4,0x7b]
+ vminmaxnepbf16 ymm2 {k7}, ymm3, ymm4, 123
+
+// CHECK: vminmaxnepbf16 ymm2 {k7} {z}, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0xaf,0x52,0xd4,0x7b]
+ vminmaxnepbf16 ymm2 {k7} {z}, ymm3, ymm4, 123
+
+// CHECK: vminmaxnepbf16 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxnepbf16 ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxnepbf16 ymm2, ymm3, word ptr [eax]{1to16}, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x38,0x52,0x10,0x7b]
+ vminmaxnepbf16 ymm2, ymm3, word ptr [eax]{1to16}, 123
+
+// CHECK: vminmaxnepbf16 ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxnepbf16 ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+
+// CHECK: vminmaxnepbf16 ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxnepbf16 ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+
+// CHECK: vminmaxnepbf16 ymm2 {k7} {z}, ymm3, word ptr [edx - 256]{1to16}, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxnepbf16 ymm2 {k7} {z}, ymm3, word ptr [edx - 256]{1to16}, 123
+
+// CHECK: vminmaxnepbf16 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxnepbf16 xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxnepbf16 xmm2, xmm3, word ptr [eax]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x18,0x52,0x10,0x7b]
+ vminmaxnepbf16 xmm2, xmm3, word ptr [eax]{1to8}, 123
+
+// CHECK: vminmaxnepbf16 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxnepbf16 xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK: vminmaxnepbf16 xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxnepbf16 xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK: vminmaxnepbf16 xmm2 {k7} {z}, xmm3, word ptr [edx - 256]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxnepbf16 xmm2 {k7} {z}, xmm3, word ptr [edx - 256]{1to8}, 123
+
+// CHECK: vminmaxnepbf16 zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxnepbf16 zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxnepbf16 zmm2, zmm3, word ptr [eax]{1to32}, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x58,0x52,0x10,0x7b]
+ vminmaxnepbf16 zmm2, zmm3, word ptr [eax]{1to32}, 123
+
+// CHECK: vminmaxnepbf16 zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxnepbf16 zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+
+// CHECK: vminmaxnepbf16 zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+// CHECK: encoding: [0x62,0xf3,0x67,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxnepbf16 zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+
+// CHECK: vminmaxnepbf16 zmm2 {k7} {z}, zmm3, word ptr [edx - 256]{1to32}, 123
+// CHECK: encoding: [0x62,0xf3,0x67,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxnepbf16 zmm2 {k7} {z}, zmm3, word ptr [edx - 256]{1to32}, 123
+
+// CHECK: vminmaxpd xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x52,0xd4,0x7b]
+ vminmaxpd xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxpd xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x52,0xd4,0x7b]
+ vminmaxpd xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxpd xmm2 {k7} {z}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x52,0xd4,0x7b]
+ vminmaxpd xmm2 {k7} {z}, xmm3, xmm4, 123
+
+// CHECK: vminmaxpd zmm2, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x48,0x52,0xd4,0x7b]
+ vminmaxpd zmm2, zmm3, zmm4, 123
+
+// CHECK: vminmaxpd zmm2, zmm3, zmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x18,0x52,0xd4,0x7b]
+ vminmaxpd zmm2, zmm3, zmm4, {sae}, 123
+
+// CHECK: vminmaxpd zmm2 {k7}, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x4f,0x52,0xd4,0x7b]
+ vminmaxpd zmm2 {k7}, zmm3, zmm4, 123
+
+// CHECK: vminmaxpd zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x9f,0x52,0xd4,0x7b]
+ vminmaxpd zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+
+// CHECK: vminmaxpd ymm2, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0xd4,0x7b]
+ vminmaxpd ymm2, ymm3, ymm4, 123
+
+// CHECK: vminmaxpd ymm2, ymm3, ymm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0xe1,0x18,0x52,0xd4,0x7b]
+ vminmaxpd ymm2, ymm3, ymm4, {sae}, 123
+
+// CHECK: vminmaxpd ymm2 {k7}, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x2f,0x52,0xd4,0x7b]
+ vminmaxpd ymm2 {k7}, ymm3, ymm4, 123
+
+// CHECK: vminmaxpd ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0xe1,0x9f,0x52,0xd4,0x7b]
+ vminmaxpd ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+
+// CHECK: vminmaxpd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxpd ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxpd ymm2, ymm3, qword ptr [eax]{1to4}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x38,0x52,0x10,0x7b]
+ vminmaxpd ymm2, ymm3, qword ptr [eax]{1to4}, 123
+
+// CHECK: vminmaxpd ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxpd ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+
+// CHECK: vminmaxpd ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxpd ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+
+// CHECK: vminmaxpd ymm2 {k7} {z}, ymm3, qword ptr [edx - 1024]{1to4}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxpd ymm2 {k7} {z}, ymm3, qword ptr [edx - 1024]{1to4}, 123
+
+// CHECK: vminmaxpd xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxpd xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxpd xmm2, xmm3, qword ptr [eax]{1to2}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x18,0x52,0x10,0x7b]
+ vminmaxpd xmm2, xmm3, qword ptr [eax]{1to2}, 123
+
+// CHECK: vminmaxpd xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxpd xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK: vminmaxpd xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxpd xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK: vminmaxpd xmm2 {k7} {z}, xmm3, qword ptr [edx - 1024]{1to2}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxpd xmm2 {k7} {z}, xmm3, qword ptr [edx - 1024]{1to2}, 123
+
+// CHECK: vminmaxpd zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxpd zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxpd zmm2, zmm3, qword ptr [eax]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x58,0x52,0x10,0x7b]
+ vminmaxpd zmm2, zmm3, qword ptr [eax]{1to8}, 123
+
+// CHECK: vminmaxpd zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxpd zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+
+// CHECK: vminmaxpd zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxpd zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+
+// CHECK: vminmaxpd zmm2 {k7} {z}, zmm3, qword ptr [edx - 1024]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxpd zmm2 {k7} {z}, zmm3, qword ptr [edx - 1024]{1to8}, 123
+
+// CHECK: vminmaxph xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x52,0xd4,0x7b]
+ vminmaxph xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxph xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x52,0xd4,0x7b]
+ vminmaxph xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxph xmm2 {k7} {z}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x52,0xd4,0x7b]
+ vminmaxph xmm2 {k7} {z}, xmm3, xmm4, 123
+
+// CHECK: vminmaxph zmm2, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x48,0x52,0xd4,0x7b]
+ vminmaxph zmm2, zmm3, zmm4, 123
+
+// CHECK: vminmaxph zmm2, zmm3, zmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x18,0x52,0xd4,0x7b]
+ vminmaxph zmm2, zmm3, zmm4, {sae}, 123
+
+// CHECK: vminmaxph zmm2 {k7}, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x4f,0x52,0xd4,0x7b]
+ vminmaxph zmm2 {k7}, zmm3, zmm4, 123
+
+// CHECK: vminmaxph zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x9f,0x52,0xd4,0x7b]
+ vminmaxph zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+
+// CHECK: vminmaxph ymm2, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0xd4,0x7b]
+ vminmaxph ymm2, ymm3, ymm4, 123
+
+// CHECK: vminmaxph ymm2, ymm3, ymm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x60,0x18,0x52,0xd4,0x7b]
+ vminmaxph ymm2, ymm3, ymm4, {sae}, 123
+
+// CHECK: vminmaxph ymm2 {k7}, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x2f,0x52,0xd4,0x7b]
+ vminmaxph ymm2 {k7}, ymm3, ymm4, 123
+
+// CHECK: vminmaxph ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x60,0x9f,0x52,0xd4,0x7b]
+ vminmaxph ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+
+// CHECK: vminmaxph ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxph ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxph ymm2, ymm3, word ptr [eax]{1to16}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x38,0x52,0x10,0x7b]
+ vminmaxph ymm2, ymm3, word ptr [eax]{1to16}, 123
+
+// CHECK: vminmaxph ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxph ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+
+// CHECK: vminmaxph ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxph ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+
+// CHECK: vminmaxph ymm2 {k7} {z}, ymm3, word ptr [edx - 256]{1to16}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxph ymm2 {k7} {z}, ymm3, word ptr [edx - 256]{1to16}, 123
+
+// CHECK: vminmaxph xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxph xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxph xmm2, xmm3, word ptr [eax]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x18,0x52,0x10,0x7b]
+ vminmaxph xmm2, xmm3, word ptr [eax]{1to8}, 123
+
+// CHECK: vminmaxph xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxph xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK: vminmaxph xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxph xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK: vminmaxph xmm2 {k7} {z}, xmm3, word ptr [edx - 256]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxph xmm2 {k7} {z}, xmm3, word ptr [edx - 256]{1to8}, 123
+
+// CHECK: vminmaxph zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxph zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxph zmm2, zmm3, word ptr [eax]{1to32}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x58,0x52,0x10,0x7b]
+ vminmaxph zmm2, zmm3, word ptr [eax]{1to32}, 123
+
+// CHECK: vminmaxph zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxph zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+
+// CHECK: vminmaxph zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxph zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+
+// CHECK: vminmaxph zmm2 {k7} {z}, zmm3, word ptr [edx - 256]{1to32}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxph zmm2 {k7} {z}, zmm3, word ptr [edx - 256]{1to32}, 123
+
+// CHECK: vminmaxps xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x52,0xd4,0x7b]
+ vminmaxps xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxps xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x52,0xd4,0x7b]
+ vminmaxps xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxps xmm2 {k7} {z}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x52,0xd4,0x7b]
+ vminmaxps xmm2 {k7} {z}, xmm3, xmm4, 123
+
+// CHECK: vminmaxps zmm2, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x48,0x52,0xd4,0x7b]
+ vminmaxps zmm2, zmm3, zmm4, 123
+
+// CHECK: vminmaxps zmm2, zmm3, zmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x18,0x52,0xd4,0x7b]
+ vminmaxps zmm2, zmm3, zmm4, {sae}, 123
+
+// CHECK: vminmaxps zmm2 {k7}, zmm3, zmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x4f,0x52,0xd4,0x7b]
+ vminmaxps zmm2 {k7}, zmm3, zmm4, 123
+
+// CHECK: vminmaxps zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x9f,0x52,0xd4,0x7b]
+ vminmaxps zmm2 {k7} {z}, zmm3, zmm4, {sae}, 123
+
+// CHECK: vminmaxps ymm2, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0xd4,0x7b]
+ vminmaxps ymm2, ymm3, ymm4, 123
+
+// CHECK: vminmaxps ymm2, ymm3, ymm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x61,0x18,0x52,0xd4,0x7b]
+ vminmaxps ymm2, ymm3, ymm4, {sae}, 123
+
+// CHECK: vminmaxps ymm2 {k7}, ymm3, ymm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x2f,0x52,0xd4,0x7b]
+ vminmaxps ymm2 {k7}, ymm3, ymm4, 123
+
+// CHECK: vminmaxps ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x61,0x9f,0x52,0xd4,0x7b]
+ vminmaxps ymm2 {k7} {z}, ymm3, ymm4, {sae}, 123
+
+// CHECK: vminmaxps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxps ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxps ymm2, ymm3, dword ptr [eax]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x38,0x52,0x10,0x7b]
+ vminmaxps ymm2, ymm3, dword ptr [eax]{1to8}, 123
+
+// CHECK: vminmaxps ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxps ymm2, ymm3, ymmword ptr [2*ebp - 1024], 123
+
+// CHECK: vminmaxps ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0xaf,0x52,0x51,0x7f,0x7b]
+ vminmaxps ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064], 123
+
+// CHECK: vminmaxps ymm2 {k7} {z}, ymm3, dword ptr [edx - 512]{1to8}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0xbf,0x52,0x52,0x80,0x7b]
+ vminmaxps ymm2 {k7} {z}, ymm3, dword ptr [edx - 512]{1to8}, 123
+
+// CHECK: vminmaxps xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxps xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxps xmm2, xmm3, dword ptr [eax]{1to4}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x18,0x52,0x10,0x7b]
+ vminmaxps xmm2, xmm3, dword ptr [eax]{1to4}, 123
+
+// CHECK: vminmaxps xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxps xmm2, xmm3, xmmword ptr [2*ebp - 512], 123
+
+// CHECK: vminmaxps xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x52,0x51,0x7f,0x7b]
+ vminmaxps xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032], 123
+
+// CHECK: vminmaxps xmm2 {k7} {z}, xmm3, dword ptr [edx - 512]{1to4}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x9f,0x52,0x52,0x80,0x7b]
+ vminmaxps xmm2 {k7} {z}, xmm3, dword ptr [edx - 512]{1to4}, 123
+
+// CHECK: vminmaxps zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxps zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxps zmm2, zmm3, dword ptr [eax]{1to16}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x58,0x52,0x10,0x7b]
+ vminmaxps zmm2, zmm3, dword ptr [eax]{1to16}, 123
+
+// CHECK: vminmaxps zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxps zmm2, zmm3, zmmword ptr [2*ebp - 2048], 123
+
+// CHECK: vminmaxps zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0xcf,0x52,0x51,0x7f,0x7b]
+ vminmaxps zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128], 123
+
+// CHECK: vminmaxps zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0xdf,0x52,0x52,0x80,0x7b]
+ vminmaxps zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16}, 123
+
+// CHECK: vminmaxsd xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0xd4,0x7b]
+ vminmaxsd xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxsd xmm2, xmm3, xmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x18,0x53,0xd4,0x7b]
+ vminmaxsd xmm2, xmm3, xmm4, {sae}, 123
+
+// CHECK: vminmaxsd xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x53,0xd4,0x7b]
+ vminmaxsd xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxsd xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x9f,0x53,0xd4,0x7b]
+ vminmaxsd xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+
+// CHECK: vminmaxsd xmm2, xmm3, qword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsd xmm2, xmm3, qword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxsd xmm2 {k7}, xmm3, qword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsd xmm2 {k7}, xmm3, qword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxsd xmm2, xmm3, qword ptr [eax], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0x10,0x7b]
+ vminmaxsd xmm2, xmm3, qword ptr [eax], 123
+
+// CHECK: vminmaxsd xmm2, xmm3, qword ptr [2*ebp - 256], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x08,0x53,0x14,0x6d,0x00,0xff,0xff,0xff,0x7b]
+ vminmaxsd xmm2, xmm3, qword ptr [2*ebp - 256], 123
+
+// CHECK: vminmaxsd xmm2 {k7} {z}, xmm3, qword ptr [ecx + 1016], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x53,0x51,0x7f,0x7b]
+ vminmaxsd xmm2 {k7} {z}, xmm3, qword ptr [ecx + 1016], 123
+
+// CHECK: vminmaxsd xmm2 {k7} {z}, xmm3, qword ptr [edx - 1024], 123
+// CHECK: encoding: [0x62,0xf3,0xe5,0x8f,0x53,0x52,0x80,0x7b]
+ vminmaxsd xmm2 {k7} {z}, xmm3, qword ptr [edx - 1024], 123
+
+// CHECK: vminmaxsh xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0xd4,0x7b]
+ vminmaxsh xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxsh xmm2, xmm3, xmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x18,0x53,0xd4,0x7b]
+ vminmaxsh xmm2, xmm3, xmm4, {sae}, 123
+
+// CHECK: vminmaxsh xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x53,0xd4,0x7b]
+ vminmaxsh xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxsh xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x9f,0x53,0xd4,0x7b]
+ vminmaxsh xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+
+// CHECK: vminmaxsh xmm2, xmm3, word ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsh xmm2, xmm3, word ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxsh xmm2 {k7}, xmm3, word ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsh xmm2 {k7}, xmm3, word ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxsh xmm2, xmm3, word ptr [eax], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0x10,0x7b]
+ vminmaxsh xmm2, xmm3, word ptr [eax], 123
+
+// CHECK: vminmaxsh xmm2, xmm3, word ptr [2*ebp - 64], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x08,0x53,0x14,0x6d,0xc0,0xff,0xff,0xff,0x7b]
+ vminmaxsh xmm2, xmm3, word ptr [2*ebp - 64], 123
+
+// CHECK: vminmaxsh xmm2 {k7} {z}, xmm3, word ptr [ecx + 254], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x53,0x51,0x7f,0x7b]
+ vminmaxsh xmm2 {k7} {z}, xmm3, word ptr [ecx + 254], 123
+
+// CHECK: vminmaxsh xmm2 {k7} {z}, xmm3, word ptr [edx - 256], 123
+// CHECK: encoding: [0x62,0xf3,0x64,0x8f,0x53,0x52,0x80,0x7b]
+ vminmaxsh xmm2 {k7} {z}, xmm3, word ptr [edx - 256], 123
+
+// CHECK: vminmaxss xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0xd4,0x7b]
+ vminmaxss xmm2, xmm3, xmm4, 123
+
+// CHECK: vminmaxss xmm2, xmm3, xmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x18,0x53,0xd4,0x7b]
+ vminmaxss xmm2, xmm3, xmm4, {sae}, 123
+
+// CHECK: vminmaxss xmm2 {k7}, xmm3, xmm4, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x53,0xd4,0x7b]
+ vminmaxss xmm2 {k7}, xmm3, xmm4, 123
+
+// CHECK: vminmaxss xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x9f,0x53,0xd4,0x7b]
+ vminmaxss xmm2 {k7} {z}, xmm3, xmm4, {sae}, 123
+
+// CHECK: vminmaxss xmm2, xmm3, dword ptr [esp + 8*esi + 268435456], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0x94,0xf4,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxss xmm2, xmm3, dword ptr [esp + 8*esi + 268435456], 123
+
+// CHECK: vminmaxss xmm2 {k7}, xmm3, dword ptr [edi + 4*eax + 291], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x0f,0x53,0x94,0x87,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxss xmm2 {k7}, xmm3, dword ptr [edi + 4*eax + 291], 123
+
+// CHECK: vminmaxss xmm2, xmm3, dword ptr [eax], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0x10,0x7b]
+ vminmaxss xmm2, xmm3, dword ptr [eax], 123
+
+// CHECK: vminmaxss xmm2, xmm3, dword ptr [2*ebp - 128], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x08,0x53,0x14,0x6d,0x80,0xff,0xff,0xff,0x7b]
+ vminmaxss xmm2, xmm3, dword ptr [2*ebp - 128], 123
+
+// CHECK: vminmaxss xmm2 {k7} {z}, xmm3, dword ptr [ecx + 508], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x53,0x51,0x7f,0x7b]
+ vminmaxss xmm2 {k7} {z}, xmm3, dword ptr [ecx + 508], 123
+
+// CHECK: vminmaxss xmm2 {k7} {z}, xmm3, dword ptr [edx - 512], 123
+// CHECK: encoding: [0x62,0xf3,0x65,0x8f,0x53,0x52,0x80,0x7b]
+ vminmaxss xmm2 {k7} {z}, xmm3, dword ptr [edx - 512], 123
+
diff --git a/llvm/test/MC/X86/avx10.2minmax-64-att.s b/llvm/test/MC/X86/avx10.2minmax-64-att.s
new file mode 100644
index 0000000000000..f58b4a51b995f
--- /dev/null
+++ b/llvm/test/MC/X86/avx10.2minmax-64-att.s
@@ -0,0 +1,578 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x47,0x00,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x47,0x07,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x47,0x87,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0x47,0x40,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x47,0x47,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x47,0xc7,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %zmm24, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0x47,0x20,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x47,0x27,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x47,0xa7,0x52,0xf0,0x7b]
+ vminmaxnepbf16 $123, %ymm24, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xa3,0x47,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+
+// CHECK: vminmaxnepbf16 $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x47,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, (%rip){1to16}, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0x47,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, (%rip){1to16}, %ymm23, %ymm22
+
+// CHECK: vminmaxnepbf16 $123, -1024(,%rbp,2), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0x47,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxnepbf16 $123, -1024(,%rbp,2), %ymm23, %ymm22
+
+// CHECK: vminmaxnepbf16 $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x47,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxnepbf16 $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, -256(%rdx){1to16}, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x47,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxnepbf16 $123, -256(%rdx){1to16}, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0x47,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxnepbf16 $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x47,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, (%rip){1to8}, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x47,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, (%rip){1to8}, %xmm23, %xmm22
+
+// CHECK: vminmaxnepbf16 $123, -512(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x47,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxnepbf16 $123, -512(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxnepbf16 $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x47,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxnepbf16 $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, -256(%rdx){1to8}, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x47,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxnepbf16 $123, -256(%rdx){1to8}, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xa3,0x47,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+
+// CHECK: vminmaxnepbf16 $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x47,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxnepbf16 $123, (%rip){1to32}, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0x47,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxnepbf16 $123, (%rip){1to32}, %zmm23, %zmm22
+
+// CHECK: vminmaxnepbf16 $123, -2048(,%rbp,2), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0x47,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxnepbf16 $123, -2048(,%rbp,2), %zmm23, %zmm22
+
+// CHECK: vminmaxnepbf16 $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x47,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxnepbf16 $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxnepbf16 $123, -256(%rdx){1to32}, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x47,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxnepbf16 $123, -256(%rdx){1to32}, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0xc5,0x00,0x52,0xf0,0x7b]
+ vminmaxpd $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxpd $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0xc5,0x07,0x52,0xf0,0x7b]
+ vminmaxpd $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxpd $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0xc5,0x87,0x52,0xf0,0x7b]
+ vminmaxpd $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0xc5,0x40,0x52,0xf0,0x7b]
+ vminmaxpd $123, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxpd $123, {sae}, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0xc5,0x10,0x52,0xf0,0x7b]
+ vminmaxpd $123, {sae}, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxpd $123, %zmm24, %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0xc5,0x47,0x52,0xf0,0x7b]
+ vminmaxpd $123, %zmm24, %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxpd $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0xc5,0x97,0x52,0xf0,0x7b]
+ vminmaxpd $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0xc5,0x20,0x52,0xf0,0x7b]
+ vminmaxpd $123, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0xc1,0x10,0x52,0xf0,0x7b]
+ vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxpd $123, %ymm24, %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0xc5,0x27,0x52,0xf0,0x7b]
+ vminmaxpd $123, %ymm24, %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0xc1,0x97,0x52,0xf0,0x7b]
+ vminmaxpd $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xa3,0xc5,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+
+// CHECK: vminmaxpd $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0xc5,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxpd $123, (%rip){1to4}, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxpd $123, (%rip){1to4}, %ymm23, %ymm22
+
+// CHECK: vminmaxpd $123, -1024(,%rbp,2), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxpd $123, -1024(,%rbp,2), %ymm23, %ymm22
+
+// CHECK: vminmaxpd $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxpd $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, -1024(%rdx){1to4}, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxpd $123, -1024(%rdx){1to4}, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0xc5,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxpd $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0xc5,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxpd $123, (%rip){1to2}, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxpd $123, (%rip){1to2}, %xmm23, %xmm22
+
+// CHECK: vminmaxpd $123, -512(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxpd $123, -512(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxpd $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxpd $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, -1024(%rdx){1to2}, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxpd $123, -1024(%rdx){1to2}, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xa3,0xc5,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+
+// CHECK: vminmaxpd $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0xc5,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxpd $123, (%rip){1to8}, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxpd $123, (%rip){1to8}, %zmm23, %zmm22
+
+// CHECK: vminmaxpd $123, -2048(,%rbp,2), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxpd $123, -2048(,%rbp,2), %zmm23, %zmm22
+
+// CHECK: vminmaxpd $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxpd $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxpd $123, -1024(%rdx){1to8}, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxpd $123, -1024(%rdx){1to8}, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x44,0x00,0x52,0xf0,0x7b]
+ vminmaxph $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxph $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x44,0x07,0x52,0xf0,0x7b]
+ vminmaxph $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxph $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x44,0x87,0x52,0xf0,0x7b]
+ vminmaxph $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0x44,0x40,0x52,0xf0,0x7b]
+ vminmaxph $123, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxph $123, {sae}, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0x44,0x10,0x52,0xf0,0x7b]
+ vminmaxph $123, {sae}, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxph $123, %zmm24, %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x44,0x47,0x52,0xf0,0x7b]
+ vminmaxph $123, %zmm24, %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxph $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x44,0x97,0x52,0xf0,0x7b]
+ vminmaxph $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0x44,0x20,0x52,0xf0,0x7b]
+ vminmaxph $123, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0x40,0x10,0x52,0xf0,0x7b]
+ vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxph $123, %ymm24, %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x44,0x27,0x52,0xf0,0x7b]
+ vminmaxph $123, %ymm24, %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x40,0x97,0x52,0xf0,0x7b]
+ vminmaxph $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xa3,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+
+// CHECK: vminmaxph $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x44,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxph $123, (%rip){1to16}, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxph $123, (%rip){1to16}, %ymm23, %ymm22
+
+// CHECK: vminmaxph $123, -1024(,%rbp,2), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxph $123, -1024(,%rbp,2), %ymm23, %ymm22
+
+// CHECK: vminmaxph $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxph $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, -256(%rdx){1to16}, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxph $123, -256(%rdx){1to16}, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0x44,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxph $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x44,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxph $123, (%rip){1to8}, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxph $123, (%rip){1to8}, %xmm23, %xmm22
+
+// CHECK: vminmaxph $123, -512(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxph $123, -512(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxph $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxph $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, -256(%rdx){1to8}, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxph $123, -256(%rdx){1to8}, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xa3,0x44,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+
+// CHECK: vminmaxph $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x44,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxph $123, (%rip){1to32}, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxph $123, (%rip){1to32}, %zmm23, %zmm22
+
+// CHECK: vminmaxph $123, -2048(,%rbp,2), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxph $123, -2048(,%rbp,2), %zmm23, %zmm22
+
+// CHECK: vminmaxph $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxph $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxph $123, -256(%rdx){1to32}, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxph $123, -256(%rdx){1to32}, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x45,0x00,0x52,0xf0,0x7b]
+ vminmaxps $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxps $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x45,0x07,0x52,0xf0,0x7b]
+ vminmaxps $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxps $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x45,0x87,0x52,0xf0,0x7b]
+ vminmaxps $123, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0x45,0x40,0x52,0xf0,0x7b]
+ vminmaxps $123, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxps $123, {sae}, %zmm24, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0x83,0x45,0x10,0x52,0xf0,0x7b]
+ vminmaxps $123, {sae}, %zmm24, %zmm23, %zmm22
+
+// CHECK: vminmaxps $123, %zmm24, %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x45,0x47,0x52,0xf0,0x7b]
+ vminmaxps $123, %zmm24, %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxps $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x45,0x97,0x52,0xf0,0x7b]
+ vminmaxps $123, {sae}, %zmm24, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0x45,0x20,0x52,0xf0,0x7b]
+ vminmaxps $123, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0x83,0x41,0x10,0x52,0xf0,0x7b]
+ vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22
+
+// CHECK: vminmaxps $123, %ymm24, %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x45,0x27,0x52,0xf0,0x7b]
+ vminmaxps $123, %ymm24, %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x41,0x97,0x52,0xf0,0x7b]
+ vminmaxps $123, {sae}, %ymm24, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xa3,0x45,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps $123, 268435456(%rbp,%r14,8), %ymm23, %ymm22
+
+// CHECK: vminmaxps $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x45,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps $123, 291(%r8,%rax,4), %ymm23, %ymm22 {%k7}
+
+// CHECK: vminmaxps $123, (%rip){1to8}, %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxps $123, (%rip){1to8}, %ymm23, %ymm22
+
+// CHECK: vminmaxps $123, -1024(,%rbp,2), %ymm23, %ymm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxps $123, -1024(,%rbp,2), %ymm23, %ymm22
+
+// CHECK: vminmaxps $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxps $123, 4064(%rcx), %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxps $123, -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0x45,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxps $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x45,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxps $123, (%rip){1to4}, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxps $123, (%rip){1to4}, %xmm23, %xmm22
+
+// CHECK: vminmaxps $123, -512(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxps $123, -512(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxps $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxps $123, 2032(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxps $123, -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xa3,0x45,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps $123, 268435456(%rbp,%r14,8), %zmm23, %zmm22
+
+// CHECK: vminmaxps $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x45,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps $123, 291(%r8,%rax,4), %zmm23, %zmm22 {%k7}
+
+// CHECK: vminmaxps $123, (%rip){1to16}, %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxps $123, (%rip){1to16}, %zmm23, %zmm22
+
+// CHECK: vminmaxps $123, -2048(,%rbp,2), %zmm23, %zmm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxps $123, -2048(,%rbp,2), %zmm23, %zmm22
+
+// CHECK: vminmaxps $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxps $123, 8128(%rcx), %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxps $123, -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxps $123, -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z}
+
+// CHECK: vminmaxsd $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0xc5,0x00,0x53,0xf0,0x7b]
+ vminmaxsd $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxsd $123, {sae}, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0xc5,0x10,0x53,0xf0,0x7b]
+ vminmaxsd $123, {sae}, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxsd $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0xc5,0x07,0x53,0xf0,0x7b]
+ vminmaxsd $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxsd $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0xc5,0x97,0x53,0xf0,0x7b]
+ vminmaxsd $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxsd $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0xc5,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsd $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxsd $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0xc5,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsd $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxsd $123, (%rip), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxsd $123, (%rip), %xmm23, %xmm22
+
+// CHECK: vminmaxsd $123, -256(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0xc5,0x00,0x53,0x34,0x6d,0x00,0xff,0xff,0xff,0x7b]
+ vminmaxsd $123, -256(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxsd $123, 1016(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0x87,0x53,0x71,0x7f,0x7b]
+ vminmaxsd $123, 1016(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxsd $123, -1024(%rdx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0xc5,0x87,0x53,0x72,0x80,0x7b]
+ vminmaxsd $123, -1024(%rdx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxsh $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x44,0x00,0x53,0xf0,0x7b]
+ vminmaxsh $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxsh $123, {sae}, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x44,0x10,0x53,0xf0,0x7b]
+ vminmaxsh $123, {sae}, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxsh $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x44,0x07,0x53,0xf0,0x7b]
+ vminmaxsh $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxsh $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x44,0x97,0x53,0xf0,0x7b]
+ vminmaxsh $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxsh $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0x44,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsh $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxsh $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x44,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsh $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxsh $123, (%rip), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxsh $123, (%rip), %xmm23, %xmm22
+
+// CHECK: vminmaxsh $123, -64(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x44,0x00,0x53,0x34,0x6d,0xc0,0xff,0xff,0xff,0x7b]
+ vminmaxsh $123, -64(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxsh $123, 254(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0x87,0x53,0x71,0x7f,0x7b]
+ vminmaxsh $123, 254(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxsh $123, -256(%rdx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x44,0x87,0x53,0x72,0x80,0x7b]
+ vminmaxsh $123, -256(%rdx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxss $123, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x45,0x00,0x53,0xf0,0x7b]
+ vminmaxss $123, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxss $123, {sae}, %xmm24, %xmm23, %xmm22
+// CHECK: encoding: [0x62,0x83,0x45,0x10,0x53,0xf0,0x7b]
+ vminmaxss $123, {sae}, %xmm24, %xmm23, %xmm22
+
+// CHECK: vminmaxss $123, %xmm24, %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0x83,0x45,0x07,0x53,0xf0,0x7b]
+ vminmaxss $123, %xmm24, %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxss $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0x83,0x45,0x97,0x53,0xf0,0x7b]
+ vminmaxss $123, {sae}, %xmm24, %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxss $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xa3,0x45,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxss $123, 268435456(%rbp,%r14,8), %xmm23, %xmm22
+
+// CHECK: vminmaxss $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+// CHECK: encoding: [0x62,0xc3,0x45,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxss $123, 291(%r8,%rax,4), %xmm23, %xmm22 {%k7}
+
+// CHECK: vminmaxss $123, (%rip), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxss $123, (%rip), %xmm23, %xmm22
+
+// CHECK: vminmaxss $123, -128(,%rbp,2), %xmm23, %xmm22
+// CHECK: encoding: [0x62,0xe3,0x45,0x00,0x53,0x34,0x6d,0x80,0xff,0xff,0xff,0x7b]
+ vminmaxss $123, -128(,%rbp,2), %xmm23, %xmm22
+
+// CHECK: vminmaxss $123, 508(%rcx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0x87,0x53,0x71,0x7f,0x7b]
+ vminmaxss $123, 508(%rcx), %xmm23, %xmm22 {%k7} {z}
+
+// CHECK: vminmaxss $123, -512(%rdx), %xmm23, %xmm22 {%k7} {z}
+// CHECK: encoding: [0x62,0xe3,0x45,0x87,0x53,0x72,0x80,0x7b]
+ vminmaxss $123, -512(%rdx), %xmm23, %xmm22 {%k7} {z}
+
diff --git a/llvm/test/MC/X86/avx10.2minmax-64-intel.s b/llvm/test/MC/X86/avx10.2minmax-64-intel.s
new file mode 100644
index 0000000000000..8630d7f96165c
--- /dev/null
+++ b/llvm/test/MC/X86/avx10.2minmax-64-intel.s
@@ -0,0 +1,578 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vminmaxnepbf16 xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x00,0x52,0xf0,0x7b]
+ vminmaxnepbf16 xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxnepbf16 xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x07,0x52,0xf0,0x7b]
+ vminmaxnepbf16 xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxnepbf16 xmm22 {k7} {z}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x87,0x52,0xf0,0x7b]
+ vminmaxnepbf16 xmm22 {k7} {z}, xmm23, xmm24, 123
+
+// CHECK: vminmaxnepbf16 zmm22, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x40,0x52,0xf0,0x7b]
+ vminmaxnepbf16 zmm22, zmm23, zmm24, 123
+
+// CHECK: vminmaxnepbf16 zmm22 {k7}, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x47,0x52,0xf0,0x7b]
+ vminmaxnepbf16 zmm22 {k7}, zmm23, zmm24, 123
+
+// CHECK: vminmaxnepbf16 zmm22 {k7} {z}, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0xc7,0x52,0xf0,0x7b]
+ vminmaxnepbf16 zmm22 {k7} {z}, zmm23, zmm24, 123
+
+// CHECK: vminmaxnepbf16 ymm22, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x20,0x52,0xf0,0x7b]
+ vminmaxnepbf16 ymm22, ymm23, ymm24, 123
+
+// CHECK: vminmaxnepbf16 ymm22 {k7}, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0x27,0x52,0xf0,0x7b]
+ vminmaxnepbf16 ymm22 {k7}, ymm23, ymm24, 123
+
+// CHECK: vminmaxnepbf16 ymm22 {k7} {z}, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x47,0xa7,0x52,0xf0,0x7b]
+ vminmaxnepbf16 ymm22 {k7} {z}, ymm23, ymm24, 123
+
+// CHECK: vminmaxnepbf16 ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x47,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxnepbf16 ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x47,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxnepbf16 ymm22, ymm23, word ptr [rip]{1to16}, 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxnepbf16 ymm22, ymm23, word ptr [rip]{1to16}, 123
+
+// CHECK: vminmaxnepbf16 ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxnepbf16 ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+
+// CHECK: vminmaxnepbf16 ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+// CHECK: encoding: [0x62,0xe3,0x47,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxnepbf16 ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+
+// CHECK: vminmaxnepbf16 ymm22 {k7} {z}, ymm23, word ptr [rdx - 256]{1to16}, 123
+// CHECK: encoding: [0x62,0xe3,0x47,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxnepbf16 ymm22 {k7} {z}, ymm23, word ptr [rdx - 256]{1to16}, 123
+
+// CHECK: vminmaxnepbf16 xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x47,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxnepbf16 xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x47,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxnepbf16 xmm22, xmm23, word ptr [rip]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxnepbf16 xmm22, xmm23, word ptr [rip]{1to8}, 123
+
+// CHECK: vminmaxnepbf16 xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxnepbf16 xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vminmaxnepbf16 xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxnepbf16 xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vminmaxnepbf16 xmm22 {k7} {z}, xmm23, word ptr [rdx - 256]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxnepbf16 xmm22 {k7} {z}, xmm23, word ptr [rdx - 256]{1to8}, 123
+
+// CHECK: vminmaxnepbf16 zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x47,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxnepbf16 zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxnepbf16 zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x47,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxnepbf16 zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxnepbf16 zmm22, zmm23, word ptr [rip]{1to32}, 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxnepbf16 zmm22, zmm23, word ptr [rip]{1to32}, 123
+
+// CHECK: vminmaxnepbf16 zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+// CHECK: encoding: [0x62,0xe3,0x47,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxnepbf16 zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+
+// CHECK: vminmaxnepbf16 zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+// CHECK: encoding: [0x62,0xe3,0x47,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxnepbf16 zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+
+// CHECK: vminmaxnepbf16 zmm22 {k7} {z}, zmm23, word ptr [rdx - 256]{1to32}, 123
+// CHECK: encoding: [0x62,0xe3,0x47,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxnepbf16 zmm22 {k7} {z}, zmm23, word ptr [rdx - 256]{1to32}, 123
+
+// CHECK: vminmaxpd xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x00,0x52,0xf0,0x7b]
+ vminmaxpd xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxpd xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x07,0x52,0xf0,0x7b]
+ vminmaxpd xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxpd xmm22 {k7} {z}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x87,0x52,0xf0,0x7b]
+ vminmaxpd xmm22 {k7} {z}, xmm23, xmm24, 123
+
+// CHECK: vminmaxpd zmm22, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x40,0x52,0xf0,0x7b]
+ vminmaxpd zmm22, zmm23, zmm24, 123
+
+// CHECK: vminmaxpd zmm22, zmm23, zmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x10,0x52,0xf0,0x7b]
+ vminmaxpd zmm22, zmm23, zmm24, {sae}, 123
+
+// CHECK: vminmaxpd zmm22 {k7}, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x47,0x52,0xf0,0x7b]
+ vminmaxpd zmm22 {k7}, zmm23, zmm24, 123
+
+// CHECK: vminmaxpd zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x97,0x52,0xf0,0x7b]
+ vminmaxpd zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+
+// CHECK: vminmaxpd ymm22, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x20,0x52,0xf0,0x7b]
+ vminmaxpd ymm22, ymm23, ymm24, 123
+
+// CHECK: vminmaxpd ymm22, ymm23, ymm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0xc1,0x10,0x52,0xf0,0x7b]
+ vminmaxpd ymm22, ymm23, ymm24, {sae}, 123
+
+// CHECK: vminmaxpd ymm22 {k7}, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x27,0x52,0xf0,0x7b]
+ vminmaxpd ymm22 {k7}, ymm23, ymm24, 123
+
+// CHECK: vminmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0xc1,0x97,0x52,0xf0,0x7b]
+ vminmaxpd ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+
+// CHECK: vminmaxpd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0xc5,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxpd ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0xc5,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxpd ymm22, ymm23, qword ptr [rip]{1to4}, 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxpd ymm22, ymm23, qword ptr [rip]{1to4}, 123
+
+// CHECK: vminmaxpd ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxpd ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+
+// CHECK: vminmaxpd ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxpd ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+
+// CHECK: vminmaxpd ymm22 {k7} {z}, ymm23, qword ptr [rdx - 1024]{1to4}, 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxpd ymm22 {k7} {z}, ymm23, qword ptr [rdx - 1024]{1to4}, 123
+
+// CHECK: vminmaxpd xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0xc5,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxpd xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0xc5,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxpd xmm22, xmm23, qword ptr [rip]{1to2}, 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxpd xmm22, xmm23, qword ptr [rip]{1to2}, 123
+
+// CHECK: vminmaxpd xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxpd xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vminmaxpd xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxpd xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vminmaxpd xmm22 {k7} {z}, xmm23, qword ptr [rdx - 1024]{1to2}, 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxpd xmm22 {k7} {z}, xmm23, qword ptr [rdx - 1024]{1to2}, 123
+
+// CHECK: vminmaxpd zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0xc5,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxpd zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxpd zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0xc5,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxpd zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxpd zmm22, zmm23, qword ptr [rip]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxpd zmm22, zmm23, qword ptr [rip]{1to8}, 123
+
+// CHECK: vminmaxpd zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxpd zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+
+// CHECK: vminmaxpd zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxpd zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+
+// CHECK: vminmaxpd zmm22 {k7} {z}, zmm23, qword ptr [rdx - 1024]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxpd zmm22 {k7} {z}, zmm23, qword ptr [rdx - 1024]{1to8}, 123
+
+// CHECK: vminmaxph xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x00,0x52,0xf0,0x7b]
+ vminmaxph xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxph xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x07,0x52,0xf0,0x7b]
+ vminmaxph xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxph xmm22 {k7} {z}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x87,0x52,0xf0,0x7b]
+ vminmaxph xmm22 {k7} {z}, xmm23, xmm24, 123
+
+// CHECK: vminmaxph zmm22, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x40,0x52,0xf0,0x7b]
+ vminmaxph zmm22, zmm23, zmm24, 123
+
+// CHECK: vminmaxph zmm22, zmm23, zmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x10,0x52,0xf0,0x7b]
+ vminmaxph zmm22, zmm23, zmm24, {sae}, 123
+
+// CHECK: vminmaxph zmm22 {k7}, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x47,0x52,0xf0,0x7b]
+ vminmaxph zmm22 {k7}, zmm23, zmm24, 123
+
+// CHECK: vminmaxph zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x97,0x52,0xf0,0x7b]
+ vminmaxph zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+
+// CHECK: vminmaxph ymm22, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x20,0x52,0xf0,0x7b]
+ vminmaxph ymm22, ymm23, ymm24, 123
+
+// CHECK: vminmaxph ymm22, ymm23, ymm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x40,0x10,0x52,0xf0,0x7b]
+ vminmaxph ymm22, ymm23, ymm24, {sae}, 123
+
+// CHECK: vminmaxph ymm22 {k7}, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x27,0x52,0xf0,0x7b]
+ vminmaxph ymm22 {k7}, ymm23, ymm24, 123
+
+// CHECK: vminmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x40,0x97,0x52,0xf0,0x7b]
+ vminmaxph ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+
+// CHECK: vminmaxph ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x44,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxph ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x44,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxph ymm22, ymm23, word ptr [rip]{1to16}, 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxph ymm22, ymm23, word ptr [rip]{1to16}, 123
+
+// CHECK: vminmaxph ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxph ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+
+// CHECK: vminmaxph ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxph ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+
+// CHECK: vminmaxph ymm22 {k7} {z}, ymm23, word ptr [rdx - 256]{1to16}, 123
+// CHECK: encoding: [0x62,0xe3,0x44,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxph ymm22 {k7} {z}, ymm23, word ptr [rdx - 256]{1to16}, 123
+
+// CHECK: vminmaxph xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x44,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxph xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x44,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxph xmm22, xmm23, word ptr [rip]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxph xmm22, xmm23, word ptr [rip]{1to8}, 123
+
+// CHECK: vminmaxph xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxph xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vminmaxph xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxph xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vminmaxph xmm22 {k7} {z}, xmm23, word ptr [rdx - 256]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxph xmm22 {k7} {z}, xmm23, word ptr [rdx - 256]{1to8}, 123
+
+// CHECK: vminmaxph zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x44,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxph zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxph zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x44,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxph zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxph zmm22, zmm23, word ptr [rip]{1to32}, 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxph zmm22, zmm23, word ptr [rip]{1to32}, 123
+
+// CHECK: vminmaxph zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxph zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+
+// CHECK: vminmaxph zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxph zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+
+// CHECK: vminmaxph zmm22 {k7} {z}, zmm23, word ptr [rdx - 256]{1to32}, 123
+// CHECK: encoding: [0x62,0xe3,0x44,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxph zmm22 {k7} {z}, zmm23, word ptr [rdx - 256]{1to32}, 123
+
+// CHECK: vminmaxps xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x00,0x52,0xf0,0x7b]
+ vminmaxps xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxps xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x07,0x52,0xf0,0x7b]
+ vminmaxps xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxps xmm22 {k7} {z}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x87,0x52,0xf0,0x7b]
+ vminmaxps xmm22 {k7} {z}, xmm23, xmm24, 123
+
+// CHECK: vminmaxps zmm22, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x40,0x52,0xf0,0x7b]
+ vminmaxps zmm22, zmm23, zmm24, 123
+
+// CHECK: vminmaxps zmm22, zmm23, zmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x10,0x52,0xf0,0x7b]
+ vminmaxps zmm22, zmm23, zmm24, {sae}, 123
+
+// CHECK: vminmaxps zmm22 {k7}, zmm23, zmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x47,0x52,0xf0,0x7b]
+ vminmaxps zmm22 {k7}, zmm23, zmm24, 123
+
+// CHECK: vminmaxps zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x97,0x52,0xf0,0x7b]
+ vminmaxps zmm22 {k7} {z}, zmm23, zmm24, {sae}, 123
+
+// CHECK: vminmaxps ymm22, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x20,0x52,0xf0,0x7b]
+ vminmaxps ymm22, ymm23, ymm24, 123
+
+// CHECK: vminmaxps ymm22, ymm23, ymm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x41,0x10,0x52,0xf0,0x7b]
+ vminmaxps ymm22, ymm23, ymm24, {sae}, 123
+
+// CHECK: vminmaxps ymm22 {k7}, ymm23, ymm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x27,0x52,0xf0,0x7b]
+ vminmaxps ymm22 {k7}, ymm23, ymm24, 123
+
+// CHECK: vminmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x41,0x97,0x52,0xf0,0x7b]
+ vminmaxps ymm22 {k7} {z}, ymm23, ymm24, {sae}, 123
+
+// CHECK: vminmaxps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x45,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxps ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x45,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxps ymm22, ymm23, dword ptr [rip]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x30,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxps ymm22, ymm23, dword ptr [rip]{1to8}, 123
+
+// CHECK: vminmaxps ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff,0x7b]
+ vminmaxps ymm22, ymm23, ymmword ptr [2*rbp - 1024], 123
+
+// CHECK: vminmaxps ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0xa7,0x52,0x71,0x7f,0x7b]
+ vminmaxps ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064], 123
+
+// CHECK: vminmaxps ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}, 123
+// CHECK: encoding: [0x62,0xe3,0x45,0xb7,0x52,0x72,0x80,0x7b]
+ vminmaxps ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8}, 123
+
+// CHECK: vminmaxps xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x45,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxps xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x45,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxps xmm22, xmm23, dword ptr [rip]{1to4}, 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x10,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxps xmm22, xmm23, dword ptr [rip]{1to4}, 123
+
+// CHECK: vminmaxps xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff,0x7b]
+ vminmaxps xmm22, xmm23, xmmword ptr [2*rbp - 512], 123
+
+// CHECK: vminmaxps xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x87,0x52,0x71,0x7f,0x7b]
+ vminmaxps xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032], 123
+
+// CHECK: vminmaxps xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}, 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x97,0x52,0x72,0x80,0x7b]
+ vminmaxps xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4}, 123
+
+// CHECK: vminmaxps zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x45,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxps zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxps zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x45,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxps zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxps zmm22, zmm23, dword ptr [rip]{1to16}, 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x50,0x52,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxps zmm22, zmm23, dword ptr [rip]{1to16}, 123
+
+// CHECK: vminmaxps zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff,0x7b]
+ vminmaxps zmm22, zmm23, zmmword ptr [2*rbp - 2048], 123
+
+// CHECK: vminmaxps zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0xc7,0x52,0x71,0x7f,0x7b]
+ vminmaxps zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128], 123
+
+// CHECK: vminmaxps zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}, 123
+// CHECK: encoding: [0x62,0xe3,0x45,0xd7,0x52,0x72,0x80,0x7b]
+ vminmaxps zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16}, 123
+
+// CHECK: vminmaxsd xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x00,0x53,0xf0,0x7b]
+ vminmaxsd xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxsd xmm22, xmm23, xmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x10,0x53,0xf0,0x7b]
+ vminmaxsd xmm22, xmm23, xmm24, {sae}, 123
+
+// CHECK: vminmaxsd xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x07,0x53,0xf0,0x7b]
+ vminmaxsd xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxsd xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0xc5,0x97,0x53,0xf0,0x7b]
+ vminmaxsd xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+
+// CHECK: vminmaxsd xmm22, xmm23, qword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0xc5,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsd xmm22, xmm23, qword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxsd xmm22 {k7}, xmm23, qword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0xc5,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsd xmm22 {k7}, xmm23, qword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxsd xmm22, xmm23, qword ptr [rip], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxsd xmm22, xmm23, qword ptr [rip], 123
+
+// CHECK: vminmaxsd xmm22, xmm23, qword ptr [2*rbp - 256], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x00,0x53,0x34,0x6d,0x00,0xff,0xff,0xff,0x7b]
+ vminmaxsd xmm22, xmm23, qword ptr [2*rbp - 256], 123
+
+// CHECK: vminmaxsd xmm22 {k7} {z}, xmm23, qword ptr [rcx + 1016], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x87,0x53,0x71,0x7f,0x7b]
+ vminmaxsd xmm22 {k7} {z}, xmm23, qword ptr [rcx + 1016], 123
+
+// CHECK: vminmaxsd xmm22 {k7} {z}, xmm23, qword ptr [rdx - 1024], 123
+// CHECK: encoding: [0x62,0xe3,0xc5,0x87,0x53,0x72,0x80,0x7b]
+ vminmaxsd xmm22 {k7} {z}, xmm23, qword ptr [rdx - 1024], 123
+
+// CHECK: vminmaxsh xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x00,0x53,0xf0,0x7b]
+ vminmaxsh xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxsh xmm22, xmm23, xmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x10,0x53,0xf0,0x7b]
+ vminmaxsh xmm22, xmm23, xmm24, {sae}, 123
+
+// CHECK: vminmaxsh xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x07,0x53,0xf0,0x7b]
+ vminmaxsh xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxsh xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x44,0x97,0x53,0xf0,0x7b]
+ vminmaxsh xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+
+// CHECK: vminmaxsh xmm22, xmm23, word ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x44,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxsh xmm22, xmm23, word ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxsh xmm22 {k7}, xmm23, word ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x44,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxsh xmm22 {k7}, xmm23, word ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxsh xmm22, xmm23, word ptr [rip], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxsh xmm22, xmm23, word ptr [rip], 123
+
+// CHECK: vminmaxsh xmm22, xmm23, word ptr [2*rbp - 64], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x00,0x53,0x34,0x6d,0xc0,0xff,0xff,0xff,0x7b]
+ vminmaxsh xmm22, xmm23, word ptr [2*rbp - 64], 123
+
+// CHECK: vminmaxsh xmm22 {k7} {z}, xmm23, word ptr [rcx + 254], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x87,0x53,0x71,0x7f,0x7b]
+ vminmaxsh xmm22 {k7} {z}, xmm23, word ptr [rcx + 254], 123
+
+// CHECK: vminmaxsh xmm22 {k7} {z}, xmm23, word ptr [rdx - 256], 123
+// CHECK: encoding: [0x62,0xe3,0x44,0x87,0x53,0x72,0x80,0x7b]
+ vminmaxsh xmm22 {k7} {z}, xmm23, word ptr [rdx - 256], 123
+
+// CHECK: vminmaxss xmm22, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x00,0x53,0xf0,0x7b]
+ vminmaxss xmm22, xmm23, xmm24, 123
+
+// CHECK: vminmaxss xmm22, xmm23, xmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x10,0x53,0xf0,0x7b]
+ vminmaxss xmm22, xmm23, xmm24, {sae}, 123
+
+// CHECK: vminmaxss xmm22 {k7}, xmm23, xmm24, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x07,0x53,0xf0,0x7b]
+ vminmaxss xmm22 {k7}, xmm23, xmm24, 123
+
+// CHECK: vminmaxss xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+// CHECK: encoding: [0x62,0x83,0x45,0x97,0x53,0xf0,0x7b]
+ vminmaxss xmm22 {k7} {z}, xmm23, xmm24, {sae}, 123
+
+// CHECK: vminmaxss xmm22, xmm23, dword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0x62,0xa3,0x45,0x00,0x53,0xb4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+ vminmaxss xmm22, xmm23, dword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vminmaxss xmm22 {k7}, xmm23, dword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0x62,0xc3,0x45,0x07,0x53,0xb4,0x80,0x23,0x01,0x00,0x00,0x7b]
+ vminmaxss xmm22 {k7}, xmm23, dword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vminmaxss xmm22, xmm23, dword ptr [rip], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x00,0x53,0x35,0x00,0x00,0x00,0x00,0x7b]
+ vminmaxss xmm22, xmm23, dword ptr [rip], 123
+
+// CHECK: vminmaxss xmm22, xmm23, dword ptr [2*rbp - 128], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x00,0x53,0x34,0x6d,0x80,0xff,0xff,0xff,0x7b]
+ vminmaxss xmm22, xmm23, dword ptr [2*rbp - 128], 123
+
+// CHECK: vminmaxss xmm22 {k7} {z}, xmm23, dword ptr [rcx + 508], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x87,0x53,0x71,0x7f,0x7b]
+ vminmaxss xmm22 {k7} {z}, xmm23, dword ptr [rcx + 508], 123
+
+// CHECK: vminmaxss xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512], 123
+// CHECK: encoding: [0x62,0xe3,0x45,0x87,0x53,0x72,0x80,0x7b]
+ vminmaxss xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512], 123
+
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index f31c4baada141..e85cde3140594 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -2822,6 +2822,21 @@ static const X86FoldTableEntry Table2[] = {
{X86::VMINCSHZrr, X86::VMINCSHZrm, 0},
{X86::VMINCSSZrr, X86::VMINCSSZrm, 0},
{X86::VMINCSSrr, X86::VMINCSSrm, 0},
+ {X86::VMINMAXNEPBF16Z128rri, X86::VMINMAXNEPBF16Z128rmi, 0},
+ {X86::VMINMAXNEPBF16Z256rri, X86::VMINMAXNEPBF16Z256rmi, 0},
+ {X86::VMINMAXNEPBF16Zrri, X86::VMINMAXNEPBF16Zrmi, 0},
+ {X86::VMINMAXPDZ128rri, X86::VMINMAXPDZ128rmi, 0},
+ {X86::VMINMAXPDZ256rri, X86::VMINMAXPDZ256rmi, 0},
+ {X86::VMINMAXPDZrri, X86::VMINMAXPDZrmi, 0},
+ {X86::VMINMAXPHZ128rri, X86::VMINMAXPHZ128rmi, 0},
+ {X86::VMINMAXPHZ256rri, X86::VMINMAXPHZ256rmi, 0},
+ {X86::VMINMAXPHZrri, X86::VMINMAXPHZrmi, 0},
+ {X86::VMINMAXPSZ128rri, X86::VMINMAXPSZ128rmi, 0},
+ {X86::VMINMAXPSZ256rri, X86::VMINMAXPSZ256rmi, 0},
+ {X86::VMINMAXPSZrri, X86::VMINMAXPSZrmi, 0},
+ {X86::VMINMAXSDrri, X86::VMINMAXSDrmi, TB_NO_REVERSE},
+ {X86::VMINMAXSHrri, X86::VMINMAXSHrmi, TB_NO_REVERSE},
+ {X86::VMINMAXSSrri, X86::VMINMAXSSrmi, TB_NO_REVERSE},
{X86::VMINPDYrr, X86::VMINPDYrm, 0},
{X86::VMINPDZ128rr, X86::VMINPDZ128rm, 0},
{X86::VMINPDZ256rr, X86::VMINPDZ256rm, 0},
@@ -4661,6 +4676,21 @@ static const X86FoldTableEntry Table3[] = {
{X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmkz, 0},
{X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmkz, 0},
{X86::VMINCPSZrrkz, X86::VMINCPSZrmkz, 0},
+ {X86::VMINMAXNEPBF16Z128rrikz, X86::VMINMAXNEPBF16Z128rmikz, 0},
+ {X86::VMINMAXNEPBF16Z256rrikz, X86::VMINMAXNEPBF16Z256rmikz, 0},
+ {X86::VMINMAXNEPBF16Zrrikz, X86::VMINMAXNEPBF16Zrmikz, 0},
+ {X86::VMINMAXPDZ128rrikz, X86::VMINMAXPDZ128rmikz, 0},
+ {X86::VMINMAXPDZ256rrikz, X86::VMINMAXPDZ256rmikz, 0},
+ {X86::VMINMAXPDZrrikz, X86::VMINMAXPDZrmikz, 0},
+ {X86::VMINMAXPHZ128rrikz, X86::VMINMAXPHZ128rmikz, 0},
+ {X86::VMINMAXPHZ256rrikz, X86::VMINMAXPHZ256rmikz, 0},
+ {X86::VMINMAXPHZrrikz, X86::VMINMAXPHZrmikz, 0},
+ {X86::VMINMAXPSZ128rrikz, X86::VMINMAXPSZ128rmikz, 0},
+ {X86::VMINMAXPSZ256rrikz, X86::VMINMAXPSZ256rmikz, 0},
+ {X86::VMINMAXPSZrrikz, X86::VMINMAXPSZrmikz, 0},
+ {X86::VMINMAXSDrrikz, X86::VMINMAXSDrmikz, TB_NO_REVERSE},
+ {X86::VMINMAXSHrrikz, X86::VMINMAXSHrmikz, TB_NO_REVERSE},
+ {X86::VMINMAXSSrrikz, X86::VMINMAXSSrmikz, TB_NO_REVERSE},
{X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0},
{X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0},
{X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0},
@@ -6091,6 +6121,21 @@ static const X86FoldTableEntry Table4[] = {
{X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmk, 0},
{X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmk, 0},
{X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0},
+ {X86::VMINMAXNEPBF16Z128rrik, X86::VMINMAXNEPBF16Z128rmik, 0},
+ {X86::VMINMAXNEPBF16Z256rrik, X86::VMINMAXNEPBF16Z256rmik, 0},
+ {X86::VMINMAXNEPBF16Zrrik, X86::VMINMAXNEPBF16Zrmik, 0},
+ {X86::VMINMAXPDZ128rrik, X86::VMINMAXPDZ128rmik, 0},
+ {X86::VMINMAXPDZ256rrik, X86::VMINMAXPDZ256rmik, 0},
+ {X86::VMINMAXPDZrrik, X86::VMINMAXPDZrmik, 0},
+ {X86::VMINMAXPHZ128rrik, X86::VMINMAXPHZ128rmik, 0},
+ {X86::VMINMAXPHZ256rrik, X86::VMINMAXPHZ256rmik, 0},
+ {X86::VMINMAXPHZrrik, X86::VMINMAXPHZrmik, 0},
+ {X86::VMINMAXPSZ128rrik, X86::VMINMAXPSZ128rmik, 0},
+ {X86::VMINMAXPSZ256rrik, X86::VMINMAXPSZ256rmik, 0},
+ {X86::VMINMAXPSZrrik, X86::VMINMAXPSZrmik, 0},
+ {X86::VMINMAXSDrrik, X86::VMINMAXSDrmik, TB_NO_REVERSE},
+ {X86::VMINMAXSHrrik, X86::VMINMAXSHrmik, TB_NO_REVERSE},
+ {X86::VMINMAXSSrrik, X86::VMINMAXSSrmik, TB_NO_REVERSE},
{X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0},
{X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0},
{X86::VMINPDZrrk, X86::VMINPDZrmk, 0},
@@ -7235,6 +7280,18 @@ static const X86FoldTableEntry BroadcastTable2[] = {
{X86::VMINCPSZ128rr, X86::VMINCPSZ128rmb, TB_BCAST_SS},
{X86::VMINCPSZ256rr, X86::VMINCPSZ256rmb, TB_BCAST_SS},
{X86::VMINCPSZrr, X86::VMINCPSZrmb, TB_BCAST_SS},
+ {X86::VMINMAXNEPBF16Z128rri, X86::VMINMAXNEPBF16Z128rmbi, TB_BCAST_SH},
+ {X86::VMINMAXNEPBF16Z256rri, X86::VMINMAXNEPBF16Z256rmbi, TB_BCAST_SH},
+ {X86::VMINMAXNEPBF16Zrri, X86::VMINMAXNEPBF16Zrmbi, TB_BCAST_SH},
+ {X86::VMINMAXPDZ128rri, X86::VMINMAXPDZ128rmbi, TB_BCAST_SD},
+ {X86::VMINMAXPDZ256rri, X86::VMINMAXPDZ256rmbi, TB_BCAST_SD},
+ {X86::VMINMAXPDZrri, X86::VMINMAXPDZrmbi, TB_BCAST_SD},
+ {X86::VMINMAXPHZ128rri, X86::VMINMAXPHZ128rmbi, TB_BCAST_SH},
+ {X86::VMINMAXPHZ256rri, X86::VMINMAXPHZ256rmbi, TB_BCAST_SH},
+ {X86::VMINMAXPHZrri, X86::VMINMAXPHZrmbi, TB_BCAST_SH},
+ {X86::VMINMAXPSZ128rri, X86::VMINMAXPSZ128rmbi, TB_BCAST_SS},
+ {X86::VMINMAXPSZ256rri, X86::VMINMAXPSZ256rmbi, TB_BCAST_SS},
+ {X86::VMINMAXPSZrri, X86::VMINMAXPSZrmbi, TB_BCAST_SS},
{X86::VMINPDZ128rr, X86::VMINPDZ128rmb, TB_BCAST_SD},
{X86::VMINPDZ256rr, X86::VMINPDZ256rmb, TB_BCAST_SD},
{X86::VMINPDZrr, X86::VMINPDZrmb, TB_BCAST_SD},
@@ -8068,6 +8125,18 @@ static const X86FoldTableEntry BroadcastTable3[] = {
{X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmbkz, TB_BCAST_SS},
{X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmbkz, TB_BCAST_SS},
{X86::VMINCPSZrrkz, X86::VMINCPSZrmbkz, TB_BCAST_SS},
+ {X86::VMINMAXNEPBF16Z128rrikz, X86::VMINMAXNEPBF16Z128rmbikz, TB_BCAST_SH},
+ {X86::VMINMAXNEPBF16Z256rrikz, X86::VMINMAXNEPBF16Z256rmbikz, TB_BCAST_SH},
+ {X86::VMINMAXNEPBF16Zrrikz, X86::VMINMAXNEPBF16Zrmbikz, TB_BCAST_SH},
+ {X86::VMINMAXPDZ128rrikz, X86::VMINMAXPDZ128rmbikz, TB_BCAST_SD},
+ {X86::VMINMAXPDZ256rrikz, X86::VMINMAXPDZ256rmbikz, TB_BCAST_SD},
+ {X86::VMINMAXPDZrrikz, X86::VMINMAXPDZrmbikz, TB_BCAST_SD},
+ {X86::VMINMAXPHZ128rrikz, X86::VMINMAXPHZ128rmbikz, TB_BCAST_SH},
+ {X86::VMINMAXPHZ256rrikz, X86::VMINMAXPHZ256rmbikz, TB_BCAST_SH},
+ {X86::VMINMAXPHZrrikz, X86::VMINMAXPHZrmbikz, TB_BCAST_SH},
+ {X86::VMINMAXPSZ128rrikz, X86::VMINMAXPSZ128rmbikz, TB_BCAST_SS},
+ {X86::VMINMAXPSZ256rrikz, X86::VMINMAXPSZ256rmbikz, TB_BCAST_SS},
+ {X86::VMINMAXPSZrrikz, X86::VMINMAXPSZrmbikz, TB_BCAST_SS},
{X86::VMINPDZ128rrkz, X86::VMINPDZ128rmbkz, TB_BCAST_SD},
{X86::VMINPDZ256rrkz, X86::VMINPDZ256rmbkz, TB_BCAST_SD},
{X86::VMINPDZrrkz, X86::VMINPDZrmbkz, TB_BCAST_SD},
@@ -8950,6 +9019,18 @@ static const X86FoldTableEntry BroadcastTable4[] = {
{X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmbk, TB_BCAST_SS},
{X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmbk, TB_BCAST_SS},
{X86::VMINCPSZrrk, X86::VMINCPSZrmbk, TB_BCAST_SS},
+ {X86::VMINMAXNEPBF16Z128rrik, X86::VMINMAXNEPBF16Z128rmbik, TB_BCAST_SH},
+ {X86::VMINMAXNEPBF16Z256rrik, X86::VMINMAXNEPBF16Z256rmbik, TB_BCAST_SH},
+ {X86::VMINMAXNEPBF16Zrrik, X86::VMINMAXNEPBF16Zrmbik, TB_BCAST_SH},
+ {X86::VMINMAXPDZ128rrik, X86::VMINMAXPDZ128rmbik, TB_BCAST_SD},
+ {X86::VMINMAXPDZ256rrik, X86::VMINMAXPDZ256rmbik, TB_BCAST_SD},
+ {X86::VMINMAXPDZrrik, X86::VMINMAXPDZrmbik, TB_BCAST_SD},
+ {X86::VMINMAXPHZ128rrik, X86::VMINMAXPHZ128rmbik, TB_BCAST_SH},
+ {X86::VMINMAXPHZ256rrik, X86::VMINMAXPHZ256rmbik, TB_BCAST_SH},
+ {X86::VMINMAXPHZrrik, X86::VMINMAXPHZrmbik, TB_BCAST_SH},
+ {X86::VMINMAXPSZ128rrik, X86::VMINMAXPSZ128rmbik, TB_BCAST_SS},
+ {X86::VMINMAXPSZ256rrik, X86::VMINMAXPSZ256rmbik, TB_BCAST_SS},
+ {X86::VMINMAXPSZrrik, X86::VMINMAXPSZrmbik, TB_BCAST_SS},
{X86::VMINPDZ128rrk, X86::VMINPDZ128rmbk, TB_BCAST_SD},
{X86::VMINPDZ256rrk, X86::VMINPDZ256rmbk, TB_BCAST_SD},
{X86::VMINPDZrrk, X86::VMINPDZrmbk, TB_BCAST_SD},
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