[clang] [compiler-rt] [llvm] [RISCV] Support new groupid/bitmask for cpu_model (PR #101632)

[Craig Topper via cfe-commits]

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@@ -80,10 +80,14 @@ class RISCVISAInfo {
                                      std::set<StringRef> &EnabledFeatureNames,
                                      StringMap<StringRef> &DescMap);
 
-  /// Return the bit position (in group 0) of __riscv_feature_bits.  Returns
+  /// Return the bit position of __riscv_feature_bits.  Returns
   /// -1 if not supported.
   static int getRISCVFeaturesBitPosition(StringRef Ext);
 
+  /// Return the group id of __riscv_feature_bits.  Returns
+  /// -1 if not supported.
+  static int getRISCVFeaturesGroupID(StringRef Ext);
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topperc wrote:

Can we merge this into getRISCVFeaturesBitPosition by returning a std::pair? This way we only have to search the table one time.

https://github.com/llvm/llvm-project/pull/101632