[libunwind] [RISCV] Allow libunwind to build for rv32e (PR #98855)

[via cfe-commits]

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@@ -1169,7 +1169,11 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_riscv6jumptoEv)
     ILOAD x\i, (RISCV_ISIZE * \i)(a0)
   .endr
   // skip a0 for now
+#if defined(__riscv_abi_rve)
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ArcaneNibble wrote:

In general, libunwind seems to be somewhat inconsistent with when it checks ISA vs ABI defines?

* i386 doesn't touch any FPU registers at all. not sure what happens if `vectorcall` gets involved?
* x86_64 only restores XMM registers for `_WIN64` which is an ABI-related define
* PPC32/PPC64 checks `__VSX__`/`__NO_FPRS__`/`__ALTIVEC__` which are ISA-related defines
* ARM has its own special unique logic for handling FPU registers involving runtime flags
* MIPS checks `__mips_hard_float` which is an ABI-related define but also `__mips_isa_rev` which is an ISA-related define
* SPARC has separate functions for two different ABIs
* RISC-V checks `__riscv_flen` which is an ISA-related define
* LoongArch checks `__loongarch_frlen` which is an ISA-related define
* aarch64/or1k/hexagon/s390x do not have any variations to handle

https://github.com/llvm/llvm-project/pull/98855