[clang] [Clang][AArch64] Add customisable immediate range checking to NEON (PR #100278)
via cfe-commits
cfe-commits at lists.llvm.org
Tue Jul 23 16:22:09 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
@llvm/pr-subscribers-clang
Author: None (SpencerAbson)
<details>
<summary>Changes</summary>
This patch moves NEON immediate argument specification and checking to the system currently shared by both SVE and SME. As a result, NEON instructions that take immediate arguments must specify the type of range check to be completed (E.g ImmCheckShiftRight), the parameter index of the immediate argument that should be verified against this check, and, in cases where the base type of the builtin is not determined by a call to an overloaded function (such as for [vdup_lane](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@<!-- -->navigationhierarchiessimdisa=[Neon]&q=vdup_lane)), the index of the argument that should define the base type for this immediate check (0 in this case). Though an effort has been made to supply this final argument in most cases either way.
This patch also adds immediate range-checking tests for VCMLA (Armv8.3 complex number) intrinsics and resolves a discrepancy in the argument range of the [vcmla_laneq_f16](https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=vcmla_laneq_f16) (and rotations) type intrinsic. As a result of this, existing CodeGen tests for vcmla intrinsics that violated this immediate range have had to be rectified.
---
Patch is 132.32 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/100278.diff
12 Files Affected:
- (modified) clang/include/clang/Basic/TargetBuiltins.h (+32-7)
- (modified) clang/include/clang/Basic/arm_fp16.td (+1-1)
- (added) clang/include/clang/Basic/arm_immcheck_incl.td (+39)
- (modified) clang/include/clang/Basic/arm_neon.td (+248-126)
- (modified) clang/include/clang/Basic/arm_neon_incl.td (+7-4)
- (modified) clang/include/clang/Basic/arm_sve_sme_incl.td (+2-34)
- (modified) clang/include/clang/Sema/SemaARM.h (+3)
- (modified) clang/lib/Sema/SemaARM.cpp (+88-63)
- (modified) clang/test/CodeGen/aarch64-neon-vcmla.c (+388-236)
- (added) clang/test/Sema/aarch64-neon-vcmla-ranges.c (+202)
- (modified) clang/utils/TableGen/NeonEmitter.cpp (+50-83)
- (modified) clang/utils/TableGen/SveEmitter.cpp (+1-1)
``````````diff
diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h
index 4333830bf34f2..50e17ad7e1628 100644
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -209,15 +209,45 @@ namespace clang {
Flags |= QuadFlag;
}
- EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
+ EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
bool isPoly() const {
EltType ET = getEltType();
return ET == Poly8 || ET == Poly16 || ET == Poly64;
}
bool isUnsigned() const { return (Flags & UnsignedFlag) != 0; }
- bool isQuad() const { return (Flags & QuadFlag) != 0; }
+ bool isQuad() const { return (Flags & QuadFlag) != 0; };
+ unsigned getEltSizeInBits() const {
+ switch(getEltType()){
+ case Int8:
+ case Poly8:
+ return 8;
+ case Int16:
+ case Float16:
+ case Poly16:
+ case BFloat16:
+ return 16;
+ case Int32:
+ case Float32:
+ return 32;
+ case Int64:
+ case Float64:
+ case Poly64:
+ return 64;
+ case Poly128:
+ return 128;
+ default:
+ llvm_unreachable("Invalid NeonTypeFlag!");
+ }
+ }
};
+ // Shared between SVE/SME and NEON
+ enum ArmImmCheckType {
+#define LLVM_GET_ARM_INTRIN_IMMCHECKTYPES
+#include "clang/Basic/arm_sve_typeflags.inc"
+#undef LLVM_GET_ARM_INTRIN_IMMCHECKTYPES
+ };
+
/// Flags to identify the types for overloaded SVE builtins.
class SVETypeFlags {
uint64_t Flags;
@@ -249,11 +279,6 @@ namespace clang {
#undef LLVM_GET_SVE_MERGETYPES
};
- enum ImmCheckType {
-#define LLVM_GET_SVE_IMMCHECKTYPES
-#include "clang/Basic/arm_sve_typeflags.inc"
-#undef LLVM_GET_SVE_IMMCHECKTYPES
- };
SVETypeFlags(uint64_t F) : Flags(F) {
EltTypeShift = llvm::countr_zero(EltTypeMask);
diff --git a/clang/include/clang/Basic/arm_fp16.td b/clang/include/clang/Basic/arm_fp16.td
index d36b4617bef5d..42228a3ba1ffa 100644
--- a/clang/include/clang/Basic/arm_fp16.td
+++ b/clang/include/clang/Basic/arm_fp16.td
@@ -76,7 +76,7 @@ let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)", TargetGuard = "f
def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "(1U)1", "Sh">;
def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "(1U>)1", "Sh">;
def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "(1U>>)1", "Sh">;
- let isVCVT_N = 1 in {
+ let isVCVT_N = 1, ImmChecks = [ImmCheck<1, ImmCheck1_16>] in {
def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "(1F)(1!)I", "sUs">;
def SCALAR_SCVTFSH1O: SInst<"vcvth_n_f16", "(1F<)(1!)I", "iUi">;
def SCALAR_SCVTFSH2O: SInst<"vcvth_n_f16", "(1F<<)(1!)I", "lUl">;
diff --git a/clang/include/clang/Basic/arm_immcheck_incl.td b/clang/include/clang/Basic/arm_immcheck_incl.td
new file mode 100644
index 0000000000000..3b20248f65040
--- /dev/null
+++ b/clang/include/clang/Basic/arm_immcheck_incl.td
@@ -0,0 +1,39 @@
+class ImmCheckType<int val> {
+ int Value = val;
+}
+
+// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
+def ImmCheck0_31 : ImmCheckType<0>; // 0..31 (used for e.g. predicate patterns)
+def ImmCheck1_16 : ImmCheckType<1>; // 1..16
+def ImmCheckExtract : ImmCheckType<2>; // 0..(2048/sizeinbits(elt) - 1)
+def ImmCheckShiftRight : ImmCheckType<3>; // 1..sizeinbits(elt)
+def ImmCheckShiftRightNarrow : ImmCheckType<4>; // 1..sizeinbits(elt)/2
+def ImmCheckShiftLeft : ImmCheckType<5>; // 0..(sizeinbits(elt) - 1)
+def ImmCheck0_7 : ImmCheckType<6>; // 0..7
+def ImmCheckLaneIndex : ImmCheckType<7>; // 0..(128/(1*sizeinbits(elt)) - 1)
+def ImmCheckLaneQIndex : ImmCheckType<8>; // (Neon) treat type as Quad
+def ImmCheckLaneIndexCompRotate : ImmCheckType<9>; // 0..(128/(2*sizeinbits(elt)) - 1)
+def ImmCheckLaneIndexDot : ImmCheckType<10>; // 0..(128/(4*sizeinbits(elt)) - 1)
+def ImmCheckComplexRot90_270 : ImmCheckType<11>; // [90,270]
+def ImmCheckComplexRotAll90 : ImmCheckType<12>; // [0, 90, 180,270]
+def ImmCheck0_13 : ImmCheckType<13>; // 0..13
+def ImmCheck0_1 : ImmCheckType<14>; // 0..1
+def ImmCheck0_2 : ImmCheckType<15>; // 0..2
+def ImmCheck0_3 : ImmCheckType<16>; // 0..3
+def ImmCheck0_0 : ImmCheckType<17>; // 0..0
+def ImmCheck0_15 : ImmCheckType<18>; // 0..15
+def ImmCheck0_255 : ImmCheckType<19>; // 0..255
+def ImmCheck2_4_Mul2 : ImmCheckType<20>; // 2, 4
+def ImmCheck1_1 : ImmCheckType<21>; // 1..1
+def ImmCheck1_3 : ImmCheckType<22>; // 1..3
+def ImmCheck1_7 : ImmCheckType<23>; // 1..7
+def ImmCheck1_32 : ImmCheckType<24>; // 1..32
+def ImmCheck1_64 : ImmCheckType<25>; // 1..64
+def ImmCheck0_63 : ImmCheckType<26>; // 0..63
+
+class ImmCheck<int arg, ImmCheckType kind, int eltSizeArg = -1> {
+ int Arg = arg;
+ // The index of the argument whose type should be referred to when validating this immedaite.
+ int EltSizeArg = eltSizeArg;
+ ImmCheckType Kind = kind;
+}
diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td
index 3098fa67e6a51..ee823f6ef6813 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -284,14 +284,18 @@ def OP_CVT_F32_BF16
// Splat operation - performs a range-checked splat over a vector
def SPLAT : WInst<"splat_lane", ".(!q)I",
- "UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl">;
+ "UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl",
+ [ImmCheck<1, ImmCheckLaneIndex, 0>]>;
def SPLATQ : WInst<"splat_laneq", ".(!Q)I",
- "UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
+ "UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl",
+ [ImmCheck<1, ImmCheckLaneQIndex, 1>]> {
let isLaneQ = 1;
}
let TargetGuard = "bf16,neon" in {
- def SPLAT_BF : WInst<"splat_lane", ".(!q)I", "bQb">;
- def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
+ def SPLAT_BF : WInst<"splat_lane", ".(!q)I", "bQb",
+ [ImmCheck<1, ImmCheckLaneIndex, 0>]>;
+ def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb",
+ [ImmCheck<1, ImmCheckLaneQIndex, 1>]> {
let isLaneQ = 1;
}
}
@@ -401,27 +405,45 @@ def VQRSHL : SInst<"vqrshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
////////////////////////////////////////////////////////////////////////////////
// E.3.12 Shifts by constant
let isShift = 1 in {
-def VSHR_N : SInst<"vshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VSHL_N : IInst<"vshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VRSHR_N : SInst<"vrshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VSRA_N : SInst<"vsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VRSRA_N : SInst<"vrsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VQSHL_N : SInst<"vqshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">;
-def VQSHLU_N : SInst<"vqshlu_n", "U.I", "csilQcQsQiQl">;
-def VSHRN_N : IInst<"vshrn_n", "<QI", "silUsUiUl">;
-def VQSHRUN_N : SInst<"vqshrun_n", "(<U)QI", "sil">;
-def VQRSHRUN_N : SInst<"vqrshrun_n", "(<U)QI", "sil">;
-def VQSHRN_N : SInst<"vqshrn_n", "<QI", "silUsUiUl">;
-def VRSHRN_N : IInst<"vrshrn_n", "<QI", "silUsUiUl">;
-def VQRSHRN_N : SInst<"vqrshrn_n", "<QI", "silUsUiUl">;
-def VSHLL_N : SInst<"vshll_n", "(>Q).I", "csiUcUsUi">;
+
+
+def VSHR_N : SInst<"vshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VSHL_N : IInst<"vshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl",
+ [ImmCheck<1, ImmCheckShiftLeft>]>;
+def VRSHR_N : SInst<"vrshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VSRA_N : SInst<"vsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl",
+ [ImmCheck<2, ImmCheckShiftRight>]>;
+def VRSRA_N : SInst<"vrsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl",
+ [ImmCheck<2, ImmCheckShiftRight>]>;
+def VQSHL_N : SInst<"vqshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl",
+ [ImmCheck<1, ImmCheckShiftLeft>]>;
+def VQSHLU_N : SInst<"vqshlu_n", "U.I", "csilQcQsQiQl",
+ [ImmCheck<1, ImmCheckShiftLeft>]>;
+def VSHRN_N : IInst<"vshrn_n", "<QI", "silUsUiUl",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VQSHRUN_N : SInst<"vqshrun_n", "(<U)QI", "sil",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VQRSHRUN_N : SInst<"vqrshrun_n", "(<U)QI", "sil",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VQSHRN_N : SInst<"vqshrn_n", "<QI", "silUsUiUl",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VRSHRN_N : IInst<"vrshrn_n", "<QI", "silUsUiUl",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VQRSHRN_N : SInst<"vqrshrn_n", "<QI", "silUsUiUl",
+ [ImmCheck<1, ImmCheckShiftRight>]>;
+def VSHLL_N : SInst<"vshll_n", "(>Q).I", "csiUcUsUi",
+ [ImmCheck<1, ImmCheckShiftLeft>]>;
////////////////////////////////////////////////////////////////////////////////
// E.3.13 Shifts with insert
def VSRI_N : WInst<"vsri_n", "...I",
- "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+ "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs",
+ [ImmCheck<2, ImmCheckShiftRight>]>;
def VSLI_N : WInst<"vsli_n", "...I",
- "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">;
+ "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs",
+ [ImmCheck<2, ImmCheckShiftLeft>]>;
}
////////////////////////////////////////////////////////////////////////////////
@@ -435,7 +457,8 @@ def VLD1_X3 : WInst<"vld1_x3", "3(c*!)",
def VLD1_X4 : WInst<"vld1_x4", "4(c*!)",
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
def VLD1_LANE : WInst<"vld1_lane", ".(c*!).I",
- "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
+ "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs",
+ [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
def VLD1_DUP : WInst<"vld1_dup", ".(c*!)",
"QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
def VST1 : WInst<"vst1", "v*(.!)",
@@ -447,19 +470,23 @@ def VST1_X3 : WInst<"vst1_x3", "v*(3!)",
def VST1_X4 : WInst<"vst1_x4", "v*(4!)",
"cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
def VST1_LANE : WInst<"vst1_lane", "v*(.!)I",
- "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
+ "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs",
+ [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
+
let ArchGuard = "(__ARM_FP & 2)" in {
def VLD1_F16 : WInst<"vld1", ".(c*!)", "hQh">;
def VLD1_X2_F16 : WInst<"vld1_x2", "2(c*!)", "hQh">;
def VLD1_X3_F16 : WInst<"vld1_x3", "3(c*!)", "hQh">;
def VLD1_X4_F16 : WInst<"vld1_x4", "4(c*!)", "hQh">;
-def VLD1_LANE_F16 : WInst<"vld1_lane", ".(c*!).I", "hQh">;
+def VLD1_LANE_F16 : WInst<"vld1_lane", ".(c*!).I", "hQh",
+ [ImmCheck<2, ImmCheck0_3, 1>]>;
def VLD1_DUP_F16 : WInst<"vld1_dup", ".(c*!)", "hQh">;
def VST1_F16 : WInst<"vst1", "v*(.!)", "hQh">;
def VST1_X2_F16 : WInst<"vst1_x2", "v*(2!)", "hQh">;
def VST1_X3_F16 : WInst<"vst1_x3", "v*(3!)", "hQh">;
def VST1_X4_F16 : WInst<"vst1_x4", "v*(4!)", "hQh">;
-def VST1_LANE_F16 : WInst<"vst1_lane", "v*(.!)I", "hQh">;
+def VST1_LANE_F16 : WInst<"vst1_lane", "v*(.!)I", "hQh",
+ [ImmCheck<2, ImmCheck0_3, 1>]>;
}
////////////////////////////////////////////////////////////////////////////////
@@ -473,15 +500,21 @@ def VLD3_DUP : WInst<"vld3_dup", "3(c*!)",
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
def VLD4_DUP : WInst<"vld4_dup", "4(c*!)",
"UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
-def VLD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
-def VLD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
-def VLD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
+def VLD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
+ [ImmCheck<4, ImmCheckLaneIndex, 1>]>;
+def VLD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
+ [ImmCheck<5, ImmCheckLaneIndex, 1>]>;
+def VLD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
+ [ImmCheck<6, ImmCheckLaneIndex, 1>]>;
def VST2 : WInst<"vst2", "v*(2!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
def VST3 : WInst<"vst3", "v*(3!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
def VST4 : WInst<"vst4", "v*(4!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
-def VST2_LANE : WInst<"vst2_lane", "v*(2!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
-def VST3_LANE : WInst<"vst3_lane", "v*(3!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
-def VST4_LANE : WInst<"vst4_lane", "v*(4!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">;
+def VST2_LANE : WInst<"vst2_lane", "v*(2!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
+ [ImmCheck<3, ImmCheckLaneIndex, 1>]>;
+def VST3_LANE : WInst<"vst3_lane", "v*(3!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
+ [ImmCheck<4, ImmCheckLaneIndex, 1>]>;
+def VST4_LANE : WInst<"vst4_lane", "v*(4!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs",
+ [ImmCheck<5, ImmCheckLaneIndex, 1>]>;
let ArchGuard = "(__ARM_FP & 2)" in {
def VLD2_F16 : WInst<"vld2", "2(c*!)", "hQh">;
def VLD3_F16 : WInst<"vld3", "3(c*!)", "hQh">;
@@ -489,28 +522,36 @@ def VLD4_F16 : WInst<"vld4", "4(c*!)", "hQh">;
def VLD2_DUP_F16 : WInst<"vld2_dup", "2(c*!)", "hQh">;
def VLD3_DUP_F16 : WInst<"vld3_dup", "3(c*!)", "hQh">;
def VLD4_DUP_F16 : WInst<"vld4_dup", "4(c*!)", "hQh">;
-def VLD2_LANE_F16 : WInst<"vld2_lane", "2(c*!)2I", "hQh">;
-def VLD3_LANE_F16 : WInst<"vld3_lane", "3(c*!)3I", "hQh">;
-def VLD4_LANE_F16 : WInst<"vld4_lane", "4(c*!)4I", "hQh">;
+def VLD2_LANE_F16 : WInst<"vld2_lane", "2(c*!)2I", "hQh",
+ [ImmCheck<4, ImmCheck0_3, 1>]>;
+def VLD3_LANE_F16 : WInst<"vld3_lane", "3(c*!)3I", "hQh",
+ [ImmCheck<5, ImmCheck0_3, 1>]>;
+def VLD4_LANE_F16 : WInst<"vld4_lane", "4(c*!)4I", "hQh",
+ [ImmCheck<6, ImmCheck0_3, 1>]>;
def VST2_F16 : WInst<"vst2", "v*(2!)", "hQh">;
def VST3_F16 : WInst<"vst3", "v*(3!)", "hQh">;
def VST4_F16 : WInst<"vst4", "v*(4!)", "hQh">;
-def VST2_LANE_F16 : WInst<"vst2_lane", "v*(2!)I", "hQh">;
-def VST3_LANE_F16 : WInst<"vst3_lane", "v*(3!)I", "hQh">;
-def VST4_LANE_F16 : WInst<"vst4_lane", "v*(4!)I", "hQh">;
+def VST2_LANE_F16 : WInst<"vst2_lane", "v*(2!)I", "hQh",
+ [ImmCheck<3, ImmCheck0_3, 1>]>;
+def VST3_LANE_F16 : WInst<"vst3_lane", "v*(3!)I", "hQh",
+ [ImmCheck<4, ImmCheck0_3, 1>]>;
+def VST4_LANE_F16 : WInst<"vst4_lane", "v*(4!)I", "hQh",
+ [ImmCheck<5, ImmCheck0_3, 1>]>;
}
////////////////////////////////////////////////////////////////////////////////
// E.3.16 Extract lanes from a vector
let InstName = "vmov" in
def VGET_LANE : IInst<"vget_lane", "1.I",
- "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+ "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
+ [ImmCheck<1, ImmCheckLaneIndex, 0>]>;
////////////////////////////////////////////////////////////////////////////////
// E.3.17 Set lanes within a vector
let InstName = "vmov" in
def VSET_LANE : IInst<"vset_lane", ".1.I",
- "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">;
+ "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl",
+ [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
////////////////////////////////////////////////////////////////////////////////
// E.3.18 Initialize a vector from bit pattern
@@ -560,9 +601,12 @@ def VCVT_S32 : SInst<"vcvt_s32", "S.", "fQf">;
def VCVT_U32 : SInst<"vcvt_u32", "U.", "fQf">;
def VCVT_F32 : SInst<"vcvt_f32", "F(.!)", "iUiQiQUi">;
let isVCVT_N = 1 in {
-def VCVT_N_S32 : SInst<"vcvt_n_s32", "S.I", "fQf">;
-def VCVT_N_U32 : SInst<"vcvt_n_u32", "U.I", "fQf">;
-def VCVT_N_F32 : SInst<"vcvt_n_f32", "F(.!)I", "iUiQiQUi">;
+def VCVT_N_S32 : SInst<"vcvt_n_s32", "S.I", "fQf",
+ [ImmCheck<1, ImmCheck1_32>]>;
+def VCVT_N_U32 : SInst<"vcvt_n_u32", "U.I", "fQf",
+ [ImmCheck<1, ImmCheck1_32>]>;
+def VCVT_N_F32 : SInst<"vcvt_n_f32", "F(.!)I", "iUiQiQUi",
+ [ImmCheck<1, ImmCheck1_32>]>;
}
def VMOVN : IInst<"vmovn", "<Q", "silUsUiUl">;
@@ -610,8 +654,10 @@ def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>;
def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
}
let ArchGuard = "defined(__aarch64__) || defined(__arm64ec__)" in {
-def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
-def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
+def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi",
+ [ImmCheck<2, ImmCheckLaneIndex, 0>]>;
+def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi",
+ [ImmCheck<2, ImmCheckLaneIndex, 0>]>;
}
let TargetGuard = "v8.1a,neon" in {
@@ -629,7 +675,8 @@ def VQDMLSL_N : SOpInst<"vqdmlsl_n", "(>Q)(>Q).1", "si", OP_QDMLSL_N>;
////////////////////////////////////////////////////////////////////////////////
// E.3.26 Vector Extract
def VEXT : WInst<"vext", "...I",
- "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">;
+ "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf",
+ [ImmCheck<2, ImmCheckLaneIndex, 0>]>;
////////////////////////////////////////////////////////////////////////////////
// E.3.27 Reverse vector elements
@@ -738,14 +785,22 @@ def ST1_X2 : WInst<"vst1_x2", "v*(2!)", "dQdPlQPl">;
def ST1_X3 : WInst<"vst1_x3", "v*(3!)", "dQdPlQPl">;
def ST1_X4 : WInst<"vst1_x4", "v*(4!)", "dQdPlQPl">;
-def LD1_LANE : WInst<"vld1_lane", ".(c*!).I", "dQdPlQPl">;
-def LD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "lUlQcQUcQPcQlQUldQdPlQPl">;
-def LD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "lUlQcQUcQPcQlQUldQdPlQPl">;
-def LD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "lUlQcQUcQPcQlQUldQdPlQPl">;
-def ST1_LANE : WInst<"vst1_lane", "v*(.!)I", "dQdPlQPl">;
-def ST2_LANE : WInst<"vst2_lane", "v*(2!)I", "lUlQcQUcQPcQlQUldQdPlQPl">;
-def ST3_LANE : WInst<"vst3_lane", "v*(3!)I", "lUlQcQUcQPcQlQUldQdPlQPl">;
-def ST4_LANE : WInst<"vst4_lane", "v*(4!)I", "lUlQcQUcQPcQlQUldQdPlQPl">;
+def LD1_LANE : WInst<"vld1_lane", ".(c*!).I", "dQdPlQPl",
+ [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
+def LD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "lUlQcQUcQPcQlQUldQdPlQPl",
+ [ImmCheck<4, ImmCheckLaneIndex, 1>]>;
+def LD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "lUlQcQUcQPcQlQUldQdPlQPl",
+ [ImmCheck<5, ImmCheckLaneIndex, 1>]>;
+def LD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "lUlQcQUcQPcQlQUldQdPlQPl",
+ [ImmCheck<6, ImmCheckLaneIndex, 1>]>;
+def ST1_LANE : WInst<"vst1_lane", "v*(.!)I", "dQdPlQPl",
+ [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
+def ST2_LANE : WInst<"vst2_lane", "v*(2!)I", "lUlQcQUcQPcQlQUldQdPlQPl",
+ [ImmCheck<3, ImmCheckLaneIndex, 1>]>;
+def ST3_LANE : WInst<"vst3_lane", "v*(3!)I", "lUlQcQUcQPcQlQUldQdPlQPl",
+ [ImmCheck<4, ImmCheckLaneIndex, 1>]>;
+def ST4_LANE : WInst<"vst4_lane", "v*(4!)I", "lUlQcQUcQPcQlQUldQdPlQPl",
+ [ImmCheck<5, ImmCheckLaneIndex, 1>]>;
def LD1_DUP : WInst<"vld1_dup", ".(c*!...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/100278
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