[clang] e8ab413 - [RISCV] Add capital letters to T-Head extension names in descriptions. (#99070)
via cfe-commits
cfe-commits at lists.llvm.org
Tue Jul 16 15:33:30 PDT 2024
Author: Craig Topper
Date: 2024-07-16T15:33:27-07:00
New Revision: e8ab4132598cd925263137adfad510b411459907
URL: https://github.com/llvm/llvm-project/commit/e8ab4132598cd925263137adfad510b411459907
DIFF: https://github.com/llvm/llvm-project/commit/e8ab4132598cd925263137adfad510b411459907.diff
LOG: [RISCV] Add capital letters to T-Head extension names in descriptions. (#99070)
This matches T-Head documentation and the capitalization we use for the
RISCVSubtarget methods.
Added:
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/MC/RISCV/XTHeadVdot-valid.s
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 88cbcc1296244..1dc4580ec202e 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -154,17 +154,17 @@
// CHECK-NEXT: xsfvqmaccqoq 1.0 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))
// CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)
// CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)
-// CHECK-NEXT: xtheadba 1.0 'xtheadba' (T-Head address calculation instructions)
-// CHECK-NEXT: xtheadbb 1.0 'xtheadbb' (T-Head basic bit-manipulation instructions)
-// CHECK-NEXT: xtheadbs 1.0 'xtheadbs' (T-Head single-bit instructions)
-// CHECK-NEXT: xtheadcmo 1.0 'xtheadcmo' (T-Head cache management instructions)
-// CHECK-NEXT: xtheadcondmov 1.0 'xtheadcondmov' (T-Head conditional move instructions)
-// CHECK-NEXT: xtheadfmemidx 1.0 'xtheadfmemidx' (T-Head FP Indexed Memory Operations)
-// CHECK-NEXT: xtheadmac 1.0 'xtheadmac' (T-Head Multiply-Accumulate Instructions)
-// CHECK-NEXT: xtheadmemidx 1.0 'xtheadmemidx' (T-Head Indexed Memory Operations)
-// CHECK-NEXT: xtheadmempair 1.0 'xtheadmempair' (T-Head two-GPR Memory Operations)
-// CHECK-NEXT: xtheadsync 1.0 'xtheadsync' (T-Head multicore synchronization instructions)
-// CHECK-NEXT: xtheadvdot 1.0 'xtheadvdot' (T-Head Vector Extensions for Dot)
+// CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions)
+// CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions)
+// CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions)
+// CHECK-NEXT: xtheadcmo 1.0 'XTHeadCmo' (T-Head cache management instructions)
+// CHECK-NEXT: xtheadcondmov 1.0 'XTHeadCondMov' (T-Head conditional move instructions)
+// CHECK-NEXT: xtheadfmemidx 1.0 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)
+// CHECK-NEXT: xtheadmac 1.0 'XTHeadMac' (T-Head Multiply-Accumulate Instructions)
+// CHECK-NEXT: xtheadmemidx 1.0 'XTHeadMemIdx' (T-Head Indexed Memory Operations)
+// CHECK-NEXT: xtheadmempair 1.0 'XTHeadMemPair' (T-Head two-GPR Memory Operations)
+// CHECK-NEXT: xtheadsync 1.0 'XTHeadSync' (T-Head multicore synchronization instructions)
+// CHECK-NEXT: xtheadvdot 1.0 'XTHeadVdot' (T-Head Vector Extensions for Dot)
// CHECK-NEXT: xventanacondops 1.0 'XVentanaCondOps' (Ventana Conditional Ops)
// CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes)
// CHECK-EMPTY:
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 5a8605aa4a197..c9979b2b36fc3 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1006,81 +1006,81 @@ def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()"
def FeatureVendorXTHeadBa
: RISCVExtension<"xtheadba", 1, 0,
- "'xtheadba' (T-Head address calculation instructions)">;
+ "'XTHeadBa' (T-Head address calculation instructions)">;
def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
- "'xtheadba' (T-Head address calculation instructions)">;
+ "'XTHeadBa' (T-Head address calculation instructions)">;
def FeatureVendorXTHeadBb
: RISCVExtension<"xtheadbb", 1, 0,
- "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
+ "'XTHeadBb' (T-Head basic bit-manipulation instructions)">;
def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
- "'xtheadbb' (T-Head basic bit-manipulation instructions)">;
+ "'XTHeadBb' (T-Head basic bit-manipulation instructions)">;
def FeatureVendorXTHeadBs
: RISCVExtension<"xtheadbs", 1, 0,
- "'xtheadbs' (T-Head single-bit instructions)">;
+ "'XTHeadBs' (T-Head single-bit instructions)">;
def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
- "'xtheadbs' (T-Head single-bit instructions)">;
+ "'XTHeadBs' (T-Head single-bit instructions)">;
def FeatureVendorXTHeadCondMov
: RISCVExtension<"xtheadcondmov", 1, 0,
- "'xtheadcondmov' (T-Head conditional move instructions)">;
+ "'XTHeadCondMov' (T-Head conditional move instructions)">;
def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
- "'xtheadcondmov' (T-Head conditional move instructions)">;
+ "'XTHeadCondMov' (T-Head conditional move instructions)">;
def FeatureVendorXTHeadCmo
: RISCVExtension<"xtheadcmo", 1, 0,
- "'xtheadcmo' (T-Head cache management instructions)">;
+ "'XTHeadCmo' (T-Head cache management instructions)">;
def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
- "'xtheadcmo' (T-Head cache management instructions)">;
+ "'XTHeadCmo' (T-Head cache management instructions)">;
def FeatureVendorXTHeadFMemIdx
: RISCVExtension<"xtheadfmemidx", 1, 0,
- "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
+ "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">;
def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
- "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
+ "'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations)">;
def FeatureVendorXTHeadMac
: RISCVExtension<"xtheadmac", 1, 0,
- "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
+ "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">;
def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
- "'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
+ "'XTHeadMac' (T-Head Multiply-Accumulate Instructions)">;
def FeatureVendorXTHeadMemIdx
: RISCVExtension<"xtheadmemidx", 1, 0,
- "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
+ "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">;
def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
- "'xtheadmemidx' (T-Head Indexed Memory Operations)">;
+ "'XTHeadMemIdx' (T-Head Indexed Memory Operations)">;
def FeatureVendorXTHeadMemPair
: RISCVExtension<"xtheadmempair", 1, 0,
- "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
+ "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">;
def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
- "'xtheadmempair' (T-Head two-GPR Memory Operations)">;
+ "'XTHeadMemPair' (T-Head two-GPR Memory Operations)">;
def FeatureVendorXTHeadSync
: RISCVExtension<"xtheadsync", 1, 0,
- "'xtheadsync' (T-Head multicore synchronization instructions)">;
+ "'XTHeadSync' (T-Head multicore synchronization instructions)">;
def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
- "'xtheadsync' (T-Head multicore synchronization instructions)">;
+ "'XTHeadSync' (T-Head multicore synchronization instructions)">;
def FeatureVendorXTHeadVdot
: RISCVExtension<"xtheadvdot", 1, 0,
- "'xtheadvdot' (T-Head Vector Extensions for Dot)",
+ "'XTHeadVdot' (T-Head Vector Extensions for Dot)",
[FeatureStdExtV]>;
def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
- "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
+ "'XTHeadVdot' (T-Head Vector Extensions for Dot)">;
// SiFive Extensions
diff --git a/llvm/test/MC/RISCV/XTHeadVdot-valid.s b/llvm/test/MC/RISCV/XTHeadVdot-valid.s
index ab411dfac7308..ecae431f68a90 100644
--- a/llvm/test/MC/RISCV/XTHeadVdot-valid.s
+++ b/llvm/test/MC/RISCV/XTHeadVdot-valid.s
@@ -11,83 +11,83 @@
th.vmaqau.vv v8, v20, v4, v0.t
# CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x88]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 884a640b <unknown>
th.vmaqau.vv v8, v20, v4
# CHECK-INST: th.vmaqau.vv v8, v20, v4
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 8a4a640b <unknown>
th.vmaqau.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x8c]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 8c45640b <unknown>
th.vmaqau.vx v8, a0, v4
# CHECK-INST: th.vmaqau.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x8e]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 8e45640b <unknown>
th.vmaqa.vv v8, v20, v4, v0.t
# CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x80]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 804a640b <unknown>
th.vmaqa.vv v8, v20, v4
# CHECK-INST: th.vmaqa.vv v8, v20, v4
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x82]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 824a640b <unknown>
th.vmaqa.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x84]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 8445640b <unknown>
th.vmaqa.vx v8, a0, v4
# CHECK-INST: th.vmaqa.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x86]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 8645640b <unknown>
th.vmaqasu.vv v8, v20, v4, v0.t
# CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x90]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 904a640b <unknown>
th.vmaqasu.vv v8, v20, v4
# CHECK-INST: th.vmaqasu.vv v8, v20, v4
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x92]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 924a640b <unknown>
th.vmaqasu.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x94]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 9445640b <unknown>
th.vmaqasu.vx v8, a0, v4
# CHECK-INST: th.vmaqasu.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x96]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 9645640b <unknown>
th.vmaqaus.vx v8, a0, v4, v0.t
# CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x0b,0x64,0x45,0x9c]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 9c45640b <unknown>
th.vmaqaus.vx v8, a0, v4
# CHECK-INST: th.vmaqaus.vx v8, a0, v4
# CHECK-ENCODING: [0x0b,0x64,0x45,0x9e]
-# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
+# CHECK-ERROR: instruction requires the following: 'XTHeadVdot' (T-Head Vector Extensions for Dot){{$}}
# CHECK-UNKNOWN: 9e45640b <unknown>
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