[clang] [Clang] [WIP] Added builtin_alloca support for OpenCL1.2 and below (PR #95750)

Anastasia Stulova via cfe-commits cfe-commits at lists.llvm.org
Tue Jul 2 06:59:33 PDT 2024


================
@@ -0,0 +1,255 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
+// RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa -cl-std=CL1.2 \
+// RUN:     -emit-llvm -o - | FileCheck --check-prefix=OPENCL12 %s
+// RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa -cl-std=CL2.0 \
+// RUN:     -emit-llvm -o - | FileCheck --check-prefix=OPENCL20 %s
+// RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa -cl-std=CL3.0 \
+// RUN:     -emit-llvm -o - | FileCheck --check-prefix=OPENCL30 %s
+// RUN: %clang_cc1 %s -O0 -triple amdgcn-amd-amdhsa -cl-std=CL3.0 -cl-ext=+__opencl_c_generic_address_space \
+// RUN:     -emit-llvm -o - | FileCheck --check-prefix=OPENCL30-EXT %s
+
+// OPENCL12-LABEL: define dso_local void @test1(
+// OPENCL12-SAME: i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+// OPENCL12-NEXT:  [[ENTRY:.*:]]
+// OPENCL12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL12-NEXT:    [[MUL:%.*]] = mul i64 [[CONV]], 4
+// OPENCL12-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[MUL]], align 8, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL12-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL12-NEXT:    [[MUL2:%.*]] = mul i64 [[CONV1]], 4
+// OPENCL12-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[MUL2]], align 8, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL12-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL12-NEXT:    [[MUL4:%.*]] = mul i64 [[CONV3]], 4
+// OPENCL12-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[MUL4]], align 1, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL12-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV5:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL12-NEXT:    [[MUL6:%.*]] = mul i64 [[CONV5]], 4
+// OPENCL12-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[MUL6]], align 1, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL12-NEXT:    ret void
+//
+// OPENCL20-LABEL: define dso_local void @test1(
+// OPENCL20-SAME: i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+// OPENCL20-NEXT:  [[ENTRY:.*:]]
+// OPENCL20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL20-NEXT:    [[MUL:%.*]] = mul i64 [[CONV]], 4
+// OPENCL20-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[MUL]], align 8, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL20-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL20-NEXT:    [[MUL2:%.*]] = mul i64 [[CONV1]], 4
+// OPENCL20-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[MUL2]], align 8, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL20-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL20-NEXT:    [[MUL4:%.*]] = mul i64 [[CONV3]], 4
+// OPENCL20-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[MUL4]], align 1, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL20-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV5:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL20-NEXT:    [[MUL6:%.*]] = mul i64 [[CONV5]], 4
+// OPENCL20-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[MUL6]], align 1, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL20-NEXT:    ret void
+//
+// OPENCL30-LABEL: define dso_local void @test1(
+// OPENCL30-SAME: i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+// OPENCL30-NEXT:  [[ENTRY:.*:]]
+// OPENCL30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL30-NEXT:    [[MUL:%.*]] = mul i64 [[CONV]], 4
+// OPENCL30-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[MUL]], align 8, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL30-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL30-NEXT:    [[MUL2:%.*]] = mul i64 [[CONV1]], 4
+// OPENCL30-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[MUL2]], align 8, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL30-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL30-NEXT:    [[MUL4:%.*]] = mul i64 [[CONV3]], 4
+// OPENCL30-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[MUL4]], align 1, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL30-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV5:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL30-NEXT:    [[MUL6:%.*]] = mul i64 [[CONV5]], 4
+// OPENCL30-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[MUL6]], align 1, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL30-NEXT:    ret void
+//
+// OPENCL30-EXT-LABEL: define dso_local void @test1(
+// OPENCL30-EXT-SAME: i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+// OPENCL30-EXT-NEXT:  [[ENTRY:.*:]]
+// OPENCL30-EXT-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-EXT-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-EXT-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL30-EXT-NEXT:    [[MUL:%.*]] = mul i64 [[CONV]], 4
+// OPENCL30-EXT-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[MUL]], align 8, addrspace(5)
+// OPENCL30-EXT-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL30-EXT-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-EXT-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL30-EXT-NEXT:    [[MUL2:%.*]] = mul i64 [[CONV1]], 4
+// OPENCL30-EXT-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[MUL2]], align 8, addrspace(5)
+// OPENCL30-EXT-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL30-EXT-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-EXT-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL30-EXT-NEXT:    [[MUL4:%.*]] = mul i64 [[CONV3]], 4
+// OPENCL30-EXT-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[MUL4]], align 1, addrspace(5)
+// OPENCL30-EXT-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL30-EXT-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-EXT-NEXT:    [[CONV5:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL30-EXT-NEXT:    [[MUL6:%.*]] = mul i64 [[CONV5]], 4
+// OPENCL30-EXT-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[MUL6]], align 1, addrspace(5)
+// OPENCL30-EXT-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL30-EXT-NEXT:    ret void
+//
+void test1(unsigned n) {
+    __private float* alloc_ptr = (__private float*)__builtin_alloca(n*sizeof(int));
+    __private float* alloc_ptr_uninitialized = (__private float*)__builtin_alloca_uninitialized(n*sizeof(int));
+    __private float* alloc_ptr_align = (__private float*)__builtin_alloca_with_align((n*sizeof(int)), 8);
+    __private float* alloc_ptr_align_uninitialized = (__private float*)__builtin_alloca_with_align_uninitialized((n*sizeof(int)), 8);
+}
+
+// OPENCL12-LABEL: define dso_local void @test2(
+// OPENCL12-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// OPENCL12-NEXT:  [[ENTRY:.*:]]
+// OPENCL12-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL12-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL12-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[CONV]], align 8, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL12-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL12-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[CONV1]], align 8, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL12-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV2:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL12-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[CONV2]], align 1, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL12-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL12-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL12-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[CONV3]], align 1, addrspace(5)
+// OPENCL12-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL12-NEXT:    ret void
+//
+// OPENCL20-LABEL: define dso_local void @test2(
+// OPENCL20-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// OPENCL20-NEXT:  [[ENTRY:.*:]]
+// OPENCL20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL20-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL20-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[CONV]], align 8, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL20-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL20-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[CONV1]], align 8, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL20-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV2:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL20-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[CONV2]], align 1, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL20-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL20-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL20-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[CONV3]], align 1, addrspace(5)
+// OPENCL20-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL20-NEXT:    ret void
+//
+// OPENCL30-LABEL: define dso_local void @test2(
+// OPENCL30-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// OPENCL30-NEXT:  [[ENTRY:.*:]]
+// OPENCL30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[TMP0:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV:%.*]] = zext i32 [[TMP0]] to i64
+// OPENCL30-NEXT:    [[TMP1:%.*]] = alloca i8, i64 [[CONV]], align 8, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[ALLOC_PTR]], align 4
+// OPENCL30-NEXT:    [[TMP2:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV1:%.*]] = zext i32 [[TMP2]] to i64
+// OPENCL30-NEXT:    [[TMP3:%.*]] = alloca i8, i64 [[CONV1]], align 8, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP3]], ptr addrspace(5) [[ALLOC_PTR_UNINITIALIZED]], align 4
+// OPENCL30-NEXT:    [[TMP4:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV2:%.*]] = zext i32 [[TMP4]] to i64
+// OPENCL30-NEXT:    [[TMP5:%.*]] = alloca i8, i64 [[CONV2]], align 1, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP5]], ptr addrspace(5) [[ALLOC_PTR_ALIGN]], align 4
+// OPENCL30-NEXT:    [[TMP6:%.*]] = load i32, ptr addrspace(5) [[N_ADDR]], align 4
+// OPENCL30-NEXT:    [[CONV3:%.*]] = zext i32 [[TMP6]] to i64
+// OPENCL30-NEXT:    [[TMP7:%.*]] = alloca i8, i64 [[CONV3]], align 1, addrspace(5)
+// OPENCL30-NEXT:    store ptr addrspace(5) [[TMP7]], ptr addrspace(5) [[ALLOC_PTR_ALIGN_UNINITIALIZED]], align 4
+// OPENCL30-NEXT:    ret void
+//
+// OPENCL30-EXT-LABEL: define dso_local void @test2(
+// OPENCL30-EXT-SAME: i32 noundef [[N:%.*]]) #[[ATTR0]] {
+// OPENCL30-EXT-NEXT:  [[ENTRY:.*:]]
+// OPENCL30-EXT-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR_ALIGN:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    [[ALLOC_PTR_ALIGN_UNINITIALIZED:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
+// OPENCL30-EXT-NEXT:    store i32 [[N]], ptr addrspace(5) [[N_ADDR]], align 4
----------------
AnastasiaStulova wrote:

Do we need to check all these extra lines?

https://github.com/llvm/llvm-project/pull/95750


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