[clang] [hexagon] Add {con, de}structive interference size defn (PR #94877)
Brian Cain via cfe-commits
cfe-commits at lists.llvm.org
Wed Jun 19 14:45:28 PDT 2024
androm3da wrote:
I was mistaken: it appears that the cache line size is not the same among all CPUs. I'll revise this PR.
Since I'm away from the office for a couple of weeks, I've switched this PR to a draft. I'll revisit it when I return and promote it when updated.
https://github.com/llvm/llvm-project/pull/94877
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