[clang] [llvm] [AArch64] Add ability to list extensions enabled for a target (PR #95805)
Lucas Duarte Prates via cfe-commits
cfe-commits at lists.llvm.org
Tue Jun 18 08:49:44 PDT 2024
https://github.com/pratlucas updated https://github.com/llvm/llvm-project/pull/95805
>From aa99e084441478cd5d016661b028d7d886c49a2f Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Thu, 13 Jun 2024 10:11:11 +0100
Subject: [PATCH 1/9] [NFC][AArch64] Organise extensions by archtecture version
This updates the way the AArch64 architecture extensions are
organised in AArch64Features.td to improve readability and
maintainability of the file. Extensions are now grouped by
the coresponding architecture version in which they were
introduced.
---
llvm/lib/Target/AArch64/AArch64Features.td | 980 +++++++++++----------
1 file changed, 522 insertions(+), 458 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index ffb899a301459..911a282e14936 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -101,6 +101,11 @@ def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-a
// Arm Architecture Features, it should list all the relevant features. Not all
// FEAT_ features have a corresponding SubtargetFeature.
+
+//===----------------------------------------------------------------------===//
+// Armv8.0 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
let ArchExtKindSpelling = "AEK_FP", MArchName = "fp" in
def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8",
"Enable ARMv8 (FEAT_FP)", [],
@@ -111,21 +116,11 @@ def FeatureNEON : Extension<"neon", "NEON",
"Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8],
"FEAT_SIMD", "+fp-armv8,+neon", 100>;
-def FeatureSM4 : Extension<
- "sm4", "SM4",
- "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
- "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
-
def FeatureSHA2 : Extension<
"sha2", "SHA2",
"Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON],
"FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
-def FeatureSHA3 : Extension<
- "sha3", "SHA3",
- "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2],
- "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
-
def FeatureAES : Extension<
"aes", "AES",
"Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON],
@@ -147,26 +142,24 @@ def FeatureCRC : Extension<"crc", "CRC",
"Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [],
"FEAT_CRC", "+crc", 110>;
-def FeatureRAS : Extension<"ras", "RAS",
- "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
+// This SubtargetFeature is special. It controls only whether codegen will turn
+// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
+// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
+let MArchName = "pmuv3" in
+def FeaturePerfMon : Extension<"perfmon", "PerfMon",
+ "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
-def FeatureRASv2 : Extension<"rasv2", "RASv2",
- "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
- [FeatureRAS]>;
+def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
+ "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.1 Architecture Extensions
+//===----------------------------------------------------------------------===//
def FeatureLSE : Extension<"lse", "LSE",
"Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [],
"FEAT_LSE", "+lse", 80>;
-def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
- "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
-
-def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
- "Enable out of line atomics to support LSE instructions">;
-
-def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
- "Enable Function Multi Versioning support.">;
-
let MArchAlias = "rdma" in
def FeatureRDM : Extension<"rdm", "RDM",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)",
@@ -187,22 +180,28 @@ def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
"Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
-// This SubtargetFeature is special. It controls only whether codegen will turn
-// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
-// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
-let MArchName = "pmuv3" in
-def FeaturePerfMon : Extension<"perfmon", "PerfMon",
- "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
+//===----------------------------------------------------------------------===//
+// Armv8.2 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureSM4 : Extension<
+ "sm4", "SM4",
+ "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
+ "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
+
+def FeatureSHA3 : Extension<
+ "sha3", "SHA3",
+ "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2],
+ "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
+
+def FeatureRAS : Extension<"ras", "RAS",
+ "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in
def FeatureFullFP16 : Extension<"fullfp16", "FullFP16",
"Full FP16 (FEAT_FP16)", [FeatureFPARMv8],
"FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
-def FeatureFP16FML : Extension<"fp16fml", "FP16FML",
- "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
- "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
-
let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in
def FeatureSPE : Extension<"spe", "SPE",
"Enable Statistical Profiling extension (FEAT_SPE)">;
@@ -212,7 +211,6 @@ def FeaturePAN_RWV : SubtargetFeature<
"Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)",
[FeaturePAN]>;
-// UAO PState
def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
"Enable v8.2 UAO PState (FEAT_UAO)">;
@@ -223,135 +221,509 @@ def FeatureSVE : Extension<"sve", "SVE",
"Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16],
"FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
-// This flag is currently still labeled as Experimental, but when fully
-// implemented this should tell the compiler to use the zeroing pseudos to
-// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
-// lanes are known to be zero. The pseudos will then be expanded using the
-// MOVPRFX instruction to zero the inactive lanes. This feature should only be
-// enabled if MOVPRFX instructions are known to merge with the destructive
-// operations they prefix.
-//
-// This feature could similarly be extended to support cheap merging of _any_
-// value into the inactive lanes using the MOVPRFX instruction that uses
-// merging-predication.
-def FeatureExperimentalZeroingPseudos
- : SubtargetFeature<"use-experimental-zeroing-pseudos",
- "UseExperimentalZeroingPseudos", "true",
- "Hint to the compiler that the MOVPRFX instruction is "
- "merged with destructive operations",
- []>;
+let ArchExtKindSpelling = "AEK_I8MM" in
+def FeatureMatMulInt8 : Extension<"i8mm", "MatMulInt8",
+ "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
+ "FEAT_I8MM", "+i8mm", 270>;
-def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
- "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
+let ArchExtKindSpelling = "AEK_F32MM" in
+def FeatureMatMulFP32 : Extension<"f32mm", "MatMulFP32",
+ "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
+ "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
-def FeatureBF16 : Extension<"bf16", "BF16",
- "Enable BFloat16 Extension (FEAT_BF16)", [],
- "FEAT_BF16", "+bf16", 280>;
+let ArchExtKindSpelling = "AEK_F64MM" in
+def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64",
+ "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
+ "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
-def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
- "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;
+//===----------------------------------------------------------------------===//
+// Armv8.3 Architecture Extensions
+//===----------------------------------------------------------------------===//
-def FeatureSVE2 : Extension<"sve2", "SVE2",
- "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
- [FeatureSVE, FeatureUseScalarIncVL],
- "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
+def FeatureRCPC : Extension<"rcpc", "RCPC",
+ "Enable support for RCPC extension (FEAT_LRCPC)", [],
+ "FEAT_RCPC", "+rcpc", 230>;
-def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES",
- "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
- [FeatureSVE2, FeatureAES],
- "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
+def FeaturePAuth : Extension<
+ "pauth", "PAuth",
+ "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
-def FeatureSVE2SM4 : Extension<"sve2-sm4", "SVE2SM4",
- "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4],
- "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
+let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
+def FeatureJS : Extension<
+ "jsconv", "JS",
+ "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
+ [FeatureFPARMv8],
+ "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
-def FeatureSVE2SHA3 : Extension<"sve2-sha3", "SVE2SHA3",
- "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3],
- "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
+def FeatureCCIDX : SubtargetFeature<
+ "ccidx", "HasCCIDX", "true",
+ "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
-def FeatureSVE2BitPerm : Extension<"sve2-bitperm", "SVE2BitPerm",
- "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
- "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
+let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
+def FeatureComplxNum : Extension<
+ "complxnum", "ComplxNum",
+ "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
+ [FeatureNEON],
+ "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
-let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in
-def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1",
- "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
+def FeatureNV : SubtargetFeature<
+ "nv", "HasNV", "true",
+ "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
-def FeatureB16B16 : Extension<"b16b16", "B16B16",
- "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>;
+//===----------------------------------------------------------------------===//
+// Armv8.4 Architecture Extensions
+//===----------------------------------------------------------------------===//
-def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
- "Has zero-cycle register moves">;
+def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
+ "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
-def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
- "Has zero-cycle zeroing instructions for generic registers">;
+def FeatureFP16FML : Extension<"fp16fml", "FP16FML",
+ "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
+ "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
-// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
-// as movi is more efficient across all cores. Newer cores can eliminate
-// fmovs early and there is no difference with movi, but this not true for
-// all implementations.
-def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
- "Has no zero-cycle zeroing instructions for FP registers">;
+def FeatureDotProd : Extension<
+ "dotprod", "DotProd",
+ "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
+ "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
-def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
- "Has zero-cycle zeroing instructions",
- [FeatureZCZeroingGP]>;
+def FeatureMPAM : SubtargetFeature<
+ "mpam", "HasMPAM", "true",
+ "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
-/// ... but the floating-point version doesn't quite work in rare cases on older
-/// CPUs.
-def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
- "HasZeroCycleZeroingFPWorkaround", "true",
- "The zero-cycle floating-point zeroing instruction has a bug">;
+def FeatureDIT : Extension<
+ "dit", "DIT",
+ "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", [],
+ "FEAT_DIT", "+dit", 180>;
-def FeatureStrictAlign : SubtargetFeature<"strict-align",
- "RequiresStrictAlign", "true",
- "Disallow all unaligned memory "
- "access">;
+def FeatureTRACEV8_4 : SubtargetFeature<
+ "tracev8.4", "HasTRACEV8_4", "true",
+ "Enable v8.4-A Trace extension (FEAT_TRF)">;
-foreach i = {1-7,9-15,18,20-28} in
- def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
- "Reserve X"#i#", making it unavailable "
- "as a GPR">;
+def FeatureAM : SubtargetFeature<
+ "am", "HasAM", "true",
+ "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
-foreach i = {8-15,18} in
- def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
- "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
+def FeatureSEL2 : SubtargetFeature<
+ "sel2", "HasSEL2", "true",
+ "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
-def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
- "true",
- "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
+def FeatureTLB_RMI : SubtargetFeature<
+ "tlb-rmi", "HasTLB_RMI", "true",
+ "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
-def FeaturePredictableSelectIsExpensive : SubtargetFeature<
- "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
- "Prefer likely predicted branches over selects">;
+def FeatureFlagM : Extension<
+ "flagm", "FlagM",
+ "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
+ "FEAT_FLAGM", "+flagm", 20>;
-def FeatureEnableSelectOptimize : SubtargetFeature<
- "enable-select-opt", "EnableSelectOptimize", "true",
- "Enable the select optimize pass for select loop heuristics">;
+def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
+ "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
+ [FeatureRCPC]>;
-def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
- "HasExynosCheapAsMoveHandling", "true",
- "Use Exynos specific handling of cheap instructions">;
+//===----------------------------------------------------------------------===//
+// Armv8.5 Architecture Extensions
+//===----------------------------------------------------------------------===//
-def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
- "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
+ "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">;
-def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
- "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">;
+def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
+ "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
+ "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >;
-def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
- "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">;
+def FeatureSB : Extension<"sb", "SB",
+ "Enable v8.5 Speculation Barrier (FEAT_SB)", [],
+ "FEAT_SB", "+sb", 470>;
-def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
- "IsStoreAddressAscend", "true",
- "Schedule vector stores by ascending address">;
+def FeatureSSBS : Extension<"ssbs", "SSBS",
+ "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [],
+ "FEAT_SSBS", "", 490>;
-def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
- "true", "STR of Q register with register offset is slow">;
+def FeaturePredRes : Extension<"predres", "PredRes",
+ "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [],
+ "FEAT_PREDRES", "+predres", 480>;
-def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
- "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
- "true", "Use alternative pattern for sextload convert to f32">;
+def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true",
+ "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
+
+let ArchExtKindSpelling = "AEK_NONE" in
+def FeatureBranchTargetId : Extension<"bti", "BTI",
+ "Enable Branch Target Identification (FEAT_BTI)", [],
+ "FEAT_BTI", "+bti", 510>;
+
+let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
+def FeatureRandGen : Extension<"rand", "RandGen",
+ "Enable Random Number generation instructions (FEAT_RNG)", [],
+ "FEAT_RNG", "+rand", 10>;
+
+// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
+// __attribute((target(...))), but only FEAT_MTE for FMV.
+let MArchName = "memtag" in
+def FeatureMTE : Extension<"mte", "MTE",
+ "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
+ "FEAT_MEMTAG", "", 440>;
+
+//===----------------------------------------------------------------------===//
+// Armv8.6 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureBF16 : Extension<"bf16", "BF16",
+ "Enable BFloat16 Extension (FEAT_BF16)", [],
+ "FEAT_BF16", "+bf16", 280>;
+
+def FeatureAMVS : SubtargetFeature<
+ "amvs", "HasAMVS", "true",
+ "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
+ [FeatureAM]>;
+
+def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
+ "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
+
+def FeatureEnhancedCounterVirtualization :
+ SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
+ "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.7 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureXS : SubtargetFeature<"xs", "HasXS",
+ "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
+
+def FeatureWFxT : Extension<"wfxt", "WFxT",
+ "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [],
+ "FEAT_WFXT", "+wfxt", 550>;
+
+def FeatureHCX : SubtargetFeature<
+ "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
+
+def FeatureLS64 : Extension<"ls64", "LS64",
+ "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
+ "FEAT_LS64", "", 520>;
+
+def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
+ "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.8 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureHBC : Extension<"hbc", "HBC",
+ "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
+
+def FeatureMOPS : Extension<"mops", "MOPS",
+ "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", [],
+ "FEAT_MOPS", "+mops", 650>;
+
+def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
+ "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
+
+//===----------------------------------------------------------------------===//
+// Armv8.9 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureRASv2 : Extension<"rasv2", "RASv2",
+ "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
+ [FeatureRAS]>;
+
+def FeatureCSSC : Extension<"cssc", "CSSC",
+ "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
+
+def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB",
+ "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">;
+
+def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC",
+ "true", "Enable SLC target for PRFM instruction">;
+
+let MArchName = "predres2" in
+def FeatureSPECRES2 : Extension<"specres2", "SPECRES2",
+ "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
+ [FeaturePredRes]>;
+
+def FeatureRCPC3 : Extension<"rcpc3", "RCPC3",
+ "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
+ [FeatureRCPC_IMMO],
+ "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
+
+def FeatureTHE : Extension<"the", "THE",
+ "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
+
+//===----------------------------------------------------------------------===//
+// Armv9.0 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
+ "UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
+
+def FeatureSVE2 : Extension<"sve2", "SVE2",
+ "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
+ [FeatureSVE, FeatureUseScalarIncVL],
+ "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
+
+def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES",
+ "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
+ [FeatureSVE2, FeatureAES],
+ "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
+
+def FeatureSVE2SM4 : Extension<"sve2-sm4", "SVE2SM4",
+ "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4],
+ "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
+
+def FeatureSVE2SHA3 : Extension<"sve2-sha3", "SVE2SHA3",
+ "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3],
+ "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
+
+def FeatureSVE2BitPerm : Extension<"sve2-bitperm", "SVE2BitPerm",
+ "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
+ "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
+
+def FeatureTRBE : SubtargetFeature<"trbe", "TRBE", "true",
+ "Enable Trace Buffer Extension (FEAT_TRBE)">;
+
+def FeatureETE : SubtargetFeature<"ete", "ETE", "true",
+ "Enable Embedded Trace Extension (FEAT_ETE)",
+ [FeatureTRBE]>;
+
+def FeatureTME : Extension<"tme", "TME",
+ "Enable Transactional Memory Extension (FEAT_TME)" >;
+
+//===----------------------------------------------------------------------===//
+// Armv9.1 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Armv9.2 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureBRBE : Extension<"brbe", "BRBE",
+ "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
+
+def FeatureRME : SubtargetFeature<"rme", "HasRME",
+ "true", "Enable Realm Management Extension (FEAT_RME)">;
+
+def FeatureSME : Extension<"sme", "SME",
+ "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL],
+ "FEAT_SME", "+sme,+bf16", 430>;
+
+def FeatureSMEF64F64 : Extension<"sme-f64f64", "SMEF64F64",
+ "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME],
+ "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
+
+def FeatureSMEI16I64 : Extension<"sme-i16i64", "SMEI16I64",
+ "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME],
+ "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
+
+def FeatureSMEFA64 : Extension<"sme-fa64", "SMEFA64",
+ "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>;
+
+//===----------------------------------------------------------------------===//
+// Armv9.3 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureSME2 : Extension<"sme2", "SME2",
+ "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
+ "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
+
+def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
+ "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
+
+//===----------------------------------------------------------------------===//
+// Armv9.4 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in
+def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1",
+ "Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
+
+def FeatureB16B16 : Extension<"b16b16", "B16B16",
+ "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>;
+
+let FMVDependencies = "+sme2,+sme-f16f16" in
+def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16",
+ "Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>;
+
+let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in
+def FeatureSME2p1 : Extension<"sme2p1", "SME2p1",
+ "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>;
+
+def FeatureCHK : SubtargetFeature<"chk", "HasCHK",
+ "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">;
+
+def FeatureGCS : Extension<"gcs", "GCS",
+ "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
+
+def FeatureITE : Extension<"ite", "ITE",
+ "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE,
+ FeatureTRBE]>;
+
+def FeatureLSE128 : Extension<"lse128", "LSE128",
+ "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
+ [FeatureLSE]>;
+
+// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.
+// Therefore group them all under a single feature flag, d128:
+def FeatureD128 : Extension<"d128", "D128",
+ "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
+ "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
+ [FeatureLSE128]>;
+
+//===----------------------------------------------------------------------===//
+// Armv9.5 Architecture Extensions
+//===----------------------------------------------------------------------===//
+
+def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX",
+ "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
+
+def FeatureLUT: Extension<"lut", "LUT",
+ "Enable Lookup Table instructions (FEAT_LUT)">;
+
+def FeatureFP8 : Extension<"fp8", "FP8",
+ "Enable FP8 instructions (FEAT_FP8)", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
+
+def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA",
+ "Enable fp8 multiply-add instructions (FEAT_FP8FMA)", [FeatureFP8]>;
+
+let FMVDependencies = "+sme2" in
+def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA",
+ "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2, FeatureFP8]>;
+
+def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
+ "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>;
+
+def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2",
+ "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>;
+
+let FMVDependencies = "+sme2" in
+def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
+ "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSSVE_FP8FMA]>;
+
+let FMVDependencies = "+sme2" in
+def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
+ "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSSVE_FP8DOT4]>;
+
+def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2",
+ "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
+
+let FMVDependencies = "+sme2,+fp8" in
+def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32",
+ "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
+
+let FMVDependencies = "+fp8,+sme2" in
+def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
+ "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSMEF8F32]>;
+
+def FeatureCPA : Extension<"cpa", "CPA",
+ "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+
+def FeaturePAuthLR : Extension<"pauth-lr", "PAuthLR",
+ "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+
+def FeatureTLBIW : Extension<"tlbiw", "TLBIW",
+ "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">;
+
+//===----------------------------------------------------------------------===//
+// Other Features
+//===----------------------------------------------------------------------===//
+
+def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
+ "Enable out of line atomics to support LSE instructions">;
+
+def FeatureFMV : SubtargetFeature<"fmv", "HasFMV", "true",
+ "Enable Function Multi Versioning support.">;
+
+// This flag is currently still labeled as Experimental, but when fully
+// implemented this should tell the compiler to use the zeroing pseudos to
+// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
+// lanes are known to be zero. The pseudos will then be expanded using the
+// MOVPRFX instruction to zero the inactive lanes. This feature should only be
+// enabled if MOVPRFX instructions are known to merge with the destructive
+// operations they prefix.
+//
+// This feature could similarly be extended to support cheap merging of _any_
+// value into the inactive lanes using the MOVPRFX instruction that uses
+// merging-predication.
+def FeatureExperimentalZeroingPseudos
+ : SubtargetFeature<"use-experimental-zeroing-pseudos",
+ "UseExperimentalZeroingPseudos", "true",
+ "Hint to the compiler that the MOVPRFX instruction is "
+ "merged with destructive operations",
+ []>;
+
+def FeatureNoSVEFPLD1R : SubtargetFeature<"no-sve-fp-ld1r",
+ "NoSVEFPLD1R", "true", "Avoid using LD1RX instructions for FP">;
+
+def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
+ "Has zero-cycle register moves">;
+
+def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
+ "Has zero-cycle zeroing instructions for generic registers">;
+
+// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
+// as movi is more efficient across all cores. Newer cores can eliminate
+// fmovs early and there is no difference with movi, but this not true for
+// all implementations.
+def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
+ "Has no zero-cycle zeroing instructions for FP registers">;
+
+def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
+ "Has zero-cycle zeroing instructions",
+ [FeatureZCZeroingGP]>;
+
+/// ... but the floating-point version doesn't quite work in rare cases on older
+/// CPUs.
+def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
+ "HasZeroCycleZeroingFPWorkaround", "true",
+ "The zero-cycle floating-point zeroing instruction has a bug">;
+
+def FeatureStrictAlign : SubtargetFeature<"strict-align",
+ "RequiresStrictAlign", "true",
+ "Disallow all unaligned memory "
+ "access">;
+
+foreach i = {1-7,9-15,18,20-28} in
+ def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
+ "Reserve X"#i#", making it unavailable "
+ "as a GPR">;
+
+foreach i = {8-15,18} in
+ def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
+ "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
+
+def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
+ "true",
+ "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
+
+def FeaturePredictableSelectIsExpensive : SubtargetFeature<
+ "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
+ "Prefer likely predicted branches over selects">;
+
+def FeatureEnableSelectOptimize : SubtargetFeature<
+ "enable-select-opt", "EnableSelectOptimize", "true",
+ "Enable the select optimize pass for select loop heuristics">;
+
+def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
+ "HasExynosCheapAsMoveHandling", "true",
+ "Use Exynos specific handling of cheap instructions">;
+
+def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
+ "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+
+def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
+ "IsMisaligned128StoreSlow", "true", "Misaligned 128 bit stores are slow">;
+
+def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
+ "IsPaired128Slow", "true", "Paired 128 bit loads and stores are slow">;
+
+def FeatureAscendStoreAddress : SubtargetFeature<"ascend-store-address",
+ "IsStoreAddressAscend", "true",
+ "Schedule vector stores by ascending address">;
+
+def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "IsSTRQroSlow",
+ "true", "STR of Q register with register offset is slow">;
+
+def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
+ "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
+ "true", "Use alternative pattern for sextload convert to f32">;
def FeatureArithmeticBccFusion : SubtargetFeature<
"arith-bcc-fusion", "HasArithmeticBccFusion", "true",
@@ -395,98 +767,23 @@ def FeatureFuseLiterals : SubtargetFeature<
def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature<
"fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true",
- "CPU fuses (a + b + 1) and (a - b - 1)">;
-
-def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
- "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
- "Disable latency scheduling heuristic">;
-
-def FeatureStorePairSuppress : SubtargetFeature<
- "store-pair-suppress", "EnableStorePairSuppress", "true",
- "Enable Store Pair Suppression heuristics">;
-
-def FeatureForce32BitJumpTables
- : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
- "Force jump table entries to be 32-bits wide except at MinSize">;
-
-def FeatureRCPC : Extension<"rcpc", "RCPC",
- "Enable support for RCPC extension (FEAT_LRCPC)", [],
- "FEAT_RCPC", "+rcpc", 230>;
-
-def FeatureUseRSqrt : SubtargetFeature<
- "use-reciprocal-square-root", "UseRSqrt", "true",
- "Use the reciprocal square root approximation">;
-
-def FeatureDotProd : Extension<
- "dotprod", "DotProd",
- "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
- "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
-
-def FeaturePAuth : Extension<
- "pauth", "PAuth",
- "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
-
-let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
-def FeatureJS : Extension<
- "jsconv", "JS",
- "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
- [FeatureFPARMv8],
- "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
-
-def FeatureCCIDX : SubtargetFeature<
- "ccidx", "HasCCIDX", "true",
- "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
-
-let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
-def FeatureComplxNum : Extension<
- "complxnum", "ComplxNum",
- "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
- [FeatureNEON],
- "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
-
-def FeatureNV : SubtargetFeature<
- "nv", "HasNV", "true",
- "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
-
-def FeatureMPAM : SubtargetFeature<
- "mpam", "HasMPAM", "true",
- "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
-
-def FeatureDIT : Extension<
- "dit", "DIT",
- "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", [],
- "FEAT_DIT", "+dit", 180>;
-
-def FeatureTRACEV8_4 : SubtargetFeature<
- "tracev8.4", "HasTRACEV8_4", "true",
- "Enable v8.4-A Trace extension (FEAT_TRF)">;
-
-def FeatureAM : SubtargetFeature<
- "am", "HasAM", "true",
- "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
-
-def FeatureAMVS : SubtargetFeature<
- "amvs", "HasAMVS", "true",
- "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
- [FeatureAM]>;
-
-def FeatureSEL2 : SubtargetFeature<
- "sel2", "HasSEL2", "true",
- "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
+ "CPU fuses (a + b + 1) and (a - b - 1)">;
-def FeatureTLB_RMI : SubtargetFeature<
- "tlb-rmi", "HasTLB_RMI", "true",
- "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
+def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
+ "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
+ "Disable latency scheduling heuristic">;
-def FeatureFlagM : Extension<
- "flagm", "FlagM",
- "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
- "FEAT_FLAGM", "+flagm", 20>;
+def FeatureStorePairSuppress : SubtargetFeature<
+ "store-pair-suppress", "EnableStorePairSuppress", "true",
+ "Enable Store Pair Suppression heuristics">;
-// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
-def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
- "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
- [FeatureRCPC]>;
+def FeatureForce32BitJumpTables
+ : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
+ "Force jump table entries to be 32-bits wide except at MinSize">;
+
+def FeatureUseRSqrt : SubtargetFeature<
+ "use-reciprocal-square-root", "UseRSqrt", "true",
+ "Use the reciprocal square root approximation">;
def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
"NegativeImmediates", "false",
@@ -518,186 +815,11 @@ def FeatureAggressiveFMA :
"true",
"Enable Aggressive FMA for floating-point.">;
-def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
- "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">;
-
-def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
- "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
- "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >;
-
-def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
- "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
-
-def FeatureSB : Extension<"sb", "SB",
- "Enable v8.5 Speculation Barrier (FEAT_SB)", [],
- "FEAT_SB", "+sb", 470>;
-
-def FeatureSSBS : Extension<"ssbs", "SSBS",
- "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [],
- "FEAT_SSBS", "", 490>;
-
-def FeaturePredRes : Extension<"predres", "PredRes",
- "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [],
- "FEAT_PREDRES", "+predres", 480>;
-
-def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true",
- "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
-
-let ArchExtKindSpelling = "AEK_NONE" in
-def FeatureBranchTargetId : Extension<"bti", "BTI",
- "Enable Branch Target Identification (FEAT_BTI)", [],
- "FEAT_BTI", "+bti", 510>;
-
-let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
-def FeatureRandGen : Extension<"rand", "RandGen",
- "Enable Random Number generation instructions (FEAT_RNG)", [],
- "FEAT_RNG", "+rand", 10>;
-
-// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
-// __attribute((target(...))), but only FEAT_MTE for FMV.
-let MArchName = "memtag" in
-def FeatureMTE : Extension<"mte", "MTE",
- "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
- "FEAT_MEMTAG", "", 440>;
-
-def FeatureTRBE : SubtargetFeature<"trbe", "TRBE", "true",
- "Enable Trace Buffer Extension (FEAT_TRBE)">;
-
-def FeatureETE : SubtargetFeature<"ete", "ETE", "true",
- "Enable Embedded Trace Extension (FEAT_ETE)",
- [FeatureTRBE]>;
-
-def FeatureTME : Extension<"tme", "TME",
- "Enable Transactional Memory Extension (FEAT_TME)" >;
-
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
-let ArchExtKindSpelling = "AEK_I8MM" in
-def FeatureMatMulInt8 : Extension<"i8mm", "MatMulInt8",
- "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
- "FEAT_I8MM", "+i8mm", 270>;
-
-let ArchExtKindSpelling = "AEK_F32MM" in
-def FeatureMatMulFP32 : Extension<"f32mm", "MatMulFP32",
- "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
- "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
-
-let ArchExtKindSpelling = "AEK_F64MM" in
-def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64",
- "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
- "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
-
-def FeatureXS : SubtargetFeature<"xs", "HasXS",
- "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
-
-def FeatureWFxT : Extension<"wfxt", "WFxT",
- "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [],
- "FEAT_WFXT", "+wfxt", 550>;
-
-def FeatureHCX : SubtargetFeature<
- "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
-
-def FeatureLS64 : Extension<"ls64", "LS64",
- "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
- "FEAT_LS64", "", 520>;
-
-def FeatureHBC : Extension<"hbc", "HBC",
- "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
-
-def FeatureMOPS : Extension<"mops", "MOPS",
- "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", [],
- "FEAT_MOPS", "+mops", 650>;
-
-def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
- "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
-
-def FeatureBRBE : Extension<"brbe", "BRBE",
- "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
-
-def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
- "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
-
-def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
- "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
-
-def FeatureEnhancedCounterVirtualization :
- SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
- "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">;
-
-def FeatureRME : SubtargetFeature<"rme", "HasRME",
- "true", "Enable Realm Management Extension (FEAT_RME)">;
-
-def FeatureSME : Extension<"sme", "SME",
- "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL],
- "FEAT_SME", "+sme,+bf16", 430>;
-
-def FeatureSMEF64F64 : Extension<"sme-f64f64", "SMEF64F64",
- "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME],
- "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
-
-def FeatureSMEI16I64 : Extension<"sme-i16i64", "SMEI16I64",
- "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME],
- "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
-
-def FeatureSMEFA64 : Extension<"sme-fa64", "SMEFA64",
- "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>;
-
-def FeatureSME2 : Extension<"sme2", "SME2",
- "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
- "FEAT_SME2", "+sme2,+sme,+bf16", 580>;
-
-let FMVDependencies = "+sme2,+sme-f16f16" in
-def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16",
- "Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>;
-
-let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in
-def FeatureSME2p1 : Extension<"sme2p1", "SME2p1",
- "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>;
-
-def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX",
- "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
-
-def FeatureLUT: Extension<"lut", "LUT",
- "Enable Lookup Table instructions (FEAT_LUT)">;
-
-def FeatureFP8 : Extension<"fp8", "FP8",
- "Enable FP8 instructions (FEAT_FP8)", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
-
-def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA",
- "Enable fp8 multiply-add instructions (FEAT_FP8FMA)", [FeatureFP8]>;
-
-let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA",
- "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2, FeatureFP8]>;
-
-def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
- "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>;
-
-def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2",
- "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>;
-
-let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
- "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSSVE_FP8FMA]>;
-
-let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
- "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSSVE_FP8DOT4]>;
-
-def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2",
- "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
-
-let FMVDependencies = "+sme2,+fp8" in
-def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32",
- "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
-
-let FMVDependencies = "+fp8,+sme2" in
-def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
- "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSMEF8F32]>;
-
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
"Apple A7 (the CPU formerly known as Cyclone)">;
@@ -707,9 +829,6 @@ def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
"Enable Exception Level 3">;
-def FeatureCSSC : Extension<"cssc", "CSSC",
- "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
-
def FeatureFixCortexA53_835769 : SubtargetFeature<"fix-cortex-a53-835769",
"FixCortexA53_835769", "true", "Mitigate Cortex-A53 Erratum 835769">;
@@ -718,49 +837,6 @@ def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
"Don't place a BTI instruction "
"after a return-twice">;
-def FeatureCHK : SubtargetFeature<"chk", "HasCHK",
- "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">;
-
-def FeatureGCS : Extension<"gcs", "GCS",
- "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
-
-def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB",
- "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">;
-
-def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC",
- "true", "Enable SLC target for PRFM instruction">;
-
-let MArchName = "predres2" in
-def FeatureSPECRES2 : Extension<"specres2", "SPECRES2",
- "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
- [FeaturePredRes]>;
-
-def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
- "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
-
-def FeatureITE : Extension<"ite", "ITE",
- "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE,
- FeatureTRBE]>;
-
-def FeatureRCPC3 : Extension<"rcpc3", "RCPC3",
- "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
- [FeatureRCPC_IMMO],
- "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
-
-def FeatureTHE : Extension<"the", "THE",
- "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
-
-def FeatureLSE128 : Extension<"lse128", "LSE128",
- "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
- [FeatureLSE]>;
-
-// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.
-// Therefore group them all under a single feature flag, d128:
-def FeatureD128 : Extension<"d128", "D128",
- "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
- "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
- [FeatureLSE128]>;
-
def FeatureDisableLdp : SubtargetFeature<"disable-ldp", "HasDisableLdp",
"true", "Do not emit ldp">;
@@ -773,18 +849,6 @@ def FeatureLdpAlignedOnly : SubtargetFeature<"ldp-aligned-only", "HasLdpAlignedO
def FeatureStpAlignedOnly : SubtargetFeature<"stp-aligned-only", "HasStpAlignedOnly",
"true", "In order to emit stp, first check if the store will be aligned to 2 * element_size">;
-// AArch64 2023 Architecture Extensions (v9.5-A)
-
-def FeatureCPA : Extension<"cpa", "CPA",
- "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
-
-def FeaturePAuthLR : Extension<"pauth-lr", "PAuthLR",
- "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
-
-def FeatureTLBIW : Extension<"tlbiw", "TLBIW",
- "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">;
-
-
//===----------------------------------------------------------------------===//
// Architectures.
//
>From f37f6fc2cc4704ed99c900c0d3f6a1a593683cd0 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Thu, 13 Jun 2024 16:08:54 +0100
Subject: [PATCH 2/9] [AArch64] Make TargetParser aware of all architecture
extensions
This updates the implementation in AArch64Features.td to make the
TargetParser aware of all of the architecture extensions declared
in TableGen. This change makes this information accessible to
other components and will allow the reduction of code duplication
and the expansion of the testability of targets in an upcoming
patch.
---
llvm/lib/Target/AArch64/AArch64Features.td | 457 +++++++++---------
llvm/lib/TargetParser/AArch64TargetParser.cpp | 4 +-
2 files changed, 227 insertions(+), 234 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 911a282e14936..92cb9df811e8f 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -33,11 +33,8 @@ class Extension<
{
string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.
- // In general, the name written on the command line should match the name
- // used for -target-feature. However, there are exceptions. Therefore we
- // add a separate field for this, to allow overriding it. Strongly prefer
- // not doing so.
- string MArchName = TargetFeatureName;
+ // By default, extensions are available as -march/-cpu command line options.
+ string MArchName = "";
// An alias that can be used on the command line, if the extension has one.
// Used for correcting historical names while remaining backwards compatible.
@@ -58,6 +55,23 @@ class Extension<
int FMVPriority = _FMVPriority;
}
+class ExtensionWithMArch<
+ string TargetFeatureName, // String used for -target-feature and -march, unless overridden.
+ string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
+ string Desc, // Description.
+ list<SubtargetFeature> Implies = [], // List of dependent features.
+ // FMV properties
+ string _FMVBit = "FEAT_INIT", // FEAT_INIT is repurposed to indicate "not an FMV feature"
+ string _FMVDependencies = "",
+ int _FMVPriority = 0
+> : Extension<TargetFeatureName, Spelling, Desc, Implies, _FMVBit, _FMVDependencies, _FMVPriority> {
+ // In general, the name written on the command line should match the name
+ // used for -target-feature. However, there are exceptions. Therefore we
+ // add a separate field for this, to allow overriding it. Strongly prefer
+ // not doing so.
+ let MArchName = TargetFeatureName;
+}
+
// Some extensions are available for FMV but can not be controlled via the
// command line. These entries:
// - are SubtargetFeatures, so they have (unused) FieldNames on the subtarget
@@ -72,6 +86,7 @@ class Extension<
class FMVOnlyExtension<string FMVBit, string Name, string Deps, int Priority>
: Extension<Name, "FMVOnly"#FMVBit, "", [], FMVBit, Deps, Priority> {
let ArchExtKindSpelling = "AEK_NONE"; // AEK_NONE indicates FMV-only feature
+ let MArchName = Name;
}
def : FMVOnlyExtension<"FEAT_DGH", "dgh", "", 260>;
@@ -107,24 +122,22 @@ def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-a
//===----------------------------------------------------------------------===//
let ArchExtKindSpelling = "AEK_FP", MArchName = "fp" in
-def FeatureFPARMv8 : Extension<"fp-armv8", "FPARMv8",
+def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8",
"Enable ARMv8 (FEAT_FP)", [],
"FEAT_FP", "+fp-armv8,+neon", 90>;
let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd" in
-def FeatureNEON : Extension<"neon", "NEON",
+def FeatureNEON : ExtensionWithMArch<"neon", "NEON",
"Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8],
"FEAT_SIMD", "+fp-armv8,+neon", 100>;
-def FeatureSHA2 : Extension<
- "sha2", "SHA2",
- "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON],
- "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
+def FeatureSHA2 : ExtensionWithMArch<"sha2", "SHA2",
+ "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON],
+ "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
-def FeatureAES : Extension<
- "aes", "AES",
- "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON],
- "FEAT_AES", "+fp-armv8,+neon", 150>;
+def FeatureAES : ExtensionWithMArch<"aes", "AES",
+ "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON],
+ "FEAT_AES", "+fp-armv8,+neon", 150>;
// Crypto has been split up and any combination is now valid (see the
// crypto definitions above). Also, crypto is now context sensitive:
@@ -135,10 +148,10 @@ def FeatureAES : Extension<
// compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto.
let FMVDependencies = "+aes,+sha2" in
-def FeatureCrypto : Extension<"crypto", "Crypto",
+def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
-def FeatureCRC : Extension<"crc", "CRC",
+def FeatureCRC : ExtensionWithMArch<"crc", "CRC",
"Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [],
"FEAT_CRC", "+crc", 110>;
@@ -146,307 +159,287 @@ def FeatureCRC : Extension<"crc", "CRC",
// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
let MArchName = "pmuv3" in
-def FeaturePerfMon : Extension<"perfmon", "PerfMon",
+def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon",
"Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
-def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
- "true", "Enable architectural speculation restriction (FEAT_CSV2_2)">;
+def FeatureSpecRestrict : Extension<"specrestrict", "SpecRestrict",
+ "Enable architectural speculation restriction (FEAT_CSV2_2)">;
//===----------------------------------------------------------------------===//
// Armv8.1 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureLSE : Extension<"lse", "LSE",
+def FeatureLSE : ExtensionWithMArch<"lse", "LSE",
"Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [],
"FEAT_LSE", "+lse", 80>;
let MArchAlias = "rdma" in
-def FeatureRDM : Extension<"rdm", "RDM",
+def FeatureRDM : ExtensionWithMArch<"rdm", "RDM",
"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)",
[FeatureNEON],
"FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
-def FeaturePAN : SubtargetFeature<
- "pan", "HasPAN", "true",
- "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">;
+def FeaturePAN : Extension<"pan", "PAN",
+ "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">;
-def FeatureLOR : SubtargetFeature<
- "lor", "HasLOR", "true",
- "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">;
+def FeatureLOR : Extension<"lor", "LOR",
+ "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">;
def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
"true", "Enable RW operand CONTEXTIDR_EL2" >;
-def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
- "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
+def FeatureVH : Extension<"vh", "VH",
+ "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
//===----------------------------------------------------------------------===//
// Armv8.2 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureSM4 : Extension<
- "sm4", "SM4",
- "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
- "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
+def FeatureSM4 : ExtensionWithMArch<"sm4", "SM4",
+ "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
+ "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
-def FeatureSHA3 : Extension<
- "sha3", "SHA3",
- "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2],
- "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
+def FeatureSHA3 : ExtensionWithMArch<"sha3", "SHA3",
+ "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2],
+ "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
-def FeatureRAS : Extension<"ras", "RAS",
+def FeatureRAS : ExtensionWithMArch<"ras", "RAS",
"Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in
-def FeatureFullFP16 : Extension<"fullfp16", "FullFP16",
+def FeatureFullFP16 : ExtensionWithMArch<"fullfp16", "FullFP16",
"Full FP16 (FEAT_FP16)", [FeatureFPARMv8],
"FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in
-def FeatureSPE : Extension<"spe", "SPE",
+def FeatureSPE : ExtensionWithMArch<"spe", "SPE",
"Enable Statistical Profiling extension (FEAT_SPE)">;
-def FeaturePAN_RWV : SubtargetFeature<
- "pan-rwv", "HasPAN_RWV", "true",
- "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)",
- [FeaturePAN]>;
+def FeaturePAN_RWV : Extension<"pan-rwv", "PAN_RWV",
+ "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", [FeaturePAN]>;
-def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
- "Enable v8.2 UAO PState (FEAT_UAO)">;
+def FeaturePsUAO : Extension<"uaops", "PsUAO",
+ "Enable v8.2 UAO PState (FEAT_UAO)">;
-def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
- "true", "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
+def FeatureCCPP : Extension<"ccpp", "CCPP",
+ "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
-def FeatureSVE : Extension<"sve", "SVE",
+def FeatureSVE : ExtensionWithMArch<"sve", "SVE",
"Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16],
"FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
let ArchExtKindSpelling = "AEK_I8MM" in
-def FeatureMatMulInt8 : Extension<"i8mm", "MatMulInt8",
- "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
- "FEAT_I8MM", "+i8mm", 270>;
+def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8",
+ "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
+ "FEAT_I8MM", "+i8mm", 270>;
let ArchExtKindSpelling = "AEK_F32MM" in
-def FeatureMatMulFP32 : Extension<"f32mm", "MatMulFP32",
- "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
- "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
+def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32",
+ "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
+ "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
let ArchExtKindSpelling = "AEK_F64MM" in
-def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64",
- "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
- "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
+def FeatureMatMulFP64 : ExtensionWithMArch<"f64mm", "MatMulFP64",
+ "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
+ "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
//===----------------------------------------------------------------------===//
// Armv8.3 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureRCPC : Extension<"rcpc", "RCPC",
- "Enable support for RCPC extension (FEAT_LRCPC)", [],
- "FEAT_RCPC", "+rcpc", 230>;
+def FeatureRCPC : ExtensionWithMArch<"rcpc", "RCPC",
+ "Enable support for RCPC extension (FEAT_LRCPC)", [],
+ "FEAT_RCPC", "+rcpc", 230>;
-def FeaturePAuth : Extension<
- "pauth", "PAuth",
- "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
+def FeaturePAuth : ExtensionWithMArch<"pauth", "PAuth",
+ "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
-def FeatureJS : Extension<
- "jsconv", "JS",
- "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
- [FeatureFPARMv8],
- "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
+def FeatureJS : ExtensionWithMArch<"jsconv", "JS",
+ "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
+ [FeatureFPARMv8],
+ "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
-def FeatureCCIDX : SubtargetFeature<
- "ccidx", "HasCCIDX", "true",
- "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
+def FeatureCCIDX : Extension<"ccidx", "CCIDX",
+ "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
-def FeatureComplxNum : Extension<
- "complxnum", "ComplxNum",
- "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
- [FeatureNEON],
- "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
+def FeatureComplxNum : ExtensionWithMArch<"complxnum", "ComplxNum",
+ "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
+ [FeatureNEON],
+ "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
-def FeatureNV : SubtargetFeature<
- "nv", "HasNV", "true",
- "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
+def FeatureNV : Extension<"nv", "NV",
+ "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
//===----------------------------------------------------------------------===//
// Armv8.4 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureLSE2 : SubtargetFeature<"lse2", "HasLSE2", "true",
+def FeatureLSE2 : Extension<"lse2", "LSE2",
"Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
-def FeatureFP16FML : Extension<"fp16fml", "FP16FML",
+def FeatureFP16FML : ExtensionWithMArch<"fp16fml", "FP16FML",
"Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
"FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
-def FeatureDotProd : Extension<
- "dotprod", "DotProd",
- "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
- "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
+def FeatureDotProd : ExtensionWithMArch<"dotprod", "DotProd",
+ "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
+ "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
-def FeatureMPAM : SubtargetFeature<
- "mpam", "HasMPAM", "true",
- "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
+def FeatureMPAM : Extension<"mpam", "MPAM",
+ "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
-def FeatureDIT : Extension<
- "dit", "DIT",
- "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", [],
- "FEAT_DIT", "+dit", 180>;
+def FeatureDIT : ExtensionWithMArch<"dit", "DIT",
+ "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", [],
+ "FEAT_DIT", "+dit", 180>;
-def FeatureTRACEV8_4 : SubtargetFeature<
- "tracev8.4", "HasTRACEV8_4", "true",
- "Enable v8.4-A Trace extension (FEAT_TRF)">;
+def FeatureTRACEV8_4 : Extension<"tracev8.4", "TRACEV8_4",
+ "Enable v8.4-A Trace extension (FEAT_TRF)">;
-def FeatureAM : SubtargetFeature<
- "am", "HasAM", "true",
- "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
+def FeatureAM : Extension<"am", "AM",
+ "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
-def FeatureSEL2 : SubtargetFeature<
- "sel2", "HasSEL2", "true",
- "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
+def FeatureSEL2 : Extension<"sel2", "SEL2",
+ "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
-def FeatureTLB_RMI : SubtargetFeature<
- "tlb-rmi", "HasTLB_RMI", "true",
- "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
+def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI",
+ "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
-def FeatureFlagM : Extension<
- "flagm", "FlagM",
- "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
- "FEAT_FLAGM", "+flagm", 20>;
+def FeatureFlagM : ExtensionWithMArch<"flagm", "FlagM",
+ "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
+ "FEAT_FLAGM", "+flagm", 20>;
-def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
- "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
- [FeatureRCPC]>;
+def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO",
+ "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
+ [FeatureRCPC]>;
//===----------------------------------------------------------------------===//
// Armv8.5 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
+def FeatureAltFPCmp : Extension<"altnzcv", "AlternativeNZCV",
"Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">;
-def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
+def FeatureFRInt3264 : Extension<"fptoint", "FRInt3264",
"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
"an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >;
-def FeatureSB : Extension<"sb", "SB",
+def FeatureSB : ExtensionWithMArch<"sb", "SB",
"Enable v8.5 Speculation Barrier (FEAT_SB)", [],
"FEAT_SB", "+sb", 470>;
-def FeatureSSBS : Extension<"ssbs", "SSBS",
+def FeatureSSBS : ExtensionWithMArch<"ssbs", "SSBS",
"Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [],
"FEAT_SSBS", "", 490>;
-def FeaturePredRes : Extension<"predres", "PredRes",
+def FeaturePredRes : ExtensionWithMArch<"predres", "PredRes",
"Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [],
"FEAT_PREDRES", "+predres", 480>;
-def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "CCDP", "true",
- "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
+def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP",
+ "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
let ArchExtKindSpelling = "AEK_NONE" in
-def FeatureBranchTargetId : Extension<"bti", "BTI",
- "Enable Branch Target Identification (FEAT_BTI)", [],
- "FEAT_BTI", "+bti", 510>;
+def FeatureBranchTargetId : ExtensionWithMArch<"bti", "BTI",
+ "Enable Branch Target Identification (FEAT_BTI)", [],
+ "FEAT_BTI", "+bti", 510>;
let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
-def FeatureRandGen : Extension<"rand", "RandGen",
- "Enable Random Number generation instructions (FEAT_RNG)", [],
- "FEAT_RNG", "+rand", 10>;
+def FeatureRandGen : ExtensionWithMArch<"rand", "RandGen",
+ "Enable Random Number generation instructions (FEAT_RNG)", [],
+ "FEAT_RNG", "+rand", 10>;
// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
// __attribute((target(...))), but only FEAT_MTE for FMV.
let MArchName = "memtag" in
-def FeatureMTE : Extension<"mte", "MTE",
- "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
- "FEAT_MEMTAG", "", 440>;
+def FeatureMTE : ExtensionWithMArch<"mte", "MTE",
+ "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
+ "FEAT_MEMTAG", "", 440>;
//===----------------------------------------------------------------------===//
// Armv8.6 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureBF16 : Extension<"bf16", "BF16",
- "Enable BFloat16 Extension (FEAT_BF16)", [],
- "FEAT_BF16", "+bf16", 280>;
+def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16",
+ "Enable BFloat16 Extension (FEAT_BF16)", [],
+ "FEAT_BF16", "+bf16", 280>;
-def FeatureAMVS : SubtargetFeature<
- "amvs", "HasAMVS", "true",
- "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
- [FeatureAM]>;
+def FeatureAMVS : Extension<"amvs", "AMVS",
+ "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
+ [FeatureAM]>;
-def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
- "true", "Enable fine grained virtualization traps extension (FEAT_FGT)">;
+def FeatureFineGrainedTraps : Extension<"fgt", "FineGrainedTraps",
+ "Enable fine grained virtualization traps extension (FEAT_FGT)">;
def FeatureEnhancedCounterVirtualization :
- SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
- "true", "Enable enhanced counter virtualization extension (FEAT_ECV)">;
+ Extension<"ecv", "EnhancedCounterVirtualization",
+ "Enable enhanced counter virtualization extension (FEAT_ECV)">;
//===----------------------------------------------------------------------===//
// Armv8.7 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureXS : SubtargetFeature<"xs", "HasXS",
- "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
+def FeatureXS : Extension<"xs", "XS",
+ "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
-def FeatureWFxT : Extension<"wfxt", "WFxT",
- "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [],
- "FEAT_WFXT", "+wfxt", 550>;
+def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT",
+ "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [],
+ "FEAT_WFXT", "+wfxt", 550>;
-def FeatureHCX : SubtargetFeature<
- "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
+def FeatureHCX : Extension<"hcx", "HCX",
+ "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
-def FeatureLS64 : Extension<"ls64", "LS64",
- "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
- "FEAT_LS64", "", 520>;
+def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
+ "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
+ "FEAT_LS64", "", 520>;
-def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
- "true", "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
+def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF",
+ "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
//===----------------------------------------------------------------------===//
// Armv8.8 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureHBC : Extension<"hbc", "HBC",
+def FeatureHBC : ExtensionWithMArch<"hbc", "HBC",
"Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
-def FeatureMOPS : Extension<"mops", "MOPS",
+def FeatureMOPS : ExtensionWithMArch<"mops", "MOPS",
"Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", [],
"FEAT_MOPS", "+mops", 650>;
-def FeatureNMI : SubtargetFeature<"nmi", "HasNMI",
- "true", "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
+def FeatureNMI : Extension<"nmi", "NMI",
+ "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
//===----------------------------------------------------------------------===//
// Armv8.9 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureRASv2 : Extension<"rasv2", "RASv2",
+def FeatureRASv2 : ExtensionWithMArch<"rasv2", "RASv2",
"Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
[FeatureRAS]>;
-def FeatureCSSC : Extension<"cssc", "CSSC",
+def FeatureCSSC : ExtensionWithMArch<"cssc", "CSSC",
"Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
-def FeatureCLRBHB : SubtargetFeature<"clrbhb", "HasCLRBHB",
- "true", "Enable Clear BHB instruction (FEAT_CLRBHB)">;
+def FeatureCLRBHB : Extension<"clrbhb", "CLRBHB",
+ "Enable Clear BHB instruction (FEAT_CLRBHB)">;
-def FeaturePRFM_SLC : SubtargetFeature<"prfm-slc-target", "HasPRFM_SLC",
- "true", "Enable SLC target for PRFM instruction">;
+def FeaturePRFM_SLC : Extension<"prfm-slc-target", "PRFM_SLC",
+ "Enable SLC target for PRFM instruction">;
let MArchName = "predres2" in
-def FeatureSPECRES2 : Extension<"specres2", "SPECRES2",
- "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
- [FeaturePredRes]>;
+def FeatureSPECRES2 : ExtensionWithMArch<"specres2", "SPECRES2",
+ "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
+ [FeaturePredRes]>;
-def FeatureRCPC3 : Extension<"rcpc3", "RCPC3",
- "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
- [FeatureRCPC_IMMO],
- "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
+def FeatureRCPC3 : ExtensionWithMArch<"rcpc3", "RCPC3",
+ "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
+ [FeatureRCPC_IMMO],
+ "FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
-def FeatureTHE : Extension<"the", "THE",
- "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
+def FeatureTHE : ExtensionWithMArch<"the", "THE",
+ "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
//===----------------------------------------------------------------------===//
// Armv9.0 Architecture Extensions
@@ -455,37 +448,36 @@ def FeatureTHE : Extension<"the", "THE",
def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
"UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
-def FeatureSVE2 : Extension<"sve2", "SVE2",
+def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2",
"Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
[FeatureSVE, FeatureUseScalarIncVL],
"FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
-def FeatureSVE2AES : Extension<"sve2-aes", "SVE2AES",
+def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
"Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
[FeatureSVE2, FeatureAES],
"FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
-def FeatureSVE2SM4 : Extension<"sve2-sm4", "SVE2SM4",
+def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4",
"Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4],
"FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
-def FeatureSVE2SHA3 : Extension<"sve2-sha3", "SVE2SHA3",
+def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3",
"Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3],
"FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
-def FeatureSVE2BitPerm : Extension<"sve2-bitperm", "SVE2BitPerm",
+def FeatureSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",
"Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
"FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
-def FeatureTRBE : SubtargetFeature<"trbe", "TRBE", "true",
- "Enable Trace Buffer Extension (FEAT_TRBE)">;
+def FeatureTRBE : Extension<"trbe", "TRBE",
+ "Enable Trace Buffer Extension (FEAT_TRBE)">;
-def FeatureETE : SubtargetFeature<"ete", "ETE", "true",
- "Enable Embedded Trace Extension (FEAT_ETE)",
- [FeatureTRBE]>;
+def FeatureETE : Extension<"ete", "ETE",
+ "Enable Embedded Trace Extension (FEAT_ETE)", [FeatureTRBE]>;
-def FeatureTME : Extension<"tme", "TME",
- "Enable Transactional Memory Extension (FEAT_TME)" >;
+def FeatureTME : ExtensionWithMArch<"tme", "TME",
+ "Enable Transactional Memory Extension (FEAT_TME)">;
//===----------------------------------------------------------------------===//
// Armv9.1 Architecture Extensions
@@ -495,130 +487,129 @@ def FeatureTME : Extension<"tme", "TME",
// Armv9.2 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureBRBE : Extension<"brbe", "BRBE",
- "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
+def FeatureBRBE : ExtensionWithMArch<"brbe", "BRBE",
+ "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
-def FeatureRME : SubtargetFeature<"rme", "HasRME",
- "true", "Enable Realm Management Extension (FEAT_RME)">;
+def FeatureRME : Extension<"rme", "RME",
+ "Enable Realm Management Extension (FEAT_RME)">;
-def FeatureSME : Extension<"sme", "SME",
+def FeatureSME : ExtensionWithMArch<"sme", "SME",
"Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL],
"FEAT_SME", "+sme,+bf16", 430>;
-def FeatureSMEF64F64 : Extension<"sme-f64f64", "SMEF64F64",
+def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64",
"Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME],
"FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
-def FeatureSMEI16I64 : Extension<"sme-i16i64", "SMEI16I64",
+def FeatureSMEI16I64 : ExtensionWithMArch<"sme-i16i64", "SMEI16I64",
"Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME],
"FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
-def FeatureSMEFA64 : Extension<"sme-fa64", "SMEFA64",
+def FeatureSMEFA64 : ExtensionWithMArch<"sme-fa64", "SMEFA64",
"Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>;
//===----------------------------------------------------------------------===//
// Armv9.3 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureSME2 : Extension<"sme2", "SME2",
+def FeatureSME2 : ExtensionWithMArch<"sme2", "SME2",
"Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
"FEAT_SME2", "+sme2,+sme,+bf16", 580>;
-def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
- "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
+def FeatureMEC : Extension<"mec", "MEC",
+ "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
//===----------------------------------------------------------------------===//
// Armv9.4 Architecture Extensions
//===----------------------------------------------------------------------===//
let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in
-def FeatureSVE2p1: Extension<"sve2p1", "SVE2p1",
+def FeatureSVE2p1: ExtensionWithMArch<"sve2p1", "SVE2p1",
"Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
-def FeatureB16B16 : Extension<"b16b16", "B16B16",
+def FeatureB16B16 : ExtensionWithMArch<"b16b16", "B16B16",
"Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>;
let FMVDependencies = "+sme2,+sme-f16f16" in
-def FeatureSMEF16F16 : Extension<"sme-f16f16", "SMEF16F16",
+def FeatureSMEF16F16 : ExtensionWithMArch<"sme-f16f16", "SMEF16F16",
"Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>;
let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in
-def FeatureSME2p1 : Extension<"sme2p1", "SME2p1",
+def FeatureSME2p1 : ExtensionWithMArch<"sme2p1", "SME2p1",
"Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>;
-def FeatureCHK : SubtargetFeature<"chk", "HasCHK",
- "true", "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">;
+def FeatureCHK : Extension<"chk", "CHK",
+ "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">;
-def FeatureGCS : Extension<"gcs", "GCS",
- "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
+def FeatureGCS : ExtensionWithMArch<"gcs", "GCS",
+ "Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
-def FeatureITE : Extension<"ite", "ITE",
- "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE,
- FeatureTRBE]>;
+def FeatureITE : ExtensionWithMArch<"ite", "ITE",
+ "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, FeatureTRBE]>;
-def FeatureLSE128 : Extension<"lse128", "LSE128",
- "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
- [FeatureLSE]>;
+def FeatureLSE128 : ExtensionWithMArch<"lse128", "LSE128",
+ "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
+ [FeatureLSE]>;
// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.
// Therefore group them all under a single feature flag, d128:
-def FeatureD128 : Extension<"d128", "D128",
- "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
- "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
- [FeatureLSE128]>;
+def FeatureD128 : ExtensionWithMArch<"d128", "D128",
+ "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
+ "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
+ [FeatureLSE128]>;
//===----------------------------------------------------------------------===//
// Armv9.5 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX",
- "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
+def FeatureFAMINMAX: ExtensionWithMArch<"faminmax", "FAMINMAX",
+ "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
-def FeatureLUT: Extension<"lut", "LUT",
- "Enable Lookup Table instructions (FEAT_LUT)">;
+def FeatureLUT: ExtensionWithMArch<"lut", "LUT",
+ "Enable Lookup Table instructions (FEAT_LUT)">;
-def FeatureFP8 : Extension<"fp8", "FP8",
+def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8",
"Enable FP8 instructions (FEAT_FP8)", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
-def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA",
+def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA",
"Enable fp8 multiply-add instructions (FEAT_FP8FMA)", [FeatureFP8]>;
let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA",
+def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA",
"Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2, FeatureFP8]>;
-def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
- "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>;
+def FeatureFP8DOT4: ExtensionWithMArch<"fp8dot4", "FP8DOT4",
+ "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>;
-def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2",
- "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>;
+def FeatureFP8DOT2: ExtensionWithMArch<"fp8dot2", "FP8DOT2",
+ "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>;
let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
+def FeatureSSVE_FP8DOT4 : ExtensionWithMArch<"ssve-fp8dot4", "SSVE_FP8DOT4",
"Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSSVE_FP8FMA]>;
let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
+def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2",
"Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSSVE_FP8DOT4]>;
-def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2",
+def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2",
"Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
let FMVDependencies = "+sme2,+fp8" in
-def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32",
+def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32",
"Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
let FMVDependencies = "+fp8,+sme2" in
-def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
+def FeatureSMEF8F16 : ExtensionWithMArch<"sme-f8f16", "SMEF8F16",
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSMEF8F32]>;
-def FeatureCPA : Extension<"cpa", "CPA",
- "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+def FeatureCPA : ExtensionWithMArch<"cpa", "CPA",
+ "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
-def FeaturePAuthLR : Extension<"pauth-lr", "PAuthLR",
- "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+def FeaturePAuthLR : ExtensionWithMArch<"pauth-lr", "PAuthLR",
+ "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
-def FeatureTLBIW : Extension<"tlbiw", "TLBIW",
+def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW",
"Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index ca356ec82bf1f..b10535eda857e 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -116,6 +116,8 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
std::optional<AArch64::ExtensionInfo>
AArch64::parseArchExtension(StringRef ArchExt) {
for (const auto &A : Extensions) {
+ if (A.Name.empty() && !A.Alias)
+ continue;
if (ArchExt == A.Name || ArchExt == A.Alias)
return A;
}
@@ -140,7 +142,7 @@ void AArch64::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
<< (DescMap.empty() ? "\n" : "Description\n");
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
- if (!Ext.Feature.empty()) {
+ if (!Ext.Name.empty() && !Ext.Feature.empty()) {
std::string Description = DescMap[Ext.Name].str();
outs() << " "
<< format(Description.empty() ? "%s\n" : "%-20s%s\n",
>From 696db2a6d83f76ee47420a0ba6812bf5c5dcbe54 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Fri, 14 Jun 2024 14:22:01 +0100
Subject: [PATCH 3/9] [NFC][AArch64] Rename TargetParser's ExtensionInfo fields
This renames some of the fields in AArchte64TargetParser's ExtensionInfo
struct to better reflect their use cases and improve readability.
---
clang/lib/Basic/Targets/AArch64.cpp | 2 +-
clang/lib/CodeGen/Targets/AArch64.cpp | 4 ++--
clang/lib/Driver/ToolChain.cpp | 8 +++----
clang/lib/Driver/ToolChains/Clang.cpp | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 6 ++---
llvm/lib/TargetParser/AArch64TargetParser.cpp | 24 +++++++++----------
6 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index e125ad551f098..b2c3e839b7e6c 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1101,7 +1101,7 @@ bool AArch64TargetInfo::initFeatureMap(
std::optional<llvm::AArch64::ExtensionInfo> Extension =
llvm::AArch64::parseArchExtension(Feature.substr(1));
if (Extension)
- UpdatedFeature = Extension->Feature.str();
+ UpdatedFeature = Extension->TargetFeature.str();
}
UpdatedFeaturesVec.push_back(UpdatedFeature);
}
diff --git a/clang/lib/CodeGen/Targets/AArch64.cpp b/clang/lib/CodeGen/Targets/AArch64.cpp
index cfb4b5f58ef72..51a7221db8b83 100644
--- a/clang/lib/CodeGen/Targets/AArch64.cpp
+++ b/clang/lib/CodeGen/Targets/AArch64.cpp
@@ -966,8 +966,8 @@ void AArch64ABIInfo::appendAttributeMangling(StringRef AttrStr,
llvm::SmallDenseSet<StringRef, 8> UniqueFeats;
for (auto &Feat : Features)
if (auto Ext = llvm::AArch64::parseArchExtension(Feat))
- if (UniqueFeats.insert(Ext->Name).second)
- Out << 'M' << Ext->Name;
+ if (UniqueFeats.insert(Ext->UserVisibleName).second)
+ Out << 'M' << Ext->UserVisibleName;
}
std::unique_ptr<TargetCodeGenInfo>
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index 40ab2e91125d1..a6f7ffaa0e7b1 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -195,11 +195,11 @@ static void getAArch64MultilibFlags(const Driver &D,
UnifiedFeatures.end());
std::vector<std::string> MArch;
for (const auto &Ext : AArch64::Extensions)
- if (FeatureSet.contains(Ext.Feature))
- MArch.push_back(Ext.Name.str());
+ if (FeatureSet.contains(Ext.TargetFeature))
+ MArch.push_back(Ext.UserVisibleName.str());
for (const auto &Ext : AArch64::Extensions)
- if (FeatureSet.contains(Ext.NegFeature))
- MArch.push_back(("no" + Ext.Name).str());
+ if (FeatureSet.contains(Ext.NegTargetFeature))
+ MArch.push_back(("no" + Ext.UserVisibleName).str());
StringRef ArchName;
for (const auto &ArchInfo : AArch64::ArchInfos)
if (FeatureSet.contains(ArchInfo->ArchFeature))
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 331cf6e713d89..719ec1b41859b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1523,7 +1523,7 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args,
auto isPAuthLR = [](const char *member) {
llvm::AArch64::ExtensionInfo pauthlr_extension =
llvm::AArch64::getExtensionByID(llvm::AArch64::AEK_PAUTHLR);
- return pauthlr_extension.Feature == member;
+ return pauthlr_extension.TargetFeature == member;
};
if (std::any_of(CmdArgs.begin(), CmdArgs.end(), isPAuthLR))
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index c1a68a0ec5c19..44d739aa8f1c4 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -114,12 +114,12 @@ using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef Name; // Human readable name, e.g. "profile".
+ StringRef UserVisibleName; // Human readable name used in -march/-cpu, e.g. "profile"
std::optional<StringRef> Alias; // An alias for this extension, if one exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
- StringRef Feature; // -mattr enable string, e.g. "+spe"
- StringRef NegFeature; // -mattr disable string, e.g. "-spe"
+ StringRef TargetFeature; // -target-feature/-mattr enable string, e.g. "+spe"
+ StringRef NegTargetFeature; // -target-feature/-mattr disable string, e.g. "-spe"
CPUFeatures CPUFeature; // Function Multi Versioning (FMV) bitfield value
// set in __aarch64_cpu_features
StringRef DependentFeatures; // FMV enabled features string,
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index b10535eda857e..360cc68c74c96 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -61,8 +61,8 @@ bool AArch64::getExtensionFeatures(
std::vector<StringRef> &Features) {
for (const auto &E : Extensions)
/* INVALID and NONE have no feature name. */
- if (InputExts.test(E.ID) && !E.Feature.empty())
- Features.push_back(E.Feature);
+ if (InputExts.test(E.ID) && !E.TargetFeature.empty())
+ Features.push_back(E.TargetFeature);
return true;
}
@@ -80,7 +80,7 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
if (auto AE = parseArchExtension(ArchExtBase)) {
// Note: the returned string can be empty.
- return IsNegated ? AE->NegFeature : AE->Feature;
+ return IsNegated ? AE->NegTargetFeature : AE->TargetFeature;
}
return StringRef();
@@ -116,9 +116,9 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
std::optional<AArch64::ExtensionInfo>
AArch64::parseArchExtension(StringRef ArchExt) {
for (const auto &A : Extensions) {
- if (A.Name.empty() && !A.Alias)
+ if (A.UserVisibleName.empty() && !A.Alias)
continue;
- if (ArchExt == A.Name || ArchExt == A.Alias)
+ if (ArchExt == A.UserVisibleName || ArchExt == A.Alias)
return A;
}
return {};
@@ -142,11 +142,11 @@ void AArch64::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
<< (DescMap.empty() ? "\n" : "Description\n");
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
- if (!Ext.Name.empty() && !Ext.Feature.empty()) {
- std::string Description = DescMap[Ext.Name].str();
+ if (!Ext.UserVisibleName.empty() && !Ext.TargetFeature.empty()) {
+ std::string Description = DescMap[Ext.UserVisibleName].str();
outs() << " "
<< format(Description.empty() ? "%s\n" : "%-20s%s\n",
- Ext.Name.str().c_str(), Description.c_str());
+ Ext.UserVisibleName.str().c_str(), Description.c_str());
}
}
}
@@ -221,12 +221,12 @@ void AArch64::ExtensionSet::toLLVMFeatureList(
Features.push_back(BaseArch->ArchFeature);
for (const auto &E : Extensions) {
- if (E.Feature.empty() || !Touched.test(E.ID))
+ if (E.TargetFeature.empty() || !Touched.test(E.ID))
continue;
if (Enabled.test(E.ID))
- Features.push_back(E.Feature);
+ Features.push_back(E.TargetFeature);
else
- Features.push_back(E.NegFeature);
+ Features.push_back(E.NegTargetFeature);
}
}
@@ -256,7 +256,7 @@ bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) {
StringRef ArchExt = IsNegated ? Modifier.drop_front(2) : Modifier;
if (auto AE = parseArchExtension(ArchExt)) {
- if (AE->Feature.empty() || AE->NegFeature.empty())
+ if (AE->TargetFeature.empty() || AE->NegTargetFeature.empty())
return false;
if (IsNegated)
disable(AE->ID);
>From abce5db3f8da718944fd9a9c9af7fd9b817b5ff5 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Fri, 14 Jun 2024 16:54:39 +0100
Subject: [PATCH 4/9] [NFC][AArch64] Make extension descriptions available in
TargetParser
This introduces a new field to AArch64TargetParser's ExtensionInfo
struct that contains the extension description from the TableGen record.
This allows us to simplify the information flow for functionality such
as '--print-supported-extensions'.
---
clang/tools/driver/cc1_main.cpp | 2 +-
llvm/include/llvm/TargetParser/AArch64TargetParser.h | 3 ++-
llvm/lib/TargetParser/AArch64TargetParser.cpp | 10 +++++-----
llvm/unittests/TargetParser/TargetParserTest.cpp | 10 ++--------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 3 ++-
5 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 2aebc6d3c0178..3c008d2386482 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -148,7 +148,7 @@ static int PrintSupportedExtensions(std::string TargetStr) {
if (MachineTriple.isRISCV())
llvm::riscvExtensionsHelp(DescMap);
else if (MachineTriple.isAArch64())
- llvm::AArch64::PrintSupportedExtensions(DescMap);
+ llvm::AArch64::PrintSupportedExtensions();
else if (MachineTriple.isARM())
llvm::ARM::PrintSupportedExtensions(DescMap);
else {
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 44d739aa8f1c4..56a29895aa4d1 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -118,6 +118,7 @@ struct ExtensionInfo {
std::optional<StringRef> Alias; // An alias for this extension, if one exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
+ StringRef Description; // The textual description of the extension
StringRef TargetFeature; // -target-feature/-mattr enable string, e.g. "+spe"
StringRef NegTargetFeature; // -target-feature/-mattr disable string, e.g. "-spe"
CPUFeatures CPUFeature; // Function Multi Versioning (FMV) bitfield value
@@ -639,7 +640,7 @@ bool isX18ReservedByDefault(const Triple &TT);
// themselves, they are sequential (0, 1, 2, 3, ...).
uint64_t getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
-void PrintSupportedExtensions(StringMap<StringRef> DescMap);
+void PrintSupportedExtensions();
} // namespace AArch64
} // namespace llvm
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 360cc68c74c96..c9c6965efb630 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -136,17 +136,17 @@ std::optional<AArch64::CpuInfo> AArch64::parseCpu(StringRef Name) {
return {};
}
-void AArch64::PrintSupportedExtensions(StringMap<StringRef> DescMap) {
+void AArch64::PrintSupportedExtensions() {
outs() << "All available -march extensions for AArch64\n\n"
<< " " << left_justify("Name", 20)
- << (DescMap.empty() ? "\n" : "Description\n");
+ << "Description\n";
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
if (!Ext.UserVisibleName.empty() && !Ext.TargetFeature.empty()) {
- std::string Description = DescMap[Ext.UserVisibleName].str();
outs() << " "
- << format(Description.empty() ? "%s\n" : "%-20s%s\n",
- Ext.UserVisibleName.str().c_str(), Description.c_str());
+ << format(Ext.Description.empty() ? "%s\n" : "%-20s%s\n",
+ Ext.UserVisibleName.str().c_str(),
+ Ext.Description.str().c_str());
}
}
}
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 78efa6e5332c4..4cc9bae522339 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2316,17 +2316,11 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
TEST(TargetParserTest, AArch64PrintSupportedExtensions) {
std::string expected =
"All available -march extensions for AArch64\n\n"
- " Name Description\n"
- " aes This is a long dummy description\n"
- " b16b16\n"
- " bf16\n";
-
- StringMap<StringRef> DummyMap;
- DummyMap["aes"] = "This is a long dummy description";
+ " Name Description\n";
outs().flush();
testing::internal::CaptureStdout();
- AArch64::PrintSupportedExtensions(DummyMap);
+ AArch64::PrintSupportedExtensions();
outs().flush();
std::string captured = testing::internal::GetCapturedStdout();
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 5efa7d2722d3f..76054982c68a1 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -97,6 +97,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
else
OS << ", \"" << Alias << "\"";
OS << ", AArch64::" << AEK;
+ OS << ", \"" << Rec->getValueAsString("Desc") << "\"";
if (AEK == "AEK_NONE") {
// HACK: don't emit posfeat/negfeat strings for FMVOnlyExtensions.
OS << ", {}, {}";
@@ -109,7 +110,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << ", " << (uint64_t)Rec->getValueAsInt("FMVPriority");
OS << "},\n";
};
- OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {}, FEAT_INIT, \"\", "
+ OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {}, {}, FEAT_INIT, \"\", "
"ExtensionInfo::MaxFMVPriority},\n";
OS << "};\n"
<< "#undef EMIT_EXTENSIONS\n"
>From 8878b269b6b95178474371eb12d89ab1df149c2a Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Fri, 14 Jun 2024 16:40:13 +0100
Subject: [PATCH 5/9] [AArch64][TargetParser] Add field for FEAT_* feature
names to ExtensionInfo
This introduces a new textual field for the Architecture Feature names
to the AArch64 extensions in TableGen and TargetParser. So far, any
cross references between the extensions in the implementation and the
ones from the ISA has been covered only by the free text in ther
'Description' field. The new field adds a reliable and explicit mapping
between them, and enables enhancements in testability that will be
implemented in an upcoming patch.
---
.../test/Driver/print-supported-extensions.c | 4 +-
.../llvm/TargetParser/AArch64TargetParser.h | 1 +
llvm/lib/Target/AArch64/AArch64Features.td | 436 +++++++++---------
llvm/lib/TargetParser/AArch64TargetParser.cpp | 4 +-
.../TargetParser/TargetParserTest.cpp | 2 +-
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 3 +-
6 files changed, 229 insertions(+), 221 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions.c b/clang/test/Driver/print-supported-extensions.c
index 17894fc0f7ee0..b9b16352f8295 100644
--- a/clang/test/Driver/print-supported-extensions.c
+++ b/clang/test/Driver/print-supported-extensions.c
@@ -4,8 +4,8 @@
// RUN: %if aarch64-registered-target %{ %clang --target=aarch64-linux-gnu \
// RUN: --print-supported-extensions 2>&1 | FileCheck %s --check-prefix AARCH64 %}
// AARCH64: All available -march extensions for AArch64
-// AARCH64: Name Description
-// AARCH64: aes Enable AES support (FEAT_AES, FEAT_PMULL)
+// AARCH64: Name Architecture Feature(s) Description
+// AARCH64: aes FEAT_AES, FEAT_PMULL Enable AES support
// RUN: %if riscv-registered-target %{ %clang --target=riscv64-linux-gnu \
// RUN: --print-supported-extensions 2>&1 | FileCheck %s --check-prefix RISCV %}
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 56a29895aa4d1..bdcb02770c40b 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -118,6 +118,7 @@ struct ExtensionInfo {
std::optional<StringRef> Alias; // An alias for this extension, if one exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
+ StringRef ArchFeatureName; // The feature name defined by the Architecture
StringRef Description; // The textual description of the extension
StringRef TargetFeature; // -target-feature/-mattr enable string, e.g. "+spe"
StringRef NegTargetFeature; // -target-feature/-mattr disable string, e.g. "-spe"
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 92cb9df811e8f..f62816b529b0e 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -23,6 +23,7 @@
class Extension<
string TargetFeatureName, // String used for -target-feature and -march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
+ string ArchitectureFeatureName, // The extension's "FEAT_*"" name(s) defined by the architecture
string Desc, // Description.
list<SubtargetFeature> Implies = [], // List of dependent features.
// FMV properties
@@ -33,6 +34,8 @@ class Extension<
{
string ArchExtKindSpelling = "AEK_" # Spelling; // ArchExtKind enum name.
+ string ArchFeatureName = ArchitectureFeatureName;
+
// By default, extensions are available as -march/-cpu command line options.
string MArchName = "";
@@ -58,13 +61,14 @@ class Extension<
class ExtensionWithMArch<
string TargetFeatureName, // String used for -target-feature and -march, unless overridden.
string Spelling, // The XYZ in HasXYZ and AEK_XYZ.
+ string ArchitectureFeatureName, // The extension's "FEAT_*"" name(s) defined by the architecture
string Desc, // Description.
list<SubtargetFeature> Implies = [], // List of dependent features.
// FMV properties
string _FMVBit = "FEAT_INIT", // FEAT_INIT is repurposed to indicate "not an FMV feature"
string _FMVDependencies = "",
int _FMVPriority = 0
-> : Extension<TargetFeatureName, Spelling, Desc, Implies, _FMVBit, _FMVDependencies, _FMVPriority> {
+> : Extension<TargetFeatureName, Spelling, ArchitectureFeatureName, Desc, Implies, _FMVBit, _FMVDependencies, _FMVPriority> {
// In general, the name written on the command line should match the name
// used for -target-feature. However, there are exceptions. Therefore we
// add a separate field for this, to allow overriding it. Strongly prefer
@@ -84,7 +88,7 @@ class ExtensionWithMArch<
// used to indicate that a feature is FMV only. Therefore ArchExtKindSpelling is
// manually overridden here.
class FMVOnlyExtension<string FMVBit, string Name, string Deps, int Priority>
- : Extension<Name, "FMVOnly"#FMVBit, "", [], FMVBit, Deps, Priority> {
+ : Extension<Name, "FMVOnly"#FMVBit, "", "", [], FMVBit, Deps, Priority> {
let ArchExtKindSpelling = "AEK_NONE"; // AEK_NONE indicates FMV-only feature
let MArchName = Name;
}
@@ -122,21 +126,21 @@ def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-a
//===----------------------------------------------------------------------===//
let ArchExtKindSpelling = "AEK_FP", MArchName = "fp" in
-def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8",
- "Enable ARMv8 (FEAT_FP)", [],
+def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8", "FEAT_FP",
+ "Enable ARMv8", [],
"FEAT_FP", "+fp-armv8,+neon", 90>;
let ArchExtKindSpelling = "AEK_SIMD", MArchName = "simd" in
-def FeatureNEON : ExtensionWithMArch<"neon", "NEON",
- "Enable Advanced SIMD instructions (FEAT_AdvSIMD)", [FeatureFPARMv8],
+def FeatureNEON : ExtensionWithMArch<"neon", "NEON", "FEAT_AdvSIMD",
+ "Enable Advanced SIMD instructions", [FeatureFPARMv8],
"FEAT_SIMD", "+fp-armv8,+neon", 100>;
-def FeatureSHA2 : ExtensionWithMArch<"sha2", "SHA2",
- "Enable SHA1 and SHA256 support (FEAT_SHA1, FEAT_SHA256)", [FeatureNEON],
+def FeatureSHA2 : ExtensionWithMArch<"sha2", "SHA2", "FEAT_SHA1, FEAT_SHA256",
+ "Enable SHA1 and SHA256 support", [FeatureNEON],
"FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>;
-def FeatureAES : ExtensionWithMArch<"aes", "AES",
- "Enable AES support (FEAT_AES, FEAT_PMULL)", [FeatureNEON],
+def FeatureAES : ExtensionWithMArch<"aes", "AES", "FEAT_AES, FEAT_PMULL",
+ "Enable AES support", [FeatureNEON],
"FEAT_AES", "+fp-armv8,+neon", 150>;
// Crypto has been split up and any combination is now valid (see the
@@ -148,298 +152,298 @@ def FeatureAES : ExtensionWithMArch<"aes", "AES",
// compatibility, and now imply features SHA2 and AES, which was the
// "traditional" meaning of Crypto.
let FMVDependencies = "+aes,+sha2" in
-def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto",
+def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto", "FEAT_Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
-def FeatureCRC : ExtensionWithMArch<"crc", "CRC",
- "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)", [],
+def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32",
+ "Enable ARMv8 CRC-32 checksum instructions", [],
"FEAT_CRC", "+crc", 110>;
// This SubtargetFeature is special. It controls only whether codegen will turn
// `llvm.readcyclecounter()` into an access to a PMUv3 System Register. The
// `FEAT_PMUv3*` system registers are always available for assembly/disassembly.
let MArchName = "pmuv3" in
-def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon",
- "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)">;
+def FeaturePerfMon : ExtensionWithMArch<"perfmon", "PerfMon", "FEAT_PMUv3",
+ "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension">;
-def FeatureSpecRestrict : Extension<"specrestrict", "SpecRestrict",
- "Enable architectural speculation restriction (FEAT_CSV2_2)">;
+def FeatureSpecRestrict : Extension<"specrestrict", "SpecRestrict", "FEAT_CSV2_2",
+ "Enable architectural speculation restriction">;
//===----------------------------------------------------------------------===//
// Armv8.1 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureLSE : ExtensionWithMArch<"lse", "LSE",
- "Enable ARMv8.1 Large System Extension (LSE) atomic instructions (FEAT_LSE)", [],
+def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE",
+ "Enable ARMv8.1 Large System Extension (LSE) atomic instructions", [],
"FEAT_LSE", "+lse", 80>;
let MArchAlias = "rdma" in
-def FeatureRDM : ExtensionWithMArch<"rdm", "RDM",
- "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions (FEAT_RDM)",
+def FeatureRDM : ExtensionWithMArch<"rdm", "RDM", "FEAT_RDM",
+ "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions",
[FeatureNEON],
"FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>;
-def FeaturePAN : Extension<"pan", "PAN",
- "Enables ARM v8.1 Privileged Access-Never extension (FEAT_PAN)">;
+def FeaturePAN : Extension<"pan", "PAN", "FEAT_PAN",
+ "Enables ARM v8.1 Privileged Access-Never extension">;
-def FeatureLOR : Extension<"lor", "LOR",
- "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)">;
+def FeatureLOR : Extension<"lor", "LOR", "FEAT_LOR",
+ "Enables ARM v8.1 Limited Ordering Regions extension">;
def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
"true", "Enable RW operand CONTEXTIDR_EL2" >;
-def FeatureVH : Extension<"vh", "VH",
- "Enables ARM v8.1 Virtual Host extension (FEAT_VHE)", [FeatureCONTEXTIDREL2] >;
+def FeatureVH : Extension<"vh", "VH", "FEAT_VHE",
+ "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
//===----------------------------------------------------------------------===//
// Armv8.2 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureSM4 : ExtensionWithMArch<"sm4", "SM4",
- "Enable SM3 and SM4 support (FEAT_SM4, FEAT_SM3)", [FeatureNEON],
+def FeatureSM4 : ExtensionWithMArch<"sm4", "SM4", "FEAT_SM4, FEAT_SM3",
+ "Enable SM3 and SM4 support", [FeatureNEON],
"FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>;
-def FeatureSHA3 : ExtensionWithMArch<"sha3", "SHA3",
- "Enable SHA512 and SHA3 support (FEAT_SHA3, FEAT_SHA512)", [FeatureNEON, FeatureSHA2],
+def FeatureSHA3 : ExtensionWithMArch<"sha3", "SHA3", "FEAT_SHA3, FEAT_SHA512",
+ "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2],
"FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>;
-def FeatureRAS : ExtensionWithMArch<"ras", "RAS",
- "Enable ARMv8 Reliability, Availability and Serviceability Extensions (FEAT_RAS, FEAT_RASv1p1)">;
+def FeatureRAS : ExtensionWithMArch<"ras", "RAS", "FEAT_RAS, FEAT_RASv1p1",
+ "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
let ArchExtKindSpelling = "AEK_FP16", MArchName = "fp16" in
-def FeatureFullFP16 : ExtensionWithMArch<"fullfp16", "FullFP16",
- "Full FP16 (FEAT_FP16)", [FeatureFPARMv8],
+def FeatureFullFP16 : ExtensionWithMArch<"fullfp16", "FullFP16", "FEAT_FP16",
+ "Full FP16", [FeatureFPARMv8],
"FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>;
let ArchExtKindSpelling = "AEK_PROFILE", MArchName = "profile" in
-def FeatureSPE : ExtensionWithMArch<"spe", "SPE",
- "Enable Statistical Profiling extension (FEAT_SPE)">;
+def FeatureSPE : ExtensionWithMArch<"spe", "SPE", "FEAT_SPE",
+ "Enable Statistical Profiling extension">;
-def FeaturePAN_RWV : Extension<"pan-rwv", "PAN_RWV",
- "Enable v8.2 PAN s1e1R and s1e1W Variants (FEAT_PAN2)", [FeaturePAN]>;
+def FeaturePAN_RWV : Extension<"pan-rwv", "PAN_RWV", "FEAT_PAN2",
+ "Enable v8.2 PAN s1e1R and s1e1W Variants", [FeaturePAN]>;
-def FeaturePsUAO : Extension<"uaops", "PsUAO",
- "Enable v8.2 UAO PState (FEAT_UAO)">;
+def FeaturePsUAO : Extension<"uaops", "PsUAO", "FEAT_UAO",
+ "Enable v8.2 UAO PState">;
-def FeatureCCPP : Extension<"ccpp", "CCPP",
- "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)" >;
+def FeatureCCPP : Extension<"ccpp", "CCPP", "FEAT_DPB",
+ "Enable v8.2 data Cache Clean to Point of Persistence" >;
-def FeatureSVE : ExtensionWithMArch<"sve", "SVE",
- "Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16],
+def FeatureSVE : ExtensionWithMArch<"sve", "SVE", "FEAT_SVE",
+ "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16],
"FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
let ArchExtKindSpelling = "AEK_I8MM" in
-def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8",
- "Enable Matrix Multiply Int8 Extension (FEAT_I8MM)", [],
+def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8", "FEAT_I8MM",
+ "Enable Matrix Multiply Int8 Extension", [],
"FEAT_I8MM", "+i8mm", 270>;
let ArchExtKindSpelling = "AEK_F32MM" in
-def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32",
- "Enable Matrix Multiply FP32 Extension (FEAT_F32MM)", [FeatureSVE],
+def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32", "FEAT_F32MM",
+ "Enable Matrix Multiply FP32 Extension", [FeatureSVE],
"FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>;
let ArchExtKindSpelling = "AEK_F64MM" in
-def FeatureMatMulFP64 : ExtensionWithMArch<"f64mm", "MatMulFP64",
- "Enable Matrix Multiply FP64 Extension (FEAT_F64MM)", [FeatureSVE],
+def FeatureMatMulFP64 : ExtensionWithMArch<"f64mm", "MatMulFP64", "FEAT_F64MM",
+ "Enable Matrix Multiply FP64 Extension", [FeatureSVE],
"FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>;
//===----------------------------------------------------------------------===//
// Armv8.3 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureRCPC : ExtensionWithMArch<"rcpc", "RCPC",
- "Enable support for RCPC extension (FEAT_LRCPC)", [],
+def FeatureRCPC : ExtensionWithMArch<"rcpc", "RCPC", "FEAT_LRCPC",
+ "Enable support for RCPC extension", [],
"FEAT_RCPC", "+rcpc", 230>;
-def FeaturePAuth : ExtensionWithMArch<"pauth", "PAuth",
- "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)">;
+def FeaturePAuth : ExtensionWithMArch<"pauth", "PAuth", "FEAT_PAuth",
+ "Enable v8.3-A Pointer Authentication extension">;
let ArchExtKindSpelling = "AEK_JSCVT", MArchName = "jscvt" in
-def FeatureJS : ExtensionWithMArch<"jsconv", "JS",
- "Enable v8.3-A JavaScript FP conversion instructions (FEAT_JSCVT)",
+def FeatureJS : ExtensionWithMArch<"jsconv", "JS", "FEAT_JSCVT",
+ "Enable v8.3-A JavaScript FP conversion instructions",
[FeatureFPARMv8],
"FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>;
-def FeatureCCIDX : Extension<"ccidx", "CCIDX",
- "Enable v8.3-A Extend of the CCSIDR number of sets (FEAT_CCIDX)">;
+def FeatureCCIDX : Extension<"ccidx", "CCIDX", "FEAT_CCIDX",
+ "Enable v8.3-A Extend of the CCSIDR number of sets">;
let ArchExtKindSpelling = "AEK_FCMA", MArchName = "fcma" in
-def FeatureComplxNum : ExtensionWithMArch<"complxnum", "ComplxNum",
- "Enable v8.3-A Floating-point complex number support (FEAT_FCMA)",
+def FeatureComplxNum : ExtensionWithMArch<"complxnum", "ComplxNum", "FEAT_FCMA",
+ "Enable v8.3-A Floating-point complex number support",
[FeatureNEON],
"FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>;
-def FeatureNV : Extension<"nv", "NV",
- "Enable v8.4-A Nested Virtualization Enchancement (FEAT_NV, FEAT_NV2)">;
+def FeatureNV : Extension<"nv", "NV", "FEAT_NV, FEAT_NV2",
+ "Enable v8.4-A Nested Virtualization Enchancement">;
//===----------------------------------------------------------------------===//
// Armv8.4 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureLSE2 : Extension<"lse2", "LSE2",
- "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)">;
+def FeatureLSE2 : Extension<"lse2", "LSE2", "FEAT_LSE2",
+ "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules">;
-def FeatureFP16FML : ExtensionWithMArch<"fp16fml", "FP16FML",
- "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16],
+def FeatureFP16FML : ExtensionWithMArch<"fp16fml", "FP16FML", "FEAT_FHM",
+ "Enable FP16 FML instructions", [FeatureFullFP16],
"FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>;
-def FeatureDotProd : ExtensionWithMArch<"dotprod", "DotProd",
- "Enable dot product support (FEAT_DotProd)", [FeatureNEON],
+def FeatureDotProd : ExtensionWithMArch<"dotprod", "DotProd", "FEAT_DotProd",
+ "Enable dot product support", [FeatureNEON],
"FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>;
-def FeatureMPAM : Extension<"mpam", "MPAM",
- "Enable v8.4-A Memory system Partitioning and Monitoring extension (FEAT_MPAM)">;
+def FeatureMPAM : Extension<"mpam", "MPAM", "FEAT_MPAM",
+ "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
-def FeatureDIT : ExtensionWithMArch<"dit", "DIT",
- "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)", [],
+def FeatureDIT : ExtensionWithMArch<"dit", "DIT", "FEAT_DIT",
+ "Enable v8.4-A Data Independent Timing instructions", [],
"FEAT_DIT", "+dit", 180>;
-def FeatureTRACEV8_4 : Extension<"tracev8.4", "TRACEV8_4",
- "Enable v8.4-A Trace extension (FEAT_TRF)">;
+def FeatureTRACEV8_4 : Extension<"tracev8.4", "TRACEV8_4", "FEAT_TRF",
+ "Enable v8.4-A Trace extension">;
-def FeatureAM : Extension<"am", "AM",
- "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)">;
+def FeatureAM : Extension<"am", "AM", "FEAT_AMUv1",
+ "Enable v8.4-A Activity Monitors extension">;
-def FeatureSEL2 : Extension<"sel2", "SEL2",
- "Enable v8.4-A Secure Exception Level 2 extension (FEAT_SEL2)">;
+def FeatureSEL2 : Extension<"sel2", "SEL2", "FEAT_SEL2",
+ "Enable v8.4-A Secure Exception Level 2 extension">;
-def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI",
- "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)">;
+def FeatureTLB_RMI : Extension<"tlb-rmi", "TLB_RMI", "FEAT_TLBIOS, FEAT_TLBIRANGE",
+ "Enable v8.4-A TLB Range and Maintenance Instructions">;
-def FeatureFlagM : ExtensionWithMArch<"flagm", "FlagM",
- "Enable v8.4-A Flag Manipulation Instructions (FEAT_FlagM)", [],
+def FeatureFlagM : ExtensionWithMArch<"flagm", "FlagM", "FEAT_FlagM",
+ "Enable v8.4-A Flag Manipulation Instructions", [],
"FEAT_FLAGM", "+flagm", 20>;
-def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO",
- "Enable v8.4-A RCPC instructions with Immediate Offsets (FEAT_LRCPC2)",
+def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO", "FEAT_LRCPC2",
+ "Enable v8.4-A RCPC instructions with Immediate Offsets",
[FeatureRCPC]>;
//===----------------------------------------------------------------------===//
// Armv8.5 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureAltFPCmp : Extension<"altnzcv", "AlternativeNZCV",
- "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)">;
+def FeatureAltFPCmp : Extension<"altnzcv", "AlternativeNZCV", "FEAT_FlagM2",
+ "Enable alternative NZCV format for floating point comparisons">;
-def FeatureFRInt3264 : Extension<"fptoint", "FRInt3264",
+def FeatureFRInt3264 : Extension<"fptoint", "FRInt3264", "FEAT_FRINTTS",
"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
- "an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)" >;
+ "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
-def FeatureSB : ExtensionWithMArch<"sb", "SB",
- "Enable v8.5 Speculation Barrier (FEAT_SB)", [],
+def FeatureSB : ExtensionWithMArch<"sb", "SB", "FEAT_SB",
+ "Enable v8.5 Speculation Barrier", [],
"FEAT_SB", "+sb", 470>;
-def FeatureSSBS : ExtensionWithMArch<"ssbs", "SSBS",
- "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)", [],
+def FeatureSSBS : ExtensionWithMArch<"ssbs", "SSBS", "FEAT_SSBS, FEAT_SSBS2",
+ "Enable Speculative Store Bypass Safe bit", [],
"FEAT_SSBS", "", 490>;
-def FeaturePredRes : ExtensionWithMArch<"predres", "PredRes",
- "Enable v8.5a execution and data prediction invalidation instructions (FEAT_SPECRES)", [],
+def FeaturePredRes : ExtensionWithMArch<"predres", "PredRes", "FEAT_SPECRES",
+ "Enable v8.5a execution and data prediction invalidation instructions", [],
"FEAT_PREDRES", "+predres", 480>;
-def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP",
- "Enable v8.5 Cache Clean to Point of Deep Persistence (FEAT_DPB2)" >;
+def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", "FEAT_DPB2",
+ "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
let ArchExtKindSpelling = "AEK_NONE" in
-def FeatureBranchTargetId : ExtensionWithMArch<"bti", "BTI",
- "Enable Branch Target Identification (FEAT_BTI)", [],
+def FeatureBranchTargetId : ExtensionWithMArch<"bti", "BTI", "FEAT_BTI",
+ "Enable Branch Target Identification", [],
"FEAT_BTI", "+bti", 510>;
let ArchExtKindSpelling = "AEK_RAND", MArchName = "rng" in
-def FeatureRandGen : ExtensionWithMArch<"rand", "RandGen",
- "Enable Random Number generation instructions (FEAT_RNG)", [],
+def FeatureRandGen : ExtensionWithMArch<"rand", "RandGen", "FEAT_RNG",
+ "Enable Random Number generation instructions", [],
"FEAT_RNG", "+rand", 10>;
// NOTE: "memtag" means FEAT_MTE + FEAT_MTE2 for -march or
// __attribute((target(...))), but only FEAT_MTE for FMV.
let MArchName = "memtag" in
-def FeatureMTE : ExtensionWithMArch<"mte", "MTE",
- "Enable Memory Tagging Extension (FEAT_MTE, FEAT_MTE2)", [],
+def FeatureMTE : ExtensionWithMArch<"mte", "MTE", "FEAT_MTE, FEAT_MTE2",
+ "Enable Memory Tagging Extension", [],
"FEAT_MEMTAG", "", 440>;
//===----------------------------------------------------------------------===//
// Armv8.6 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16",
- "Enable BFloat16 Extension (FEAT_BF16)", [],
+def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16", "FEAT_BF16",
+ "Enable BFloat16 Extension", [],
"FEAT_BF16", "+bf16", 280>;
-def FeatureAMVS : Extension<"amvs", "AMVS",
- "Enable v8.6-A Activity Monitors Virtualization support (FEAT_AMUv1p1)",
+def FeatureAMVS : Extension<"amvs", "AMVS", "FEAT_AMUv1p1",
+ "Enable v8.6-A Activity Monitors Virtualization support",
[FeatureAM]>;
-def FeatureFineGrainedTraps : Extension<"fgt", "FineGrainedTraps",
- "Enable fine grained virtualization traps extension (FEAT_FGT)">;
+def FeatureFineGrainedTraps : Extension<"fgt", "FineGrainedTraps", "FEAT_FGT",
+ "Enable fine grained virtualization traps extension">;
def FeatureEnhancedCounterVirtualization :
- Extension<"ecv", "EnhancedCounterVirtualization",
- "Enable enhanced counter virtualization extension (FEAT_ECV)">;
+ Extension<"ecv", "EnhancedCounterVirtualization", "FEAT_ECV",
+ "Enable enhanced counter virtualization extension">;
//===----------------------------------------------------------------------===//
// Armv8.7 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureXS : Extension<"xs", "XS",
- "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">;
+def FeatureXS : Extension<"xs", "XS", "FEAT_XS",
+ "Enable Armv8.7-A limited-TLB-maintenance instruction">;
-def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT",
- "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [],
+def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT", "FEAT_WFxT",
+ "Enable Armv8.7-A WFET and WFIT instruction", [],
"FEAT_WFXT", "+wfxt", 550>;
-def FeatureHCX : Extension<"hcx", "HCX",
- "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">;
+def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
+ "Enable Armv8.7-A HCRX_EL2 system register">;
-def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
- "Enable Armv8.7-A LD64B/ST64B Accelerator Extension (FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA)", [],
+def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64", "FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA",
+ "Enable Armv8.7-A LD64B/ST64B Accelerator Extension", [],
"FEAT_LS64", "", 520>;
-def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF",
- "Enable extra register in the Statistical Profiling Extension (FEAT_SPEv1p2)">;
+def FeatureSPE_EEF : Extension<"spe-eef", "SPE_EEF", "FEAT_SPEv1p2",
+ "Enable extra register in the Statistical Profiling Extension">;
//===----------------------------------------------------------------------===//
// Armv8.8 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureHBC : ExtensionWithMArch<"hbc", "HBC",
- "Enable Armv8.8-A Hinted Conditional Branches Extension (FEAT_HBC)">;
+def FeatureHBC : ExtensionWithMArch<"hbc", "HBC", "FEAT_HBC",
+ "Enable Armv8.8-A Hinted Conditional Branches Extension">;
-def FeatureMOPS : ExtensionWithMArch<"mops", "MOPS",
- "Enable Armv8.8-A memcpy and memset acceleration instructions (FEAT_MOPS)", [],
+def FeatureMOPS : ExtensionWithMArch<"mops", "MOPS", "FEAT_MOPS",
+ "Enable Armv8.8-A memcpy and memset acceleration instructions", [],
"FEAT_MOPS", "+mops", 650>;
-def FeatureNMI : Extension<"nmi", "NMI",
- "Enable Armv8.8-A Non-maskable Interrupts (FEAT_NMI, FEAT_GICv3_NMI)">;
+def FeatureNMI : Extension<"nmi", "NMI", "FEAT_NMI, FEAT_GICv3_NMI",
+ "Enable Armv8.8-A Non-maskable Interrupts">;
//===----------------------------------------------------------------------===//
// Armv8.9 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureRASv2 : ExtensionWithMArch<"rasv2", "RASv2",
- "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions (FEAT_RASv2)",
+def FeatureRASv2 : ExtensionWithMArch<"rasv2", "RASv2", "FEAT_RASv2",
+ "Enable ARMv8.9-A Reliability, Availability and Serviceability Extensions",
[FeatureRAS]>;
-def FeatureCSSC : ExtensionWithMArch<"cssc", "CSSC",
- "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)">;
+def FeatureCSSC : ExtensionWithMArch<"cssc", "CSSC", "FEAT_CSSC",
+ "Enable Common Short Sequence Compression (CSSC) instructions">;
-def FeatureCLRBHB : Extension<"clrbhb", "CLRBHB",
- "Enable Clear BHB instruction (FEAT_CLRBHB)">;
+def FeatureCLRBHB : Extension<"clrbhb", "CLRBHB", "FEAT_CLRBHB",
+ "Enable Clear BHB instruction">;
-def FeaturePRFM_SLC : Extension<"prfm-slc-target", "PRFM_SLC",
+def FeaturePRFM_SLC : Extension<"prfm-slc-target", "PRFM_SLC", "FEAT_PRFMSLC",
"Enable SLC target for PRFM instruction">;
let MArchName = "predres2" in
-def FeatureSPECRES2 : ExtensionWithMArch<"specres2", "SPECRES2",
- "Enable Speculation Restriction Instruction (FEAT_SPECRES2)",
+def FeatureSPECRES2 : ExtensionWithMArch<"specres2", "SPECRES2", "FEAT_SPECRES2",
+ "Enable Speculation Restriction Instruction",
[FeaturePredRes]>;
-def FeatureRCPC3 : ExtensionWithMArch<"rcpc3", "RCPC3",
- "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)",
+def FeatureRCPC3 : ExtensionWithMArch<"rcpc3", "RCPC3", "FEAT_LRCPC3",
+ "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set",
[FeatureRCPC_IMMO],
"FEAT_RCPC3", "+rcpc,+rcpc3", 241>;
-def FeatureTHE : ExtensionWithMArch<"the", "THE",
- "Enable Armv8.9-A Translation Hardening Extension (FEAT_THE)">;
+def FeatureTHE : ExtensionWithMArch<"the", "THE", "FEAT_THE",
+ "Enable Armv8.9-A Translation Hardening Extension">;
//===----------------------------------------------------------------------===//
// Armv9.0 Architecture Extensions
@@ -448,36 +452,36 @@ def FeatureTHE : ExtensionWithMArch<"the", "THE",
def FeatureUseScalarIncVL : SubtargetFeature<"use-scalar-inc-vl",
"UseScalarIncVL", "true", "Prefer inc/dec over add+cnt">;
-def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2",
- "Enable Scalable Vector Extension 2 (SVE2) instructions (FEAT_SVE2)",
+def FeatureSVE2 : ExtensionWithMArch<"sve2", "SVE2", "FEAT_SVE2",
+ "Enable Scalable Vector Extension 2 (SVE2) instructions",
[FeatureSVE, FeatureUseScalarIncVL],
"FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>;
-def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES",
- "Enable AES SVE2 instructions (FEAT_SVE_AES, FEAT_SVE_PMULL128)",
+def FeatureSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES", "FEAT_SVE_AES, FEAT_SVE_PMULL128",
+ "Enable AES SVE2 instructions",
[FeatureSVE2, FeatureAES],
"FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>;
-def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4",
- "Enable SM4 SVE2 instructions (FEAT_SVE_SM4)", [FeatureSVE2, FeatureSM4],
+def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4",
+ "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4],
"FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>;
-def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3",
- "Enable SHA3 SVE2 instructions (FEAT_SVE_SHA3)", [FeatureSVE2, FeatureSHA3],
+def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3", "FEAT_SVE_SHA3",
+ "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3],
"FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>;
-def FeatureSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm",
- "Enable bit permutation SVE2 instructions (FEAT_SVE_BitPerm)", [FeatureSVE2],
+def FeatureSVE2BitPerm : ExtensionWithMArch<"sve2-bitperm", "SVE2BitPerm", "FEAT_SVE_BitPerm",
+ "Enable bit permutation SVE2 instructions", [FeatureSVE2],
"FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>;
-def FeatureTRBE : Extension<"trbe", "TRBE",
- "Enable Trace Buffer Extension (FEAT_TRBE)">;
+def FeatureTRBE : Extension<"trbe", "TRBE", "FEAT_TRBE",
+ "Enable Trace Buffer Extension">;
-def FeatureETE : Extension<"ete", "ETE",
- "Enable Embedded Trace Extension (FEAT_ETE)", [FeatureTRBE]>;
+def FeatureETE : Extension<"ete", "ETE", "FEAT_ETE",
+ "Enable Embedded Trace Extension", [FeatureTRBE]>;
-def FeatureTME : ExtensionWithMArch<"tme", "TME",
- "Enable Transactional Memory Extension (FEAT_TME)">;
+def FeatureTME : ExtensionWithMArch<"tme", "TME", "FEAT_TME",
+ "Enable Transactional Memory Extension">;
//===----------------------------------------------------------------------===//
// Armv9.1 Architecture Extensions
@@ -487,36 +491,36 @@ def FeatureTME : ExtensionWithMArch<"tme", "TME",
// Armv9.2 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureBRBE : ExtensionWithMArch<"brbe", "BRBE",
- "Enable Branch Record Buffer Extension (FEAT_BRBE)">;
+def FeatureBRBE : ExtensionWithMArch<"brbe", "BRBE", "FEAT_BRBE",
+ "Enable Branch Record Buffer Extension">;
-def FeatureRME : Extension<"rme", "RME",
- "Enable Realm Management Extension (FEAT_RME)">;
+def FeatureRME : Extension<"rme", "RME", "FEAT_RME",
+ "Enable Realm Management Extension">;
-def FeatureSME : ExtensionWithMArch<"sme", "SME",
- "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL],
+def FeatureSME : ExtensionWithMArch<"sme", "SME", "FEAT_SME",
+ "Enable Scalable Matrix Extension (SME)", [FeatureBF16, FeatureUseScalarIncVL],
"FEAT_SME", "+sme,+bf16", 430>;
-def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64",
- "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME],
+def FeatureSMEF64F64 : ExtensionWithMArch<"sme-f64f64", "SMEF64F64", "FEAT_SME_F64F64",
+ "Enable Scalable Matrix Extension (SME) F64F64 instructions", [FeatureSME],
"FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>;
-def FeatureSMEI16I64 : ExtensionWithMArch<"sme-i16i64", "SMEI16I64",
- "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME],
+def FeatureSMEI16I64 : ExtensionWithMArch<"sme-i16i64", "SMEI16I64", "FEAT_SME_I16I64",
+ "Enable Scalable Matrix Extension (SME) I16I64 instructions", [FeatureSME],
"FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>;
-def FeatureSMEFA64 : ExtensionWithMArch<"sme-fa64", "SMEFA64",
- "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>;
+def FeatureSMEFA64 : ExtensionWithMArch<"sme-fa64", "SMEFA64", "FEAT_SME_FA64",
+ "Enable the full A64 instruction set in streaming SVE mode", [FeatureSME, FeatureSVE2]>;
//===----------------------------------------------------------------------===//
// Armv9.3 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureSME2 : ExtensionWithMArch<"sme2", "SME2",
+def FeatureSME2 : ExtensionWithMArch<"sme2", "SME2", "FEAT_SME2",
"Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME],
"FEAT_SME2", "+sme2,+sme,+bf16", 580>;
-def FeatureMEC : Extension<"mec", "MEC",
+def FeatureMEC : Extension<"mec", "MEC", "FEAT_MEC",
"Enable Memory Encryption Contexts Extension", [FeatureRME]>;
//===----------------------------------------------------------------------===//
@@ -524,93 +528,93 @@ def FeatureMEC : Extension<"mec", "MEC",
//===----------------------------------------------------------------------===//
let FMVDependencies = "+sve2p1,+sve2,+sve,+fullfp16,+fp-armv8,+neon" in
-def FeatureSVE2p1: ExtensionWithMArch<"sve2p1", "SVE2p1",
+def FeatureSVE2p1: ExtensionWithMArch<"sve2p1", "SVE2p1", "FEAT_SVE2p1",
"Enable Scalable Vector Extension 2.1 instructions", [FeatureSVE2]>;
-def FeatureB16B16 : ExtensionWithMArch<"b16b16", "B16B16",
- "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)", [FeatureBF16]>;
+def FeatureB16B16 : ExtensionWithMArch<"b16b16", "B16B16", "FEAT_SVE_B16B16",
+ "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions", [FeatureBF16]>;
let FMVDependencies = "+sme2,+sme-f16f16" in
-def FeatureSMEF16F16 : ExtensionWithMArch<"sme-f16f16", "SMEF16F16",
- "Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>;
+def FeatureSMEF16F16 : ExtensionWithMArch<"sme-f16f16", "SMEF16F16", "FEAT_SME_F16F16",
+ "Enable SME non-widening Float16 instructions", [FeatureSME2]>;
let FMVDependencies = "+sme2p1,+sme2,+sme,+bf16" in
-def FeatureSME2p1 : ExtensionWithMArch<"sme2p1", "SME2p1",
- "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>;
+def FeatureSME2p1 : ExtensionWithMArch<"sme2p1", "SME2p1", "FEAT_SME2p1",
+ "Enable Scalable Matrix Extension 2.1 instructions", [FeatureSME2]>;
-def FeatureCHK : Extension<"chk", "CHK",
- "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)">;
+def FeatureCHK : Extension<"chk", "CHK", "FEAT_CHK",
+ "Enable Armv8.0-A Check Feature Status Extension">;
-def FeatureGCS : ExtensionWithMArch<"gcs", "GCS",
+def FeatureGCS : ExtensionWithMArch<"gcs", "GCS", "FEAT_GCS",
"Enable Armv9.4-A Guarded Call Stack Extension", [FeatureCHK]>;
-def FeatureITE : ExtensionWithMArch<"ite", "ITE",
- "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, FeatureTRBE]>;
+def FeatureITE : ExtensionWithMArch<"ite", "ITE", "FEAT_ITE",
+ "Enable Armv9.4-A Instrumentation Extension", [FeatureETE, FeatureTRBE]>;
-def FeatureLSE128 : ExtensionWithMArch<"lse128", "LSE128",
- "Enable Armv9.4-A 128-bit Atomic Instructions (FEAT_LSE128)",
+def FeatureLSE128 : ExtensionWithMArch<"lse128", "LSE128", "FEAT_LSE128",
+ "Enable Armv9.4-A 128-bit Atomic Instructions",
[FeatureLSE]>;
// FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, and FEAT_SYSINSTR128 are mutually implicit.
// Therefore group them all under a single feature flag, d128:
-def FeatureD128 : ExtensionWithMArch<"d128", "D128",
+def FeatureD128 : ExtensionWithMArch<"d128", "D128", "FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128",
"Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers "
- "and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
+ "and Instructions",
[FeatureLSE128]>;
//===----------------------------------------------------------------------===//
// Armv9.5 Architecture Extensions
//===----------------------------------------------------------------------===//
-def FeatureFAMINMAX: ExtensionWithMArch<"faminmax", "FAMINMAX",
- "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
+def FeatureFAMINMAX: ExtensionWithMArch<"faminmax", "FAMINMAX", "FEAT_FAMINMAX",
+ "Enable FAMIN and FAMAX instructions">;
-def FeatureLUT: ExtensionWithMArch<"lut", "LUT",
- "Enable Lookup Table instructions (FEAT_LUT)">;
+def FeatureLUT: ExtensionWithMArch<"lut", "LUT", "FEAT_LUT",
+ "Enable Lookup Table instructions">;
-def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8",
- "Enable FP8 instructions (FEAT_FP8)", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
+def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8", "FEAT_FP8",
+ "Enable FP8 instructions", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
-def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA",
- "Enable fp8 multiply-add instructions (FEAT_FP8FMA)", [FeatureFP8]>;
+def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA", "FEAT_FP8FMA",
+ "Enable fp8 multiply-add instructions", [FeatureFP8]>;
let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA",
- "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2, FeatureFP8]>;
+def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA", "FEAT_SSVE_FP8FMA",
+ "Enable SVE2 fp8 multiply-add instructions", [FeatureSME2, FeatureFP8]>;
-def FeatureFP8DOT4: ExtensionWithMArch<"fp8dot4", "FP8DOT4",
- "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>;
+def FeatureFP8DOT4: ExtensionWithMArch<"fp8dot4", "FP8DOT4", "FEAT_FP8DOT4",
+ "Enable fp8 4-way dot instructions", [FeatureFP8FMA]>;
-def FeatureFP8DOT2: ExtensionWithMArch<"fp8dot2", "FP8DOT2",
- "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>;
+def FeatureFP8DOT2: ExtensionWithMArch<"fp8dot2", "FP8DOT2", "FEAT_FP8DOT2",
+ "Enable fp8 2-way dot instructions", [FeatureFP8DOT4]>;
let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8DOT4 : ExtensionWithMArch<"ssve-fp8dot4", "SSVE_FP8DOT4",
- "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSSVE_FP8FMA]>;
+def FeatureSSVE_FP8DOT4 : ExtensionWithMArch<"ssve-fp8dot4", "SSVE_FP8DOT4", "FEAT_SSVE_FP8DOT4",
+ "Enable SVE2 fp8 4-way dot product instructions", [FeatureSSVE_FP8FMA]>;
let FMVDependencies = "+sme2" in
-def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2",
- "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSSVE_FP8DOT4]>;
+def FeatureSSVE_FP8DOT2 : ExtensionWithMArch<"ssve-fp8dot2", "SSVE_FP8DOT2", "FEAT_SSVE_FP8DOT2",
+ "Enable SVE2 fp8 2-way dot product instructions", [FeatureSSVE_FP8DOT4]>;
-def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2",
- "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
+def FeatureSME_LUTv2 : ExtensionWithMArch<"sme-lutv2", "SME_LUTv2", "FEAT_SME_LUTv2",
+ "Enable Scalable Matrix Extension (SME) LUTv2 instructions">;
let FMVDependencies = "+sme2,+fp8" in
-def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32",
- "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
+def FeatureSMEF8F32 : ExtensionWithMArch<"sme-f8f32", "SMEF8F32", "FEAT_SME_F8F32",
+ "Enable Scalable Matrix Extension (SME) F8F32 instructions", [FeatureSME2, FeatureFP8]>;
let FMVDependencies = "+fp8,+sme2" in
-def FeatureSMEF8F16 : ExtensionWithMArch<"sme-f8f16", "SMEF8F16",
- "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSMEF8F32]>;
+def FeatureSMEF8F16 : ExtensionWithMArch<"sme-f8f16", "SMEF8F16", "FEAT_SME_F8F16",
+ "Enable Scalable Matrix Extension (SME) F8F16 instructions", [FeatureSMEF8F32]>;
-def FeatureCPA : ExtensionWithMArch<"cpa", "CPA",
- "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)">;
+def FeatureCPA : ExtensionWithMArch<"cpa", "CPA", "FEAT_CPA",
+ "Enable Armv9.5-A Checked Pointer Arithmetic">;
-def FeaturePAuthLR : ExtensionWithMArch<"pauth-lr", "PAuthLR",
- "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)">;
+def FeaturePAuthLR : ExtensionWithMArch<"pauth-lr", "PAuthLR", "FEAT_PAuth_LR",
+ "Enable Armv9.5-A PAC enhancements">;
-def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW",
- "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)">;
+def FeatureTLBIW : ExtensionWithMArch<"tlbiw", "TLBIW", "FEAT_TLBIW",
+ "Enable ARMv9.5-A TLBI VMALL for Dirty State">;
//===----------------------------------------------------------------------===//
// Other Features
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index c9c6965efb630..7b53f1eeaa53f 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -139,13 +139,15 @@ std::optional<AArch64::CpuInfo> AArch64::parseCpu(StringRef Name) {
void AArch64::PrintSupportedExtensions() {
outs() << "All available -march extensions for AArch64\n\n"
<< " " << left_justify("Name", 20)
+ << left_justify("Architecture Feature(s)", 55)
<< "Description\n";
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
if (!Ext.UserVisibleName.empty() && !Ext.TargetFeature.empty()) {
outs() << " "
- << format(Ext.Description.empty() ? "%s\n" : "%-20s%s\n",
+ << format(Ext.Description.empty() ? "%-20s%s\n" : "%-20s%-55s%s\n",
Ext.UserVisibleName.str().c_str(),
+ Ext.ArchFeatureName.str().c_str(),
Ext.Description.str().c_str());
}
}
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 4cc9bae522339..d3ed905b96494 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2316,7 +2316,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
TEST(TargetParserTest, AArch64PrintSupportedExtensions) {
std::string expected =
"All available -march extensions for AArch64\n\n"
- " Name Description\n";
+ " Name Architecture Feature(s) Description\n";
outs().flush();
testing::internal::CaptureStdout();
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 76054982c68a1..43b2aaac54288 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -97,6 +97,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
else
OS << ", \"" << Alias << "\"";
OS << ", AArch64::" << AEK;
+ OS << ", \"" << Rec->getValueAsString("ArchFeatureName") << "\"";
OS << ", \"" << Rec->getValueAsString("Desc") << "\"";
if (AEK == "AEK_NONE") {
// HACK: don't emit posfeat/negfeat strings for FMVOnlyExtensions.
@@ -110,7 +111,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
OS << ", " << (uint64_t)Rec->getValueAsInt("FMVPriority");
OS << "},\n";
};
- OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {}, {}, FEAT_INIT, \"\", "
+ OS << " {\"none\", {}, AArch64::AEK_NONE, {}, {}, {}, {}, FEAT_INIT, \"\", "
"ExtensionInfo::MaxFMVPriority},\n";
OS << "};\n"
<< "#undef EMIT_EXTENSIONS\n"
>From f4701688a0d539e893a132152f73245ac6579da4 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Mon, 17 Jun 2024 14:26:27 +0100
Subject: [PATCH 6/9] [AArch64] Add ability to list extensions enabled for a
target
This introduces the new '--print-enabled-extensions' command line option
to AArch64, which prints the list of extensins that are enabled for the
target specified by the combination of '--target/-march/-mcpu' values.
The new option allows the manual inspection of the enabled extensions by
users and enables us to programatically test that the correct set of
extensions are enabled for specific architecture versions or CPU models.
---
clang/include/clang/Driver/Options.td | 5 ++
.../include/clang/Frontend/FrontendOptions.h | 4 +
clang/lib/Driver/Driver.cpp | 19 +++--
clang/test/Driver/aarch64-v81a.c | 16 ++++
clang/test/Driver/aarch64-v82a.c | 20 +++++
clang/test/Driver/aarch64-v83a.c | 26 +++++++
clang/test/Driver/aarch64-v84a.c | 40 ++++++++++
clang/test/Driver/aarch64-v85a.c | 48 ++++++++++++
clang/test/Driver/aarch64-v86a.c | 54 +++++++++++++
clang/test/Driver/aarch64-v87a.c | 57 ++++++++++++++
clang/test/Driver/aarch64-v88a.c | 60 ++++++++++++++
clang/test/Driver/aarch64-v89a.c | 67 ++++++++++++++++
clang/test/Driver/aarch64-v8a.c | 31 ++++++++
clang/test/Driver/aarch64-v91a.c | 63 +++++++++++++++
clang/test/Driver/aarch64-v92a.c | 66 ++++++++++++++++
clang/test/Driver/aarch64-v93a.c | 69 ++++++++++++++++
clang/test/Driver/aarch64-v94a.c | 75 ++++++++++++++++++
clang/test/Driver/aarch64-v95a.c | 78 +++++++++++++++++++
clang/test/Driver/aarch64-v9a.c | 72 +++++++++++++++++
clang/tools/driver/cc1_main.cpp | 38 +++++++++
llvm/include/llvm/MC/MCSubtargetInfo.h | 3 +
.../llvm/TargetParser/AArch64TargetParser.h | 2 +
llvm/lib/MC/MCSubtargetInfo.cpp | 10 +++
llvm/lib/TargetParser/AArch64TargetParser.cpp | 20 +++++
24 files changed, 938 insertions(+), 5 deletions(-)
create mode 100644 clang/test/Driver/aarch64-v8a.c
create mode 100644 clang/test/Driver/aarch64-v9a.c
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 49b44893c25f2..6a520dc9e7062 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5703,6 +5703,11 @@ def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">
Visibility<[ClangOption, CC1Option, CLOption]>,
HelpText<"Print supported -march extensions (RISC-V, AArch64 and ARM only)">,
MarshallingInfoFlag<FrontendOpts<"PrintSupportedExtensions">>;
+def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
+ Visibility<[ClangOption, CC1Option, CLOption]>,
+ HelpText<"Print the -march/-mcpu extensions enabled for the given target"
+ " (AArch64 only)">,
+ MarshallingInfoFlag<FrontendOpts<"PrintEnabledExtensions">>;
def : Flag<["-"], "mcpu=help">, Alias<print_supported_cpus>;
def : Flag<["-"], "mtune=help">, Alias<print_supported_cpus>;
def time : Flag<["-"], "time">,
diff --git a/clang/include/clang/Frontend/FrontendOptions.h b/clang/include/clang/Frontend/FrontendOptions.h
index ebb8e9e59c6b6..5e5034fe01eb5 100644
--- a/clang/include/clang/Frontend/FrontendOptions.h
+++ b/clang/include/clang/Frontend/FrontendOptions.h
@@ -306,6 +306,10 @@ class FrontendOptions {
LLVM_PREFERRED_TYPE(bool)
unsigned PrintSupportedExtensions : 1;
+ /// Print the extensions enabled for the current target.
+ LLVM_PREFERRED_TYPE(bool)
+ unsigned PrintEnabledExtensions : 1;
+
/// Show the -version text.
LLVM_PREFERRED_TYPE(bool)
unsigned ShowVersion : 1;
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 67bf0604acd6e..db7327e25f4ad 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -370,6 +370,7 @@ phases::ID Driver::getFinalPhase(const DerivedArgList &DAL,
// -{fsyntax-only,-analyze,emit-ast} only run up to the compiler.
} else if ((PhaseArg = DAL.getLastArg(options::OPT_fsyntax_only)) ||
(PhaseArg = DAL.getLastArg(options::OPT_print_supported_cpus)) ||
+ (PhaseArg = DAL.getLastArg(options::OPT_print_enabled_extensions)) ||
(PhaseArg = DAL.getLastArg(options::OPT_module_file_info)) ||
(PhaseArg = DAL.getLastArg(options::OPT_verify_pch)) ||
(PhaseArg = DAL.getLastArg(options::OPT_rewrite_objc)) ||
@@ -2171,7 +2172,8 @@ bool Driver::HandleImmediateArgs(const Compilation &C) {
if (C.getArgs().hasArg(options::OPT_v) ||
C.getArgs().hasArg(options::OPT__HASH_HASH_HASH) ||
C.getArgs().hasArg(options::OPT_print_supported_cpus) ||
- C.getArgs().hasArg(options::OPT_print_supported_extensions)) {
+ C.getArgs().hasArg(options::OPT_print_supported_extensions) ||
+ C.getArgs().hasArg(options::OPT_print_enabled_extensions)) {
PrintVersion(C, llvm::errs());
SuppressMissingInputWarning = true;
}
@@ -4351,13 +4353,14 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
}
for (auto Opt : {options::OPT_print_supported_cpus,
- options::OPT_print_supported_extensions}) {
+ options::OPT_print_supported_extensions,
+ options::OPT_print_enabled_extensions}) {
// If --print-supported-cpus, -mcpu=? or -mtune=? is specified, build a
// custom Compile phase that prints out supported cpu models and quits.
//
- // If --print-supported-extensions is specified, call the helper function
- // RISCVMarchHelp in RISCVISAInfo.cpp that prints out supported extensions
- // and quits.
+ // If either --print-supported-extensions or --print-enabled-extensions is
+ // specified, call the corresponding helper function that prints out the
+ // supported/enabled extensions and quits.
if (Arg *A = Args.getLastArg(Opt)) {
if (Opt == options::OPT_print_supported_extensions &&
!C.getDefaultToolChain().getTriple().isRISCV() &&
@@ -4367,6 +4370,12 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
<< "--print-supported-extensions";
return;
}
+ if (Opt == options::OPT_print_enabled_extensions &&
+ !C.getDefaultToolChain().getTriple().isAArch64()) {
+ C.getDriver().Diag(diag::err_opt_not_valid_on_target)
+ << "--print-enabled-extensions";
+ return;
+ }
// Use the -mcpu=? flag as the dummy input to cc1.
Actions.clear();
diff --git a/clang/test/Driver/aarch64-v81a.c b/clang/test/Driver/aarch64-v81a.c
index e84652ec7f11e..419a2e1892c0d 100644
--- a/clang/test/Driver/aarch64-v81a.c
+++ b/clang/test/Driver/aarch64-v81a.c
@@ -19,3 +19,19 @@
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1a -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-GENERICV81A %s
// RUN: %clang --target=arm64 -mlittle-endian -march=armv8.1-a -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-GENERICV81A %s
// ARM64-GENERICV81A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"{{.*}} "-target-feature" "+v8.1a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.1-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
diff --git a/clang/test/Driver/aarch64-v82a.c b/clang/test/Driver/aarch64-v82a.c
index 9dd355934c105..a91423a67b845 100644
--- a/clang/test/Driver/aarch64-v82a.c
+++ b/clang/test/Driver/aarch64-v82a.c
@@ -13,3 +13,23 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV82A-BE %s
// GENERICV82A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.2a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.2-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
diff --git a/clang/test/Driver/aarch64-v83a.c b/clang/test/Driver/aarch64-v83a.c
index b0ff9fb3abc24..84f3c5e878328 100644
--- a/clang/test/Driver/aarch64-v83a.c
+++ b/clang/test/Driver/aarch64-v83a.c
@@ -13,3 +13,29 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV83A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV83A-BE %s
// GENERICV83A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.3a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.3-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_FCMA
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
diff --git a/clang/test/Driver/aarch64-v84a.c b/clang/test/Driver/aarch64-v84a.c
index 030990bfe5131..28062cc16d4e8 100644
--- a/clang/test/Driver/aarch64-v84a.c
+++ b/clang/test/Driver/aarch64-v84a.c
@@ -13,3 +13,43 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.4a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV84A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.4-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV84A-BE %s
// GENERICV84A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.4a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.4-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_LSE2
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
diff --git a/clang/test/Driver/aarch64-v85a.c b/clang/test/Driver/aarch64-v85a.c
index 3e1e921dcc013..32945e435b402 100644
--- a/clang/test/Driver/aarch64-v85a.c
+++ b/clang/test/Driver/aarch64-v85a.c
@@ -13,3 +13,51 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV85A-BE %s
// GENERICV85A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.5a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.5-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
diff --git a/clang/test/Driver/aarch64-v86a.c b/clang/test/Driver/aarch64-v86a.c
index ba2b57979b518..c0ca90fe49d17 100644
--- a/clang/test/Driver/aarch64-v86a.c
+++ b/clang/test/Driver/aarch64-v86a.c
@@ -13,3 +13,57 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.6a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV86A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.6-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV86A-BE %s
// GENERICV86A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.6a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.6-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
diff --git a/clang/test/Driver/aarch64-v87a.c b/clang/test/Driver/aarch64-v87a.c
index ee4b68882739a..29001fe76f480 100644
--- a/clang/test/Driver/aarch64-v87a.c
+++ b/clang/test/Driver/aarch64-v87a.c
@@ -13,3 +13,60 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.7a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV87A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.7-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV87A-BE %s
// GENERICV87A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.7a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.7-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v88a.c b/clang/test/Driver/aarch64-v88a.c
index b680c1f567134..3a2b51fa54579 100644
--- a/clang/test/Driver/aarch64-v88a.c
+++ b/clang/test/Driver/aarch64-v88a.c
@@ -13,3 +13,63 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV88A-BE %s
// GENERICV88A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.8a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.8-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// ARCH-EXTENSION: FEAT_NMI, FEAT_GICv3_NMI
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MPAM
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_HBC
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_MOPS
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v89a.c b/clang/test/Driver/aarch64-v89a.c
index 903b793d046ba..319e2d9bf6aa0 100644
--- a/clang/test/Driver/aarch64-v89a.c
+++ b/clang/test/Driver/aarch64-v89a.c
@@ -12,3 +12,70 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV89A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8.9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV89A-BE %s
// GENERICV89A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v8.9a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8.9-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// ARCH-EXTENSION: FEAT_NMI, FEAT_GICv3_NMI
+// ARCH-EXTENSION: FEAT_DPB
+// FIXME: FEAT_CHK is optional from v8.0a and mandatory from v9.4a
+// ARCH-EXTENSION: FEAT_CHK
+// ARCH-EXTENSION: FEAT_CLRBHB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PRFMSLC
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_CSSC
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// ARCH-EXTENSION: FEAT_HBC
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_MOPS
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_SPECRES2
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_RASv2
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v8a.c b/clang/test/Driver/aarch64-v8a.c
new file mode 100644
index 0000000000000..a9eb68729dd3f
--- /dev/null
+++ b/clang/test/Driver/aarch64-v8a.c
@@ -0,0 +1,31 @@
+// RUN: %clang --target=aarch64_be -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-BE %s
+// RUN: %clang --target=aarch64_be -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-BE %s
+// RUN: %clang --target=aarch64 -mbig-endian -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-BE %s
+// RUN: %clang --target=aarch64 -mbig-endian -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-BE %s
+// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-BE %s
+// RUN: %clang --target=aarch64_be -mbig-endian -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A-BE %s
+// GENERICV8A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic"{{.*}} "-target-feature" "+v8a"{{.*}} "-target-feature" "+neon"
+
+// RUN: %clang --target=aarch64 -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A %s
+// RUN: %clang --target=aarch64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A %s
+// RUN: %clang --target=aarch64 -mlittle-endian -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A %s
+// RUN: %clang --target=aarch64 -mlittle-endian -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A %s
+// RUN: %clang --target=aarch64_be -mlittle-endian -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A %s
+// RUN: %clang --target=aarch64_be -mlittle-endian -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV8A %s
+// GENERICV8A: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic"{{.*}} "-target-feature" "+v8a"{{.*}} "-target-feature" "+neon"{{.*}}
+
+// RUN: %clang --target=arm64 -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-GENERICV8A %s
+// RUN: %clang --target=arm64 -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-GENERICV8A %s
+// RUN: %clang --target=arm64 -mlittle-endian -march=armv8a -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-GENERICV8A %s
+// RUN: %clang --target=arm64 -mlittle-endian -march=armv8-a -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-GENERICV8A %s
+// ARM64-GENERICV8A: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"{{.*}} "-target-feature" "+v8a"{{.*}} "-target-feature" "+neon"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv8-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_TRBE
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
diff --git a/clang/test/Driver/aarch64-v91a.c b/clang/test/Driver/aarch64-v91a.c
index 80853a59d0153..89009a0fd9c3d 100644
--- a/clang/test/Driver/aarch64-v91a.c
+++ b/clang/test/Driver/aarch64-v91a.c
@@ -13,3 +13,66 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.1a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.1-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV91A-BE %s
// GENERICV91A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.1a"{{.*}} "-target-feature" "+sve" "-target-feature" "+sve2"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv9.1-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// FIXME: FEAT_RME is optional from v9.1a
+// ARCH-EXTENSION: FEAT_RME
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MEC
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_FP16 is optional from v8.2a, unless FEAT_SVE is implemented (see below)
+// ARCH-EXTENSION: FEAT_FP16
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// FIXME: FEAT_SVE is optional from v8.2a, unless FEAT_SVE2 is implemented (see below)
+// ARCH-EXTENSION: FEAT_SVE
+// FIXME: FEAT_SVE2 is optional from v9.0a
+// ARCH-EXTENSION: FEAT_SVE2
diff --git a/clang/test/Driver/aarch64-v92a.c b/clang/test/Driver/aarch64-v92a.c
index ee644cc6f3c62..cdadadcee8d3b 100644
--- a/clang/test/Driver/aarch64-v92a.c
+++ b/clang/test/Driver/aarch64-v92a.c
@@ -13,3 +13,69 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.2a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.2-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV92A-BE %s
// GENERICV92A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.2a"{{.*}} "-target-feature" "+sve" "-target-feature" "+sve2"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv9.2-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// FIXME: FEAT_RME is optional from v9.1a
+// ARCH-EXTENSION: FEAT_RME
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MEC
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_FP16 is optional from v8.2a, unless FEAT_SVE is implemented (see below)
+// ARCH-EXTENSION: FEAT_FP16
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// FIXME: FEAT_SVE is optional from v8.2a, unless FEAT_SVE2 is implemented (see below)
+// ARCH-EXTENSION: FEAT_SVE
+// FIXME: FEAT_SVE2 is optional from v9.0a
+// ARCH-EXTENSION: FEAT_SVE2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v93a.c b/clang/test/Driver/aarch64-v93a.c
index 817559e28ccf4..6ecc9b4b165fb 100644
--- a/clang/test/Driver/aarch64-v93a.c
+++ b/clang/test/Driver/aarch64-v93a.c
@@ -13,3 +13,72 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.3a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.3-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV93A-BE %s
// GENERICV93A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.3a"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv9.3-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// FIXME: FEAT_RME is optional from v9.1a
+// ARCH-EXTENSION: FEAT_RME
+// ARCH-EXTENSION: FEAT_NMI, FEAT_GICv3_NMI
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MEC
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_FP16 is optional from v8.2a, unless FEAT_SVE is implemented (see below)
+// ARCH-EXTENSION: FEAT_FP16
+// ARCH-EXTENSION: FEAT_HBC
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_MOPS
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// FIXME: FEAT_SVE is optional from v8.2a, unless FEAT_SVE2 is implemented (see below)
+// ARCH-EXTENSION: FEAT_SVE
+// FIXME: FEAT_SVE2 is optional from v9.0a
+// ARCH-EXTENSION: FEAT_SVE2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v94a.c b/clang/test/Driver/aarch64-v94a.c
index 9998cc8a4a216..67e7b9f2f13a1 100644
--- a/clang/test/Driver/aarch64-v94a.c
+++ b/clang/test/Driver/aarch64-v94a.c
@@ -13,3 +13,78 @@
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.4a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV94A-BE %s
// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9.4-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV94A-BE %s
// GENERICV94A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.4a"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv9.4-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// FIXME: FEAT_RME is optional from v9.1a
+// ARCH-EXTENSION: FEAT_RME
+// ARCH-EXTENSION: FEAT_NMI, FEAT_GICv3_NMI
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_CHK
+// ARCH-EXTENSION: FEAT_CLRBHB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MEC
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PRFMSLC
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_CSSC
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_FP16 is optional from v8.2a, unless FEAT_SVE is implemented (see below)
+// ARCH-EXTENSION: FEAT_FP16
+// ARCH-EXTENSION: FEAT_HBC
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_MOPS
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_SPECRES2
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_RASv2
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// FIXME: FEAT_SVE is optional from v8.2a, unless FEAT_SVE2 is implemented (see below)
+// ARCH-EXTENSION: FEAT_SVE
+// FIXME: FEAT_SVE2 is optional from v9.0a
+// ARCH-EXTENSION: FEAT_SVE2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v95a.c b/clang/test/Driver/aarch64-v95a.c
index 62878f2127626..33cadd1aaefb9 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -25,3 +25,81 @@
// RUN: %clang -target aarch64 -march=armv9.5a+tlbiw -### -c %s 2>&1 | FileCheck -check-prefix=V95A-TLBIW %s
// RUN: %clang -target aarch64 -march=armv9.5-a+tlbiw -### -c %s 2>&1 | FileCheck -check-prefix=V95A-TLBIW %s
// V95A-TLBIW: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+tlbiw"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv9.5-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_AMUv1p1 is optional from v8.6a
+// ARCH-EXTENSION: FEAT_AMUv1p1
+// FIXME: FEAT_RME is optional from v9.1a
+// ARCH-EXTENSION: FEAT_RME
+// ARCH-EXTENSION: FEAT_NMI, FEAT_GICv3_NMI
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_CHK
+// ARCH-EXTENSION: FEAT_CLRBHB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_ECV
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_FGT
+// ARCH-EXTENSION: FEAT_HCX
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MEC
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// ARCH-EXTENSION: FEAT_XS
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PRFMSLC
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_BF16
+// ARCH-EXTENSION: FEAT_CPA
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_CSSC
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FAMINMAX
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_FP16 is optional from v8.2a, unless FEAT_SVE is implemented (see below)
+// ARCH-EXTENSION: FEAT_FP16
+// ARCH-EXTENSION: FEAT_HBC
+// ARCH-EXTENSION: FEAT_I8MM
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_LUT
+// ARCH-EXTENSION: FEAT_MOPS
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_SPECRES2
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_RASv2
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// FIXME: FEAT_SVE is optional from v8.2a, unless FEAT_SVE2 is implemented (see below)
+// ARCH-EXTENSION: FEAT_SVE
+// FIXME: FEAT_SVE2 is optional from v9.0a
+// ARCH-EXTENSION: FEAT_SVE2
+// ARCH-EXTENSION: FEAT_WFxT
diff --git a/clang/test/Driver/aarch64-v9a.c b/clang/test/Driver/aarch64-v9a.c
new file mode 100644
index 0000000000000..23d74855e2bdb
--- /dev/null
+++ b/clang/test/Driver/aarch64-v9a.c
@@ -0,0 +1,72 @@
+// RUN: %clang --target=aarch64 -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
+// RUN: %clang --target=aarch64 -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
+// RUN: %clang --target=aarch64 -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
+// RUN: %clang --target=aarch64 -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
+// RUN: %clang --target=aarch64_be -mlittle-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
+// RUN: %clang --target=aarch64_be -mlittle-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A %s
+// GENERICV9A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9a"{{.*}} "-target-feature" "+sve" "-target-feature" "+sve2"
+
+// RUN: %clang --target=aarch64_be -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s
+// RUN: %clang --target=aarch64_be -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s
+// RUN: %clang --target=aarch64 -mbig-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s
+// RUN: %clang --target=aarch64 -mbig-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s
+// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s
+// RUN: %clang --target=aarch64_be -mbig-endian -march=armv9-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV9A-BE %s
+// GENERICV9A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9a"{{.*}} "-target-feature" "+sve" "-target-feature" "+sve2"
+
+// ===== Architecture extensions =====
+
+// RUN: %clang -target aarch64 -march=armv9-a --print-enabled-extensions 2>&1 | FileCheck -check-prefix=ARCH-EXTENSION --implicit-check-not FEAT_ %s
+// ARCH-EXTENSION: FEAT_TLBIOS, FEAT_TLBIRANGE
+// FIXME: FEAT_AMUv1 is optional from v8.4a
+// ARCH-EXTENSION: FEAT_AMUv1
+// FIXME: FEAT_RME is optional from v9.1a
+// ARCH-EXTENSION: FEAT_RME
+// ARCH-EXTENSION: FEAT_DPB
+// ARCH-EXTENSION: FEAT_DPB2
+// ARCH-EXTENSION: FEAT_ETE
+// ARCH-EXTENSION: FEAT_FRINTTS
+// ARCH-EXTENSION: FEAT_LOR
+// ARCH-EXTENSION: FEAT_CSV2_2
+// ARCH-EXTENSION: FEAT_LSE2
+// ARCH-EXTENSION: FEAT_MEC
+// FIXME: FEAT_MPAM is optional from v8.4a
+// ARCH-EXTENSION: FEAT_MPAM
+// ARCH-EXTENSION: FEAT_LRCPC2
+// ARCH-EXTENSION: FEAT_FlagM2
+// ARCH-EXTENSION: FEAT_TRF
+// ARCH-EXTENSION: FEAT_TRBE
+// ARCH-EXTENSION: FEAT_VHE
+// FIXME: FEAT_CCIDX is optional from v8.3a
+// ARCH-EXTENSION: FEAT_CCIDX
+// ARCH-EXTENSION: FEAT_UAO
+// ARCH-EXTENSION: FEAT_SEL2
+// ARCH-EXTENSION: FEAT_PAN2
+// ARCH-EXTENSION: FEAT_PAN
+// FIXME: FEAT_NV/FEAT_NV2 are optional from v8.4a
+// ARCH-EXTENSION: FEAT_NV, FEAT_NV2
+// ARCH-EXTENSION: FEAT_CRC32
+// ARCH-EXTENSION: FEAT_DIT
+// ARCH-EXTENSION: FEAT_DotProd
+// ARCH-EXTENSION: FEAT_FCMA
+// ARCH-EXTENSION: FEAT_FlagM
+// FIXME: FEAT_FP is optional from v8.0a
+// ARCH-EXTENSION: FEAT_FP
+// FIXME: FEAT_FP16 is optional from v8.2a, unless FEAT_SVE is implemented (see below)
+// ARCH-EXTENSION: FEAT_FP16
+// ARCH-EXTENSION: FEAT_JSCVT
+// ARCH-EXTENSION: FEAT_LSE
+// ARCH-EXTENSION: FEAT_PAuth
+// ARCH-EXTENSION: FEAT_SPECRES
+// ARCH-EXTENSION: FEAT_RAS, FEAT_RASv1p1
+// ARCH-EXTENSION: FEAT_LRCPC
+// ARCH-EXTENSION: FEAT_RDM
+// ARCH-EXTENSION: FEAT_SB
+// FIXME: FEAT_AdvSIMD is optional from v8.0a
+// ARCH-EXTENSION: FEAT_AdvSIMD
+// FIXME: FEAT_SSBS/FEAT_SSBS2 are optional from v8.0a
+// ARCH-EXTENSION: FEAT_SSBS, FEAT_SSBS2
+// FIXME: FEAT_SVE is optional from v8.2a, unless FEAT_SVE2 is implemented (see below)
+// ARCH-EXTENSION: FEAT_SVE
+// FIXME: FEAT_SVE2 is optional from v9.0a
+// ARCH-EXTENSION: FEAT_SVE2
diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index 3c008d2386482..6c0f48884494e 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -26,6 +26,7 @@
#include "clang/Frontend/Utils.h"
#include "clang/FrontendTool/Utils.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/ADT/StringExtras.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/LinkAllPasses.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -161,6 +162,39 @@ static int PrintSupportedExtensions(std::string TargetStr) {
return 0;
}
+static int PrintEnabledExtensions(const TargetOptions& TargetOpts) {
+ std::string Error;
+ const llvm::Target *TheTarget =
+ llvm::TargetRegistry::lookupTarget(TargetOpts.Triple, Error);
+ if (!TheTarget) {
+ llvm::errs() << Error;
+ return 1;
+ }
+
+ llvm::TargetOptions BackendOptions;
+ std::string FeaturesStr = llvm::join(TargetOpts.FeaturesAsWritten, ",");
+ std::unique_ptr<llvm::TargetMachine> TheTargetMachine(
+ TheTarget->createTargetMachine(TargetOpts.Triple, TargetOpts.CPU, FeaturesStr, BackendOptions, std::nullopt));
+ const llvm::Triple &MachineTriple = TheTargetMachine->getTargetTriple();
+ const llvm::MCSubtargetInfo *MCInfo = TheTargetMachine->getMCSubtargetInfo();
+ const std::vector<llvm::SubtargetFeatureKV> Features =
+ MCInfo->getEnabledProcessorFeatures();
+
+ std::vector<llvm::StringRef> EnabledFeatureNames;
+ for (const llvm::SubtargetFeatureKV &feature : Features)
+ EnabledFeatureNames.push_back(feature.Key);
+
+ if (!MachineTriple.isAArch64()) {
+ // The option was already checked in Driver::HandleImmediateArgs,
+ // so we do not expect to get here if we are not a supported architecture.
+ assert(0 && "Unhandled triple for --print-enabled-extensions option.");
+ return 1;
+ }
+ llvm::AArch64::printEnabledExtensions(EnabledFeatureNames);
+
+ return 0;
+}
+
int cc1_main(ArrayRef<const char *> Argv, const char *Argv0, void *MainAddr) {
ensureSufficientStack();
@@ -204,6 +238,10 @@ int cc1_main(ArrayRef<const char *> Argv, const char *Argv0, void *MainAddr) {
if (Clang->getFrontendOpts().PrintSupportedExtensions)
return PrintSupportedExtensions(Clang->getTargetOpts().Triple);
+ // --print-enabled-extensions takes priority over the actual compilation.
+ if (Clang->getFrontendOpts().PrintEnabledExtensions)
+ return PrintEnabledExtensions(Clang->getTargetOpts());
+
// Infer the builtin include path if unspecified.
if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
Clang->getHeaderSearchOpts().ResourceDir.empty())
diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h b/llvm/include/llvm/MC/MCSubtargetInfo.h
index ff76435d60843..deb7e2fd1c360 100644
--- a/llvm/include/llvm/MC/MCSubtargetInfo.h
+++ b/llvm/include/llvm/MC/MCSubtargetInfo.h
@@ -240,6 +240,9 @@ class MCSubtargetInfo {
return ProcFeatures;
}
+ /// Return the list of processor features currently enabled.
+ std::vector<SubtargetFeatureKV> getEnabledProcessorFeatures() const;
+
/// HwMode IDs are stored and accessed in a bit set format, enabling
/// users to efficiently retrieve specific IDs, such as the RegInfo
/// HwMode ID, from the set as required. Using this approach, various
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index bdcb02770c40b..d3a93da30437e 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -643,6 +643,8 @@ uint64_t getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs);
void PrintSupportedExtensions();
+void printEnabledExtensions(std::vector<StringRef> EnabledFeatureNames);
+
} // namespace AArch64
} // namespace llvm
diff --git a/llvm/lib/MC/MCSubtargetInfo.cpp b/llvm/lib/MC/MCSubtargetInfo.cpp
index cf3aba17fc3d4..1de0a9f66669a 100644
--- a/llvm/lib/MC/MCSubtargetInfo.cpp
+++ b/llvm/lib/MC/MCSubtargetInfo.cpp
@@ -336,6 +336,16 @@ void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
ForwardingPaths);
}
+std::vector<SubtargetFeatureKV>
+MCSubtargetInfo::getEnabledProcessorFeatures() const {
+ std::vector<SubtargetFeatureKV> EnabledFeatures;
+ auto IsEnabled = [&](const SubtargetFeatureKV &FeatureKV) {
+ return FeatureBits.test(FeatureKV.Value);
+ };
+ llvm::copy_if(ProcFeatures, std::back_inserter(EnabledFeatures), IsEnabled);
+ return EnabledFeatures;
+}
+
std::optional<unsigned> MCSubtargetInfo::getCacheSize(unsigned Level) const {
return std::nullopt;
}
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 7b53f1eeaa53f..e2b98917dfe6e 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -153,6 +153,26 @@ void AArch64::PrintSupportedExtensions() {
}
}
+void
+AArch64::printEnabledExtensions(std::vector<StringRef> EnabledFeatureNames) {
+ outs() << "Extensions enabled for the given AArch64 target\n\n"
+ << " " << left_justify("Architecture Feature(s)", 55)
+ << "Description\n";
+ auto IsEnabled = [&](const ExtensionInfo &Ext) {
+ StringRef FeatureName = Ext.TargetFeature.drop_front(); // drop '+' before comparing
+ return std::find(EnabledFeatureNames.begin(), EnabledFeatureNames.end(),
+ FeatureName) != EnabledFeatureNames.end();
+ };
+ for (const auto &Ext : Extensions) {
+ if (IsEnabled(Ext)) {
+ outs() << " "
+ << format("%-55s%s\n",
+ Ext.ArchFeatureName.str().c_str(),
+ Ext.Description.str().c_str());
+ }
+ }
+}
+
const llvm::AArch64::ExtensionInfo &
lookupExtensionByID(llvm::AArch64::ArchExtKind ExtID) {
for (const auto &E : llvm::AArch64::Extensions)
>From 41db23933f48532d6829c42f70bb6f7c13b2b810 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Tue, 18 Jun 2024 14:48:23 +0100
Subject: [PATCH 7/9] fixup! [AArch64] Add ability to list extensions enabled
for a target
---
clang/include/clang/Driver/Options.td | 2 +-
clang/lib/Basic/Targets/AArch64.cpp | 2 +-
clang/lib/Driver/ToolChain.cpp | 2 +-
clang/lib/Driver/ToolChains/Clang.cpp | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 14 ++++++++-----
llvm/lib/TargetParser/AArch64TargetParser.cpp | 20 +++++++++----------
6 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 6a520dc9e7062..f7f301035fff6 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5705,7 +5705,7 @@ def print_supported_extensions : Flag<["-", "--"], "print-supported-extensions">
MarshallingInfoFlag<FrontendOpts<"PrintSupportedExtensions">>;
def print_enabled_extensions : Flag<["-", "--"], "print-enabled-extensions">,
Visibility<[ClangOption, CC1Option, CLOption]>,
- HelpText<"Print the -march/-mcpu extensions enabled for the given target"
+ HelpText<"Print the extensions enabled by the given target and -march/-mcpu options."
" (AArch64 only)">,
MarshallingInfoFlag<FrontendOpts<"PrintEnabledExtensions">>;
def : Flag<["-"], "mcpu=help">, Alias<print_supported_cpus>;
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp
index b2c3e839b7e6c..9a446e2724d3c 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -1101,7 +1101,7 @@ bool AArch64TargetInfo::initFeatureMap(
std::optional<llvm::AArch64::ExtensionInfo> Extension =
llvm::AArch64::parseArchExtension(Feature.substr(1));
if (Extension)
- UpdatedFeature = Extension->TargetFeature.str();
+ UpdatedFeature = Extension->PosTargetFeature.str();
}
UpdatedFeaturesVec.push_back(UpdatedFeature);
}
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index a6f7ffaa0e7b1..8f4cc47e418b5 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -195,7 +195,7 @@ static void getAArch64MultilibFlags(const Driver &D,
UnifiedFeatures.end());
std::vector<std::string> MArch;
for (const auto &Ext : AArch64::Extensions)
- if (FeatureSet.contains(Ext.TargetFeature))
+ if (FeatureSet.contains(Ext.PosTargetFeature))
MArch.push_back(Ext.UserVisibleName.str());
for (const auto &Ext : AArch64::Extensions)
if (FeatureSet.contains(Ext.NegTargetFeature))
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 719ec1b41859b..c5ba98609e585 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1523,7 +1523,7 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args,
auto isPAuthLR = [](const char *member) {
llvm::AArch64::ExtensionInfo pauthlr_extension =
llvm::AArch64::getExtensionByID(llvm::AArch64::AEK_PAUTHLR);
- return pauthlr_extension.TargetFeature == member;
+ return pauthlr_extension.PosTargetFeature == member;
};
if (std::any_of(CmdArgs.begin(), CmdArgs.end(), isPAuthLR))
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index d3a93da30437e..c2fc38d4112ef 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -114,14 +114,18 @@ using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
// SubtargetFeature which may represent either an actual extension or some
// internal LLVM property.
struct ExtensionInfo {
- StringRef UserVisibleName; // Human readable name used in -march/-cpu, e.g. "profile"
+ StringRef UserVisibleName; // Human readable name used in -march, -cpu
+ // and target func attribute, e.g. "profile".
std::optional<StringRef> Alias; // An alias for this extension, if one exists.
ArchExtKind ID; // Corresponding to the ArchExtKind, this
// extensions representation in the bitfield.
- StringRef ArchFeatureName; // The feature name defined by the Architecture
- StringRef Description; // The textual description of the extension
- StringRef TargetFeature; // -target-feature/-mattr enable string, e.g. "+spe"
- StringRef NegTargetFeature; // -target-feature/-mattr disable string, e.g. "-spe"
+ StringRef ArchFeatureName; // The feature name defined by the
+ // Architecture, e.g. FEAT_AdvSIMD.
+ StringRef Description; // The textual description of the extension.
+ StringRef PosTargetFeature; // -target-feature/-mattr enable string,
+ // e.g. "+spe".
+ StringRef NegTargetFeature; // -target-feature/-mattr disable string,
+ // e.g. "-spe".
CPUFeatures CPUFeature; // Function Multi Versioning (FMV) bitfield value
// set in __aarch64_cpu_features
StringRef DependentFeatures; // FMV enabled features string,
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index e2b98917dfe6e..6d1f512169585 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -61,8 +61,8 @@ bool AArch64::getExtensionFeatures(
std::vector<StringRef> &Features) {
for (const auto &E : Extensions)
/* INVALID and NONE have no feature name. */
- if (InputExts.test(E.ID) && !E.TargetFeature.empty())
- Features.push_back(E.TargetFeature);
+ if (InputExts.test(E.ID) && !E.PosTargetFeature.empty())
+ Features.push_back(E.PosTargetFeature);
return true;
}
@@ -80,7 +80,7 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
if (auto AE = parseArchExtension(ArchExtBase)) {
// Note: the returned string can be empty.
- return IsNegated ? AE->NegTargetFeature : AE->TargetFeature;
+ return IsNegated ? AE->NegTargetFeature : AE->PosTargetFeature;
}
return StringRef();
@@ -115,9 +115,9 @@ const AArch64::ArchInfo *AArch64::parseArch(StringRef Arch) {
std::optional<AArch64::ExtensionInfo>
AArch64::parseArchExtension(StringRef ArchExt) {
+ if (ArchExt.empty())
+ return {};
for (const auto &A : Extensions) {
- if (A.UserVisibleName.empty() && !A.Alias)
- continue;
if (ArchExt == A.UserVisibleName || ArchExt == A.Alias)
return A;
}
@@ -143,7 +143,7 @@ void AArch64::PrintSupportedExtensions() {
<< "Description\n";
for (const auto &Ext : Extensions) {
// Extensions without a feature cannot be used with -march.
- if (!Ext.UserVisibleName.empty() && !Ext.TargetFeature.empty()) {
+ if (!Ext.UserVisibleName.empty() && !Ext.PosTargetFeature.empty()) {
outs() << " "
<< format(Ext.Description.empty() ? "%-20s%s\n" : "%-20s%-55s%s\n",
Ext.UserVisibleName.str().c_str(),
@@ -159,7 +159,7 @@ AArch64::printEnabledExtensions(std::vector<StringRef> EnabledFeatureNames) {
<< " " << left_justify("Architecture Feature(s)", 55)
<< "Description\n";
auto IsEnabled = [&](const ExtensionInfo &Ext) {
- StringRef FeatureName = Ext.TargetFeature.drop_front(); // drop '+' before comparing
+ StringRef FeatureName = Ext.PosTargetFeature.drop_front(); // drop '+' before comparing
return std::find(EnabledFeatureNames.begin(), EnabledFeatureNames.end(),
FeatureName) != EnabledFeatureNames.end();
};
@@ -243,10 +243,10 @@ void AArch64::ExtensionSet::toLLVMFeatureList(
Features.push_back(BaseArch->ArchFeature);
for (const auto &E : Extensions) {
- if (E.TargetFeature.empty() || !Touched.test(E.ID))
+ if (E.PosTargetFeature.empty() || !Touched.test(E.ID))
continue;
if (Enabled.test(E.ID))
- Features.push_back(E.TargetFeature);
+ Features.push_back(E.PosTargetFeature);
else
Features.push_back(E.NegTargetFeature);
}
@@ -278,7 +278,7 @@ bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) {
StringRef ArchExt = IsNegated ? Modifier.drop_front(2) : Modifier;
if (auto AE = parseArchExtension(ArchExt)) {
- if (AE->TargetFeature.empty() || AE->NegTargetFeature.empty())
+ if (AE->PosTargetFeature.empty() || AE->NegTargetFeature.empty())
return false;
if (IsNegated)
disable(AE->ID);
>From 707f49cef9a710457d9cf8f94a0ccfcb3b6f6898 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Tue, 18 Jun 2024 15:00:04 +0100
Subject: [PATCH 8/9] [AArch64][TargetParser] Add formatting test for
--print-enabled-extensios
---
.../unittests/TargetParser/TargetParserTest.cpp | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index d3ed905b96494..dd2299fdf274a 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2336,6 +2336,23 @@ TEST(TargetParserTest, AArch64PrintSupportedExtensions) {
EXPECT_EQ(std::string::npos, captured.find("ssbs2"));
}
+TEST(TargetParserTest, AArch64PrintEnabledExtensions) {
+ // Pick a single enabled extension to validate formatting
+ std::vector<StringRef> EnabledExtensions = {"crc"};
+ std::string ExpectedOutput =
+ "Extensions enabled for the given AArch64 target\n\n"
+ " Architecture Feature(s) Description\n"
+ " FEAT_CRC32 Enable ARMv8 CRC-32 checksum instructions\n";
+
+ outs().flush();
+ testing::internal::CaptureStdout();
+ AArch64::printEnabledExtensions(EnabledExtensions);
+ outs().flush();
+ std::string CapturedOutput = testing::internal::GetCapturedStdout();
+
+ EXPECT_EQ(CapturedOutput, ExpectedOutput);
+}
+
struct AArch64ExtensionDependenciesBaseArchTestParams {
const llvm::AArch64::ArchInfo &Arch;
std::vector<StringRef> Modifiers;
>From afeb489be3c41d3a370ea946bc1da996aff4c955 Mon Sep 17 00:00:00 2001
From: Lucas Prates <lucas.prates at arm.com>
Date: Tue, 18 Jun 2024 16:46:53 +0100
Subject: [PATCH 9/9] fixup! [AArch64] Add ability to list extensions enabled
for a target
---
llvm/lib/TargetParser/AArch64TargetParser.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 6d1f512169585..1b3a7d950a06d 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -185,7 +185,7 @@ void AArch64::ExtensionSet::enable(ArchExtKind E) {
if (Enabled.test(E))
return;
- LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).Name << "\n");
+ LLVM_DEBUG(llvm::dbgs() << "Enable " << lookupExtensionByID(E).UserVisibleName << "\n");
Touched.set(E);
Enabled.set(E);
@@ -226,7 +226,7 @@ void AArch64::ExtensionSet::disable(ArchExtKind E) {
if (!Enabled.test(E))
return;
- LLVM_DEBUG(llvm::dbgs() << "Disable " << lookupExtensionByID(E).Name << "\n");
+ LLVM_DEBUG(llvm::dbgs() << "Disable " << lookupExtensionByID(E).UserVisibleName << "\n");
Touched.set(E);
Enabled.reset(E);
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