[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Tue Jun 18 00:37:19 PDT 2024
================
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+ NoSchedModel,
+ !listconcat(RVA22S64Features,
+ [FeatureStdExtV,
+ FeatureStdExtSscofpmf,
+ FeatureStdExtSstc,
+ FeatureStdExtSvnapot,
+ FeatureStdExtZbc,
+ FeatureStdExtZbkc,
+ FeatureStdExtZfh,
+ FeatureStdExtZicond,
+ FeatureStdExtZmmul,
----------------
topperc wrote:
Please don't list Zmmul separate from M.
https://github.com/llvm/llvm-project/pull/94564
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