[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Shao-Ce SUN via cfe-commits]

================
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
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sunshaoce wrote:

This modification seems to cause the wrong information generated by `build/include/llvm/TargetParser/RISCVTargetParserDef.inc`. 

```c++
PROC(SIFIVE_X280, {"sifive-x280"}, {"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zifencei2p0_zfh1p0_zba1p0_zbb1p0_zvfh1p0_zvl512b1p0"}, 0)
PROC(SPACEMIT_X60, {"spacemit-x60"}, {"rv0v1p0_zicond1p0_zmmul1p0_zfh1p0_zbc1p0_zbkc1p0_zvfh1p0_zvkt1p0_zvl256b1p0_sscofpmf1p0_sstc1p0_svnapot1p0"}, 0)
PROC(SYNTACORE_SCR1_BASE, {"syntacore-scr1-base"}, {"rv32i2p1_c2p0_zicsr2p0_zifencei2p0"}, 0)
```

https://github.com/llvm/llvm-project/pull/94564