[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Pengcheng Wang via cfe-commits]

================
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
----------------
wangpc-pp wrote:

I think you can just add `RVA22S64` feature here, no `!listconcat` is needed as profiles are subtarget features now.
```
[RVI20U32,
 FeatureStdExtV,
 FeatureStdExtSscofpmf,
 ...
```

https://github.com/llvm/llvm-project/pull/94564