[clang] [llvm] [AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Sameer Sahasrabuddhe via cfe-commits]

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@@ -0,0 +1,46 @@
+# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
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ssahasra wrote:

All it needs is one new file in `test/CodeGen/AMDGPU` where 64-bit lane ops are used with a convergence tokens. Mark that as XFAIL. When the issue is fixed, that file can be merged into the existing tests. We don't need to test each of the convergence control intrinsics. It's enough to just have a token on a readlane.

https://github.com/llvm/llvm-project/pull/89217