[clang] [llvm] [RISCV] Add B extension (PR #76893)
Pengcheng Wang via cfe-commits
cfe-commits at lists.llvm.org
Mon Jun 10 23:06:03 PDT 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76893
>From 9ab05b9f68def57e9abb9d5ac65293b84aacc95a Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 4 Jan 2024 13:05:53 +0800
Subject: [PATCH] [RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
---
clang/test/Driver/riscv-arch.c | 5 -----
clang/test/Preprocessor/riscv-target-features.c | 12 ++++++++++++
llvm/docs/RISCVUsage.rst | 1 +
llvm/docs/ReleaseNotes.rst | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++++++
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 9 ++-------
7 files changed, 28 insertions(+), 12 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index ddf617bbb6237..ffd92e1f398c4 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -231,11 +231,6 @@
// RV32-STD: error: invalid arch name 'rv32imqc',
// RV32-STD: unsupported standard user-level extension 'q'
-// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ib -### %s \
-// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-B %s
-// RV32-B: error: invalid arch name 'rv32ib',
-// RV32-B: unsupported standard user-level extension 'b'
-
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s
// RV32X: error: invalid arch name 'rv32xabc',
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 09b9ad0a160bb..91307141e0406 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -7,6 +7,7 @@
// CHECK-NOT: __riscv_64e {{.*$}}
// CHECK-NOT: __riscv_a {{.*$}}
// CHECK-NOT: __riscv_atomic
+// CHECK-NOT: __riscv_b {{.*$}}
// CHECK-NOT: __riscv_c {{.*$}}
// CHECK-NOT: __riscv_compressed {{.*$}}
// CHECK-NOT: __riscv_d {{.*$}}
@@ -194,6 +195,17 @@
// CHECK-A-EXT: __riscv_a 2001000{{$}}
// CHECK-A-EXT: __riscv_atomic 1
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ib -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
+// CHECK-B-EXT: __riscv_b 1000000{{$}}
+// CHECK-B-EXT: __riscv_zba 1000000{{$}}
+// CHECK-B-EXT: __riscv_zbb 1000000{{$}}
+// CHECK-B-EXT: __riscv_zbs 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ic -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 35115e67ecf92..ef06f80c747f9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -85,6 +85,7 @@ on support follow.
Extension Status
================ =================================================================
``A`` Supported
+ ``B`` Supported
``C`` Supported
``D`` Supported
``F`` Supported
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 8cdb9db087c77..b46994bbcd66d 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -152,6 +152,7 @@ Changes to the RISC-V Backend
* Zaamo and Zalrsc are no longer experimental.
* Processors that enable post reg-alloc scheduling (PostMachineScheduler) by default should use the `UsePostRAScheduler` subtarget feature. Setting `PostRAScheduler = 1` in the scheduler model will have no effect on the enabling of the PostMachineScheduler.
* Zabha is no longer experimental.
+* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9bf06850483d8..011edca019fd6 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -477,6 +477,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
// Bitmanip Extensions for Cryptography Extensions
+def FeatureStdExtB
+ : RISCVExtension<"b", 1, 0,
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)",
+ [FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
+def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
+ AssemblerPredicate<(all_of FeatureStdExtB),
+ "'B' (the collection of the Zba, Zbb, Zbs extensions)">;
+
def FeatureStdExtZbkb
: RISCVExtension<"zbkb", 1, 0,
"'Zbkb' (Bitmanip instructions for Cryptography)">;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 1c9356fb1a05a..86b557700347e 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -5,6 +5,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32ZMMUL %s
; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s
; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s
+; RUN: llc -mtriple=riscv32 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV32B %s
; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s
; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s
; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s
@@ -131,6 +132,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
+; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
@@ -277,6 +279,7 @@
; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
; RV32A: .attribute 5, "rv32i2p1_a2p1"
+; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
; RV32C: .attribute 5, "rv32i2p1_c2p0"
@@ -402,6 +405,7 @@
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
; RV64A: .attribute 5, "rv64i2p1_a2p1"
+; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
; RV64C: .attribute 5, "rv64i2p1_c2p0"
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 22a8a05ef3719..128321fc3ae73 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -312,8 +312,6 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) {
}
TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
- EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64ib", true).takeError()),
- "unsupported standard user-level extension 'b'");
EXPECT_EQ(
toString(
RISCVISAInfo::parseArchString("rv32i_zmadeup", true).takeError()),
@@ -326,9 +324,6 @@ TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
toString(
RISCVISAInfo::parseArchString("rv64g_xmadeup", true).takeError()),
"unsupported non-standard user-level extension 'xmadeup'");
- EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rv64ib1p0", true).takeError()),
- "unsupported standard user-level extension 'b'");
EXPECT_EQ(
toString(
RISCVISAInfo::parseArchString("rv32i_zmadeup1p0", true).takeError()),
@@ -344,8 +339,7 @@ TEST(ParseArchString, RejectsUnrecognizedExtensionNamesByDefault) {
}
TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) {
- for (StringRef Input : {"rv32ib", "rv32i_zmadeup",
- "rv64i_smadeup", "rv64i_xmadeup"}) {
+ for (StringRef Input : {"rv32i_zmadeup", "rv64i_smadeup", "rv64i_xmadeup"}) {
auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true);
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
RISCVISAInfo &Info = **MaybeISAInfo;
@@ -913,6 +907,7 @@ R"(All available -march extensions for RISC-V
f 2.2
d 2.2
c 2.0
+ b 1.0
v 1.0
h 1.0
zic64b 1.0
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