[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

[Yingwei Zheng via cfe-commits]

================
@@ -381,3 +381,32 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_K1 : RISCVProcessorModel<"spacemit-k1",
+                                   NoSchedModel,
+                                   [Feature64Bit,
+                                    FeatureStdExtI,
+                                    FeatureStdExtM,
+                                    FeatureStdExtA,
+                                    FeatureStdExtF,
+                                    FeatureStdExtD,
+                                    FeatureStdExtC,
+                                    FeatureStdExtV,
+                                    FeatureStdExtZba,
+                                    FeatureStdExtZbb,
+                                    FeatureStdExtZbc,
+                                    FeatureStdExtZbs,
+                                    FeatureStdExtZbkb,
+                                    FeatureStdExtZbkc,
+                                    FeatureStdExtZfh,
+                                    FeatureStdExtZfhmin,
+                                    FeatureStdExtZicond,
+                                    FeatureStdExtZicsr,
+                                    FeatureStdExtZifencei,
+                                    FeatureStdExtZmmul,
+                                    FeatureStdExtZvfh,
+                                    FeatureStdExtZvfhmin,
+                                    FeatureStdExtZvl32b,
+                                    FeatureStdExtZvl64b,
+                                    FeatureStdExtZvl128b,
+                                    FeatureStdExtZvl256b]>;
----------------
dtcxzyw wrote:

RVA22 Profile also implies Zicntr, Ziccif, Ziccrse, Ziccamoa, Zicclsm, Za64rs, ...

See also https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#612-rva22u64-mandatory-extensions.

```suggestion
                                   !listconcat(RVA22S64Features, 
                                   [FeatureStdExtV,
                                     FeatureStdExtZvfh,
                                     FeatureStdExtZvfhmin,
                                     FeatureStdExtZvl32b,
                                     FeatureStdExtZvl64b,
                                     FeatureStdExtZvl128b,
                                     FeatureStdExtZvl256b])>;
```

https://github.com/llvm/llvm-project/pull/94564