[clang] [llvm] [AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Matt Arsenault via cfe-commits]

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@@ -1170,6 +1170,23 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
 
   :ref:`llvm.set.fpenv<int_set_fpenv>`             Sets the floating point environment to the specifies state.
 
+  llvm.amdgcn.readfirstlane                        Provides direct access to v_readfirstlane_b32. Returns the value in
+                                                   the lowest active lane of the input operand. Currently 
+                                                   implemented for i16, i32, float, half, bf16, v2i16, v2f16 and types 
+                                                   whose sizes are multiples of 32-bit.
+
+  llvm.amdgcn.readlane                             Provides direct access to v_readlane_b32. Returns the value in the 
+                                                   specified lane of the first input operand. The second operand 
+                                                   specifies the lane to read from. Currently implemented
+                                                   for i16, i32, float, half, bf16, v2i16, v2f16 and types whose sizes
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arsenm wrote:

Should probably try to avoid repeating all the same information on all 3 intrinsics 

https://github.com/llvm/llvm-project/pull/89217