[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

[Jay Foad via cfe-commits]

https://github.com/jayfoad commented:

LGTM overall.

> add f32 pattern to select read/writelane operations

Why would you need this? Don't you legalize f32 to i32?

https://github.com/llvm/llvm-project/pull/89217