[clang] [llvm] [AMDGPU][WIP] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (PR #89217)

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``````````bash
git-clang-format --diff 3d56ea05b6c746a7144f643bef2ebd599f605b8b d0610c47c0e2cb4bca5f90c289ffaa5c4178547f -- clang/lib/CodeGen/CGBuiltin.cpp llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 16d3219a16..b0a2bbeb61 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -5415,18 +5415,21 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
     Register Src0Valid = B.buildBitcast(S32, Src0).getReg(0);
     MachineInstrBuilder LaneOpDst;
     switch (IID) {
-      case Intrinsic::amdgcn_readfirstlane: {
-        LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid);
-        break;
-      }
-      case Intrinsic::amdgcn_readlane: {
-        LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid).addUse(Src1);
-        break;
-      }
-      case Intrinsic::amdgcn_writelane: {
-        Register Src2Valid = B.buildBitcast(S32, Src2).getReg(0);
-        LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid).addUse(Src1).addUse(Src2Valid);
-      }
+    case Intrinsic::amdgcn_readfirstlane: {
+      LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid);
+      break;
+    }
+    case Intrinsic::amdgcn_readlane: {
+      LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid).addUse(Src1);
+      break;
+    }
+    case Intrinsic::amdgcn_writelane: {
+      Register Src2Valid = B.buildBitcast(S32, Src2).getReg(0);
+      LaneOpDst = B.buildIntrinsic(IID, {S32})
+                      .addUse(Src0Valid)
+                      .addUse(Src1)
+                      .addUse(Src2Valid);
+    }
     }
 
     Register LaneOpDstReg = LaneOpDst.getReg(0);
@@ -5443,21 +5446,25 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
 
     MachineInstrBuilder LaneOpDst;
     switch (IID) {
-      case Intrinsic::amdgcn_readfirstlane: {
-        LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid);
-        break;
-      }
-      case Intrinsic::amdgcn_readlane: {
-        LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid).addUse(Src1);
-        break;
-      }
-      case Intrinsic::amdgcn_writelane: {
-        Register Src2Cast = MRI.getType(Src2).isScalar()
-                            ? Src2
-                            : B.buildBitcast(LLT::scalar(Size), Src2).getReg(0);
-        Register Src2Valid = B.buildAnyExt(LLT::scalar(32), Src2Cast).getReg(0);
-        LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid).addUse(Src1).addUse(Src2Valid);
-      }
+    case Intrinsic::amdgcn_readfirstlane: {
+      LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid);
+      break;
+    }
+    case Intrinsic::amdgcn_readlane: {
+      LaneOpDst = B.buildIntrinsic(IID, {S32}).addUse(Src0Valid).addUse(Src1);
+      break;
+    }
+    case Intrinsic::amdgcn_writelane: {
+      Register Src2Cast =
+          MRI.getType(Src2).isScalar()
+              ? Src2
+              : B.buildBitcast(LLT::scalar(Size), Src2).getReg(0);
+      Register Src2Valid = B.buildAnyExt(LLT::scalar(32), Src2Cast).getReg(0);
+      LaneOpDst = B.buildIntrinsic(IID, {S32})
+                      .addUse(Src0Valid)
+                      .addUse(Src1)
+                      .addUse(Src2Valid);
+    }
     }
 
     Register LaneOpDstReg = LaneOpDst.getReg(0);

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https://github.com/llvm/llvm-project/pull/89217