[clang] [llvm] [RISCV] Add processor definition and scheduling model for XiangShan-KunMingHu (PR #90392)
Yingwei Zheng via cfe-commits
cfe-commits at lists.llvm.org
Sun Apr 28 03:37:50 PDT 2024
=?utf-8?b?6YOd5bq36L6+?= <hebo at bosc.ac.cn>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/90392 at github.com>
================
@@ -378,3 +378,31 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
+ XiangShanKunMingHuModel,
+ [Feature64Bit,
+ FeatureStdExtI,
+ FeatureStdExtZicsr,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbc,
+ FeatureStdExtZbs,
+ FeatureStdExtZkn,
+ FeatureStdExtZksed,
+ FeatureStdExtZksh,
+ FeatureStdExtSvinval,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicboz,
+ FeatureStdExtV,
+ FeatureStdExtZvl128b],
+ [TuneNoDefaultUnroll,
----------------
dtcxzyw wrote:
See https://github.com/llvm/llvm-project/pull/89359#discussion_r1574366104
https://github.com/llvm/llvm-project/pull/90392
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