[clang] [llvm] [arm] Support reserving r4 and r5 alongside r9 (PR #88981)

[via cfe-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-arm

Author: None (benisxdxd)

<details>
<summary>Changes</summary>

I tried doing it like [this](https://github.com/llvm/llvm-project/commit/fcbec02ea6fb2a76352b64790cd9ae300f6a9943)

I'm not really an expert in LLVM and such so I don't really know where to add tests if needed.

---
Full diff: https://github.com/llvm/llvm-project/pull/88981.diff


5 Files Affected:

- (modified) clang/include/clang/Driver/Options.td (+4) 
- (modified) clang/lib/Driver/ToolChains/Arch/ARM.cpp (+7-1) 
- (modified) llvm/lib/Target/ARM/ARM.td (+10) 
- (modified) llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp (+6-1) 
- (modified) llvm/lib/Target/ARM/ARMSubtarget.h (+8) 


``````````diff
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index e24626913add76..bc7f51d72a3c72 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4754,6 +4754,10 @@ def mrestrict_it: Flag<["-"], "mrestrict-it">, Group<m_arm_Features_Group>,
 def mno_restrict_it: Flag<["-"], "mno-restrict-it">, Group<m_arm_Features_Group>,
   HelpText<"Allow generation of complex IT blocks.">;
 def marm : Flag<["-"], "marm">, Alias<mno_thumb>;
+def ffixed_r4 : Flag<["-"], "ffixed-r4">, Group<m_arm_Features_Group>,
+  HelpText<"Reserve the r4 register (ARM only)">;
+def ffixed_r5 : Flag<["-"], "ffixed-r5">, Group<m_arm_Features_Group>,
+  HelpText<"Reserve the r5 register (ARM only)">;
 def ffixed_r9 : Flag<["-"], "ffixed-r9">, Group<m_arm_Features_Group>,
   HelpText<"Reserve the r9 register (ARM only)">;
 def mno_movt : Flag<["-"], "mno-movt">, Group<m_arm_Features_Group>,
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index a68368c4758651..4c5d1fd55d1f82 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -915,8 +915,14 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
   }
 
   // llvm does not support reserving registers in general. There is support
-  // for reserving r9 on ARM though (defined as a platform-specific register
+  // for reserving r4,r5 and r9 on ARM though (defined as a platform-specific register
   // in ARM EABI).
+  if (Args.hasArg(options::OPT_ffixed_r4))
+    Features.push_back("+reserve-r4");
+
+  if (Args.hasArg(options::OPT_ffixed_r5))
+    Features.push_back("+reserve-r5");
+
   if (Args.hasArg(options::OPT_ffixed_r9))
     Features.push_back("+reserve-r9");
 
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 66596dbda83c95..782e6c5dfc091a 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -477,6 +477,16 @@ def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
                                              "Reserve R9, making it unavailable"
                                              " as GPR">;
 
+// True if R4 is not available as a general purpose register.
+def FeatureReserveR4      : SubtargetFeature<"reserve-r4", "ReserveR4", "true",
+                                             "Reserve R4, making it unavailable"
+                                             " as GPR">;
+
+// True if R5 is not available as a general purpose register.
+def FeatureReserveR5      : SubtargetFeature<"reserve-r5", "ReserveR5", "true",
+                                             "Reserve R5, making it unavailable"
+                                             " as GPR">;
+
 // True if MOVT / MOVW pairs are not used for materialization of
 // 32-bit imms (including global addresses).
 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 9adf758b46c481..81e16239d94008 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -211,7 +211,12 @@ getReservedRegs(const MachineFunction &MF) const {
     markSuperRegs(Reserved, STI.getFramePointerReg());
   if (hasBasePointer(MF))
     markSuperRegs(Reserved, BasePtr);
-  // Some targets reserve R9.
+
+  // Some targets reserve R4, R5 or R9.
+  if (STI.isReserveR4()) 
+    markSuperRegs(Reserved, ARM::R4);
+  if (STI.isReserveR5()) 
+    markSuperRegs(Reserved, ARM::R5);
   if (STI.isR9Reserved())
     markSuperRegs(Reserved, ARM::R9);
   // Reserve D16-D31 if the subtarget doesn't support them.
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 497ae160fde281..04f6abeba82f91 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -441,6 +441,14 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
     return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
   }
 
+  bool isR4Reserved() const {
+    return ReserveR4;
+  }
+
+  bool isR5Reserved() const {
+    return ReserveR5;
+  }
+
   MCPhysReg getFramePointerReg() const {
     if (isTargetDarwin() ||
         (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))

``````````

</details>


https://github.com/llvm/llvm-project/pull/88981