[clang] [llvm] [AArch64][SME] Add intrinsics for vector groups ZERO (PR #88114)

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@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -verify-machineinstrs < %s | FileCheck %s
+
+target triple = "aarch64-linux"
+
+define  void @test_svzero_za64_vg1x2(i32  %slice)  #0 {
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CarolineConcatto wrote:

Can you add tests for when slice is not zero. Something like:
define  void @test_svzero_za64_vg1x2(i32  %slice)  #0 {
 tail call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %slice)
%slice.max = add i32 %slice, 7
tail call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %slice.max)
ret void
}


https://github.com/llvm/llvm-project/pull/88114