[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)
via cfe-commits
cfe-commits at lists.llvm.org
Mon Apr 8 00:34:00 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
Author: Pengcheng Wang (wangpc-pp)
<details>
<summary>Changes</summary>
Remove them from experimental.
See also:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
---
Patch is 26.77 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/87966.diff
17 Files Affected:
- (modified) clang/test/Driver/riscv-profiles.c (+13-13)
- (modified) clang/test/Preprocessor/riscv-target-features.c (+18-18)
- (modified) llvm/docs/RISCVUsage.rst (-6)
- (modified) llvm/lib/Support/RISCVISAInfo.cpp (+12-14)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td (-2)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td (-2)
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+8-8)
- (modified) llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll (+1-1)
- (modified) llvm/test/MC/RISCV/attribute-arch.s (+1-1)
- (modified) llvm/test/MC/RISCV/compressed-zicfiss.s (+6-6)
- (modified) llvm/test/MC/RISCV/rv32zcmop-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zimop-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvzcmop-valid.s (+6-6)
- (modified) llvm/test/MC/RISCV/rvzimop-valid.s (+6-6)
- (modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+2-2)
``````````diff
diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c
index ec9206f2f45370..647567d4c971f4 100644
--- a/clang/test/Driver/riscv-profiles.c
+++ b/clang/test/Driver/riscv-profiles.c
@@ -111,7 +111,7 @@
// RVA22S64: "-target-feature" "+svinval"
// RVA22S64: "-target-feature" "+svpbmt"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 \
// RUN: | FileCheck -check-prefix=RVA23U64 %s
// RVA23U64: "-target-feature" "+m"
// RVA23U64: "-target-feature" "+a"
@@ -133,13 +133,13 @@
// RVA23U64: "-target-feature" "+zihintntl"
// RVA23U64: "-target-feature" "+zihintpause"
// RVA23U64: "-target-feature" "+zihpm"
-// RVA23U64: "-target-feature" "+experimental-zimop"
+// RVA23U64: "-target-feature" "+zimop"
// RVA23U64: "-target-feature" "+za64rs"
// RVA23U64: "-target-feature" "+zawrs"
// RVA23U64: "-target-feature" "+zfa"
// RVA23U64: "-target-feature" "+zfhmin"
// RVA23U64: "-target-feature" "+zcb"
-// RVA23U64: "-target-feature" "+experimental-zcmop"
+// RVA23U64: "-target-feature" "+zcmop"
// RVA23U64: "-target-feature" "+zba"
// RVA23U64: "-target-feature" "+zbb"
// RVA23U64: "-target-feature" "+zbs"
@@ -172,13 +172,13 @@
// RVA23S64: "-target-feature" "+zihintntl"
// RVA23S64: "-target-feature" "+zihintpause"
// RVA23S64: "-target-feature" "+zihpm"
-// RVA23S64: "-target-feature" "+experimental-zimop"
+// RVA23S64: "-target-feature" "+zimop"
// RVA23S64: "-target-feature" "+za64rs"
// RVA23S64: "-target-feature" "+zawrs"
// RVA23S64: "-target-feature" "+zfa"
// RVA23S64: "-target-feature" "+zfhmin"
// RVA23S64: "-target-feature" "+zcb"
-// RVA23S64: "-target-feature" "+experimental-zcmop"
+// RVA23S64: "-target-feature" "+zcmop"
// RVA23S64: "-target-feature" "+zba"
// RVA23S64: "-target-feature" "+zbb"
// RVA23S64: "-target-feature" "+zbs"
@@ -207,7 +207,7 @@
// RVA23S64: "-target-feature" "+svnapot"
// RVA23S64: "-target-feature" "+svpbmt"
-// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 -menable-experimental-extensions \
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 \
// RUN: | FileCheck -check-prefix=RVB23U64 %s
// RVB23U64: "-target-feature" "+m"
// RVB23U64: "-target-feature" "+a"
@@ -228,12 +228,12 @@
// RVB23U64: "-target-feature" "+zihintntl"
// RVB23U64: "-target-feature" "+zihintpause"
// RVB23U64: "-target-feature" "+zihpm"
-// RVB23U64: "-target-feature" "+experimental-zimop"
+// RVB23U64: "-target-feature" "+zimop"
// RVB23U64: "-target-feature" "+za64rs"
// RVB23U64: "-target-feature" "+zawrs"
// RVB23U64: "-target-feature" "+zfa"
// RVB23U64: "-target-feature" "+zcb"
-// RVB23U64: "-target-feature" "+experimental-zcmop"
+// RVB23U64: "-target-feature" "+zcmop"
// RVB23U64: "-target-feature" "+zba"
// RVB23U64: "-target-feature" "+zbb"
// RVB23U64: "-target-feature" "+zbs"
@@ -261,12 +261,12 @@
// RVB23S64: "-target-feature" "+zihintntl"
// RVB23S64: "-target-feature" "+zihintpause"
// RVB23S64: "-target-feature" "+zihpm"
-// RVB23S64: "-target-feature" "+experimental-zimop"
+// RVB23S64: "-target-feature" "+zimop"
// RVB23S64: "-target-feature" "+za64rs"
// RVB23S64: "-target-feature" "+zawrs"
// RVB23S64: "-target-feature" "+zfa"
// RVB23S64: "-target-feature" "+zcb"
-// RVB23S64: "-target-feature" "+experimental-zcmop"
+// RVB23S64: "-target-feature" "+zcmop"
// RVB23S64: "-target-feature" "+zba"
// RVB23S64: "-target-feature" "+zbb"
// RVB23S64: "-target-feature" "+zbs"
@@ -284,7 +284,7 @@
// RVB23S64: "-target-feature" "+svnapot"
// RVB23S64: "-target-feature" "+svpbmt"
-// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 -menable-experimental-extensions \
+// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 \
// RUN: | FileCheck -check-prefix=RVM23U32 %s
// RVM23U32: "-target-feature" "+m"
// RVM23U32: "-target-feature" "+zicbop"
@@ -292,9 +292,9 @@
// RVM23U32: "-target-feature" "+zicsr"
// RVM23U32: "-target-feature" "+zihintntl"
// RVM23U32: "-target-feature" "+zihintpause"
-// RVM23U32: "-target-feature" "+experimental-zimop"
+// RVM23U32: "-target-feature" "+zimop"
// RVM23U32: "-target-feature" "+zce"
-// RVM23U32: "-target-feature" "+experimental-zcmop"
+// RVM23U32: "-target-feature" "+zcmop"
// RVM23U32: "-target-feature" "+zba"
// RVM23U32: "-target-feature" "+zbb"
// RVM23U32: "-target-feature" "+zbs"
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index dfc6d18dee504e..ec7764bb538189 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -92,6 +92,7 @@
// CHECK-NOT: __riscv_zcd {{.*$}}
// CHECK-NOT: __riscv_zce {{.*$}}
// CHECK-NOT: __riscv_zcf {{.*$}}
+// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zcmp {{.*$}}
// CHECK-NOT: __riscv_zcmt {{.*$}}
// CHECK-NOT: __riscv_zdinx {{.*$}}
@@ -116,6 +117,7 @@
// CHECK-NOT: __riscv_zihintntl {{.*$}}
// CHECK-NOT: __riscv_zihintpause {{.*$}}
// CHECK-NOT: __riscv_zihpm {{.*$}}
+// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_zk {{.*$}}
// CHECK-NOT: __riscv_zkn {{.*$}}
// CHECK-NOT: __riscv_zknd {{.*$}}
@@ -173,11 +175,9 @@
// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zalasr {{.*$}}
// CHECK-NOT: __riscv_zalrsc {{.*$}}
-// CHECK-NOT: __riscv_zcmop {{.*$}}
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zicfilp {{.*$}}
// CHECK-NOT: __riscv_zicfiss {{.*$}}
-// CHECK-NOT: __riscv_zimop {{.*$}}
// CHECK-NOT: __riscv_ztso {{.*$}}
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
@@ -830,6 +830,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_zcmop1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64i_zcmop1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
+// CHECK-ZCMOP-EXT: __riscv_zcmop 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izcmp1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMP-EXT %s
@@ -1018,6 +1026,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHPM-EXT %s
// CHECK-ZIHPM-EXT: __riscv_zihpm 2000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_zimop1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64i_zimop1p0 -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
+// CHECK-ZIMOP-EXT: __riscv_zimop 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32izk1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZK-EXT %s
@@ -1561,22 +1577,6 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s
// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zimop0p1 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zimop0p1 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s
-// CHECK-ZIMOP-EXT: __riscv_zimop 1000{{$}}
-
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zcmop0p2 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zcmop0p2 -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s
-// CHECK-ZCMOP-EXT: __riscv_zcmop 2000{{$}}
-
// RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32iztso0p1 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2f17c9d7dda04a..283f258d7e5f07 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -271,12 +271,6 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-ztso``
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
-``experimental-zimop``
- LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>`__.
-
-``experimental-zcmop``
- LLVM implements the `v0.2 proposed specification <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>`__.
-
``experimental-zaamo``, ``experimental-zalrsc``
LLVM implements the `v0.2 proposed specification <https://github.com/riscv/riscv-zaamo-zalrsc/releases/tag/v0.2>`__.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 67e6e5b962b1a9..7a19d24d1ff483 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -134,6 +134,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zcd", {1, 0}},
{"zce", {1, 0}},
{"zcf", {1, 0}},
+ {"zcmop", {1, 0}},
{"zcmp", {1, 0}},
{"zcmt", {1, 0}},
@@ -162,6 +163,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"zihintntl", {1, 0}},
{"zihintpause", {2, 0}},
{"zihpm", {2, 0}},
+ {"zimop", {1, 0}},
{"zk", {1, 0}},
{"zkn", {1, 0}},
@@ -233,15 +235,11 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zalasr", {0, 1}},
{"zalrsc", {0, 2}},
- {"zcmop", {0, 2}},
-
{"zfbfmin", {1, 0}},
{"zicfilp", {0, 4}},
{"zicfiss", {0, 4}},
- {"zimop", {0, 1}},
-
{"ztso", {0, 1}},
{"zvfbfmin", {1, 0}},
@@ -264,25 +262,25 @@ static constexpr RISCVProfile SupportedProfiles[] = {
"sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
{"rva23u64",
"rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
- "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_"
+ "zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
{"rva23s64",
"rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_"
- "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"
+ "zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_"
"shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
"sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
"svbare_svinval_svnapot_svpbmt"},
{"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
"zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
- "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+ "zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"},
{"rvb23s64",
"rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
- "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_"
- "zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_"
- "sstvala_sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
- {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop0p1_"
- "zca_zcb_zce_zcmop0p2_zcmp_zcmt_zba_zbb_zbs"},
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_"
+ "zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_"
+ "sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
+ {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_"
+ "zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"},
};
static void verifyTables() {
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6ef2289bb4beeb..794455aa730400 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -104,7 +104,7 @@ def FeatureStdExtZihpm
"'Zihpm' (Hardware Performance Counters)",
[FeatureStdExtZicsr]>;
-def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true",
+def FeatureStdExtZimop : SubtargetFeature<"zimop", "HasStdExtZimop", "true",
"'Zimop' (May-Be-Operations)">;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
@@ -390,7 +390,7 @@ def HasStdExtCOrZcfOrZce
"'C' (Compressed Instructions) or "
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true",
+def FeatureStdExtZcmop : SubtargetFeature<"zcmop", "HasStdExtZcmop", "true",
"'Zcmop' (Compressed May-Be-Operations)",
[FeatureStdExtZca]>;
def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td
index 6fbfde5ef488c5..dd13a07d606d04 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td
@@ -8,8 +8,6 @@
//
// This file describes the RISC-V instructions from the standard Compressed
// May-Be-Operations Extension (Zcmop).
-// This version is still experimental as the 'Zcmop' extension hasn't been
-// ratified yet. It is based on v0.2 of the specification.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td
index f8ec099ca81973..6b26550a290269 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td
@@ -8,8 +8,6 @@
//
// This file describes the RISC-V instructions from the standard
// May-Be-Operations Extension (Zimop).
-// This version is still experimental as the 'Zimop' extension hasn't been
-// ratified yet. It is based on v0.1 of the specification.
//
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index cc332df271043f..2326599bf35136 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -103,8 +103,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s
; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
@@ -233,8 +233,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s
; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
@@ -358,8 +358,8 @@
; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
-; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1"
-; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2"
+; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0"
+; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0"
; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
@@ -487,8 +487,8 @@
; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0"
; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
-; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1"
-; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2"
+; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0"
+; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0"
; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
diff --git a/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
index e5f36086f1cfcd..8e843fa47db69b 100644
--- a/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zimop -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32ZIMOP
declare i32 @llvm.riscv.mopr.i32(i32 %a, i32 %b)
diff --git a/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
index cd57739a955d5e..a407fe552ff74d 100644
--- a/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zimop -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZIMOP
declare i64 @llvm.riscv.mopr.i64(i64 %a, i64 %b)
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 09daeee2c1b385..a8f493f781ec3d 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -394,7 +394,7 @@
# CHECK: attribute 5, "rv32i2p1_zicfilp0p4"
.attribute arch, "rv32i_zicfiss0p4"
-# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop0p1"
+# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/87966
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