[clang] [llvm] MIPS: Support -m(no-)unaligned-access for r6 (PR #85174)
YunQiang Su via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 13 21:10:26 PDT 2024
https://github.com/wzssyqa created https://github.com/llvm/llvm-project/pull/85174
MIPSr6 ISA requires normal load/store instructions support misunaligned memory access, while it is not always do so by hardware. On some microarchitectures or some corner cases it may need support by OS.
Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't support them, instead, r6 requires lw instruction support misunaligned memory access. So, if -mno-unaligned-access is used for pre-R6, lwl/lwr won't be disabled.
If -mno-unaligned-access is used for r6 and the access is not well aligned, some lb/lh instructions will be used to replace lw. This is useful for OS kernels.
>From a74a9bbd2ff2c6589db4c9756cf809c22e98fa64 Mon Sep 17 00:00:00 2001
From: YunQiang Su <syq at gcc.gnu.org>
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)unaligned-access for r6
MIPSr6 ISA requires normal load/store instructions support
misunaligned memory access, while it is not always do so
by hardware. On some microarchitectures or some corner cases
it may need support by OS.
Don't confuse with pre-R6's lwl/lwr famlily: MIPSr6 doesn't
support them, instead, r6 requires lw instruction support
misunaligned memory access. So, if -mno-unaligned-access is
used for pre-R6, lwl/lwr won't be disabled.
If -mno-unaligned-access is used for r6 and the access is
not well aligned, some lb/lh instructions will be used to replace
lw. This is useful for OS kernels.
---
clang/include/clang/Driver/Options.td | 4 +-
clang/lib/Driver/ToolChains/Arch/Mips.cpp | 2 +
clang/test/Driver/mips-features.c | 26 +++++++
llvm/lib/Target/Mips/Mips.td | 4 ++
llvm/lib/Target/Mips/MipsISelLowering.cpp | 16 ++++-
llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 11 ++-
llvm/lib/Target/Mips/MipsSubtarget.cpp | 1 +
llvm/lib/Target/Mips/MipsSubtarget.h | 7 +-
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 10 +--
.../CodeGen/Mips/no-unaligned-access-r6.ll | 69 +++++++++++++++++++
10 files changed, 138 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 1fac7b6f0093d8..6d3645f0a66828 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4696,9 +4696,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>,
" (RISC-V only)")>;
def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
- HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch/RISC-V only)">;
+ HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch/MIPS/RISC-V only)">;
def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_Group>,
- HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch/RISC-V only)">;
+ HelpText<"Force all memory accesses to be aligned (AArch32/AArch64/LoongArch/MIPS/RISC-V only)">;
def munaligned_symbols : Flag<["-"], "munaligned-symbols">, Group<m_Group>,
HelpText<"Expect external char-aligned symbols to be without ABI alignment (SystemZ only)">;
def mno_unaligned_symbols : Flag<["-"], "mno-unaligned-symbols">, Group<m_Group>,
diff --git a/clang/lib/Driver/ToolChains/Arch/Mips.cpp b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
index fe9d112b8800b1..1de11811dccbc1 100644
--- a/clang/lib/Driver/ToolChains/Arch/Mips.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -341,6 +341,8 @@ void mips::getMIPSTargetFeatures(const Driver &D, const llvm::Triple &Triple,
"dspr2");
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+ AddTargetFeature(Args, Features, options::OPT_mno_unaligned_access,
+ options::OPT_munaligned_access, "no-unaligned-access");
// Add the last -mfp32/-mfpxx/-mfp64, if none are given and the ABI is O32
// pass -mfpxx, or if none are given and fp64a is default, pass fp64 and
diff --git a/clang/test/Driver/mips-features.c b/clang/test/Driver/mips-features.c
index fd06b1400c3123..9e724b34e869d4 100644
--- a/clang/test/Driver/mips-features.c
+++ b/clang/test/Driver/mips-features.c
@@ -462,3 +462,29 @@
// RUN: -mrelax-pic-calls -mno-relax-pic-calls 2>&1 \
// RUN: | FileCheck --check-prefix=CHECK-NO-RELAX-PIC-CALLS %s
// CHECK-NO-RELAX-PIC-CALLS: "-mllvm" "-mips-jalr-reloc=0"
+//
+// -mno-unaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mno-unaligned-access 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-NO-UNALIGNED-ACCESS %s
+// CHECK-NO-UNALIGNED-ACCESS: "-target-feature" "+no-unaligned-access"
+//
+// -munaligned-access
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -munaligned-access 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-UNALIGNED-ACCESS %s
+// CHECK-UNALIGNED-ACCESS: "-target-feature" "-no-unaligned-access"
+//
+// -mstrict-align
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -munaligned-access -mno-strict-align \
+// RUN: -mstrict-align 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-NO-UNALIGNED-ACCESS %s
+//
+// -mno-strict-align
+// RUN: %clang -target mips-unknown-linux-gnu -### -c %s \
+// RUN: -mno-unaligned-access -mstrict-align \
+// RUN: -mno-strict-align 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-UNALIGNED-ACCESS %s
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index dbff25dfa0f36c..e768394dbc8192 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -208,6 +208,10 @@ def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
"true", "Use indirect jump"
" guards to prevent certain speculation based attacks">;
+def FeatureNoUnalignedAccess
+ : SubtargetFeature<"no-unaligned-access", "NoUnalignedAccess", "true",
+ "Disable unaligned load store for r6">;
+
//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 7e5f148e7bf4e7..0a0d40751fcf05 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -365,8 +365,13 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::SELECT, MVT::i64, Custom);
- setOperationAction(ISD::LOAD, MVT::i64, Custom);
- setOperationAction(ISD::STORE, MVT::i64, Custom);
+ if (Subtarget.hasMips64r6()) {
+ setOperationAction(ISD::LOAD, MVT::i64, Legal);
+ setOperationAction(ISD::STORE, MVT::i64, Legal);
+ } else {
+ setOperationAction(ISD::LOAD, MVT::i64, Custom);
+ setOperationAction(ISD::STORE, MVT::i64, Custom);
+ }
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
@@ -481,7 +486,12 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
if (!Subtarget.hasMips64r2())
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
- if (Subtarget.isGP64bit()) {
+ if (Subtarget.isGP64bit() && Subtarget.hasMips64r6()) {
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Legal);
+ setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Legal);
+ setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Legal);
+ setTruncStoreAction(MVT::i64, MVT::i32, Legal);
+ } else if (Subtarget.isGP64bit()) {
setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index b87d13cea787dd..5c8d64e3b6e3cc 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -197,8 +197,13 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
- setOperationAction(ISD::LOAD, MVT::i32, Custom);
- setOperationAction(ISD::STORE, MVT::i32, Custom);
+ if (Subtarget.hasMips32r6()) {
+ setOperationAction(ISD::LOAD, MVT::i32, Legal);
+ setOperationAction(ISD::STORE, MVT::i32, Legal);
+ } else {
+ setOperationAction(ISD::LOAD, MVT::i32, Custom);
+ setOperationAction(ISD::STORE, MVT::i32, Custom);
+ }
setTargetDAGCombine(ISD::MUL);
@@ -425,6 +430,8 @@ bool MipsSETargetLowering::allowsMisalignedMemoryAccesses(
if (Fast)
*Fast = 1;
return true;
+ } else if (Subtarget.hasMips32r6()) {
+ return false;
}
switch (SVT) {
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 0134fcb341f187..29b277f5f3f073 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -83,6 +83,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
+ NoUnalignedAccess(false),
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
TSInfo(), InstrInfo(MipsInstrInfo::create(
initializeSubtargetDependencies(CPU, FS, TM))),
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 225ee139d036f3..44c9b13b38bb3e 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -200,6 +200,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
// Assume 32-bit GOT.
bool UseXGOT = false;
+ // Disable unaligned load store for r6.
+ bool NoUnalignedAccess;
+
/// The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
Align stackAlignment;
@@ -372,7 +375,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
/// MIPS32r6/MIPS64r6 require full unaligned access support but does not
/// specify which component of the system provides it. Hardware, software, and
/// hybrid implementations are all valid.
- bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
+ bool systemSupportsUnalignedAccess() const {
+ return hasMips32r6() && !NoUnalignedAccess;
+ }
// Set helper classes
void setHelperClassesMips16();
diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
index 6a27c9f5dac9b2..45c7ab980edd64 100644
--- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
@@ -405,8 +405,9 @@ define void @uitofp(i32 %a) {
; MIPS64-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
; MIPS64-N32-NEXT: lui $2, 17200
; MIPS64-N32-NEXT: sw $2, 12($sp)
-; MIPS64-N32-NEXT: sll $2, $4, 0
-; MIPS64-N32-NEXT: sw $2, 8($sp)
+; MIPS64R5-N32-NEXT: sll $2, $4, 0
+; MIPS64R5-N32-NEXT: sw $2, 8($sp)
+; MIPSR6-N32-NEXT: sw $4, 8($sp)
; MIPS64-N32-NEXT: lw $2, %got_page(.LCPI5_0)($1)
; MIPS64-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
; MIPS64-N32-NEXT: ldc1 $f1, 8($sp)
@@ -430,8 +431,9 @@ define void @uitofp(i32 %a) {
; MIPS64-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
; MIPS64-N64-NEXT: lui $2, 17200
; MIPS64-N64-NEXT: sw $2, 12($sp)
-; MIPS64-N64-NEXT: sll $2, $4, 0
-; MIPS64-N64-NEXT: sw $2, 8($sp)
+; MIPS64R5-N64-NEXT: sll $2, $4, 0
+; MIPS64R5-N64-NEXT: sw $2, 8($sp)
+; MIPSR6-N64-NEXT: sw $4, 8($sp)
; MIPS64-N64-NEXT: ld $2, %got_page(.LCPI5_0)($1)
; MIPS64-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
; MIPS64-N64-NEXT: ldc1 $f1, 8($sp)
diff --git a/llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll b/llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll
new file mode 100644
index 00000000000000..1bd8f053cbeebb
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/no-unaligned-access-r6.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+;; Test the no-unaligned-access feature which is similar to AArch64/arm64-strict-align.ll.
+
+; RUN: llc --mtriple=mipsisa32r6 < %s | FileCheck %s --check-prefix=MIPS32R6-UNALIGNED
+; RUN: llc --mtriple=mipsisa32r6 --mattr=-no-unaligned-access < %s | FileCheck %s --check-prefix=MIPS32R6-UNALIGNED
+; RUN: llc --mtriple=mipsisa32r6 --mattr=+no-unaligned-access < %s | FileCheck %s --check-prefix=MIPS32R6-ALIGNED
+
+; RUN: llc --mtriple=mipsisa64r6 < %s | FileCheck %s --check-prefix=MIPS64R6-UNALIGNED
+; RUN: llc --mtriple=mipsisa64r6 --mattr=-no-unaligned-access < %s | FileCheck %s --check-prefix=MIPS64R6-UNALIGNED
+; RUN: llc --mtriple=mipsisa64r6 --mattr=+no-unaligned-access < %s | FileCheck %s --check-prefix=MIPS64R6-ALIGNED
+
+define i32 @f0(ptr %p) nounwind {
+; MIPS32R6-UNALIGNED-LABEL: f0:
+; MIPS32R6-UNALIGNED: # %bb.0:
+; MIPS32R6-UNALIGNED-NEXT: lw $2, 0($4)
+; MIPS32R6-UNALIGNED-NEXT: jrc $ra
+;
+; MIPS32R6-ALIGNED-LABEL: f0:
+; MIPS32R6-ALIGNED: # %bb.0:
+; MIPS32R6-ALIGNED-NEXT: lhu $1, 2($4)
+; MIPS32R6-ALIGNED-NEXT: lhu $2, 0($4)
+; MIPS32R6-ALIGNED-NEXT: sll $2, $2, 16
+; MIPS32R6-ALIGNED-NEXT: jr $ra
+; MIPS32R6-ALIGNED-NEXT: or $2, $2, $1
+;
+; MIPS64R6-UNALIGNED-LABEL: f0:
+; MIPS64R6-UNALIGNED: # %bb.0:
+; MIPS64R6-UNALIGNED-NEXT: lw $2, 0($4)
+; MIPS64R6-UNALIGNED-NEXT: jrc $ra
+;
+; MIPS64R6-ALIGNED-LABEL: f0:
+; MIPS64R6-ALIGNED: # %bb.0:
+; MIPS64R6-ALIGNED-NEXT: lhu $1, 2($4)
+; MIPS64R6-ALIGNED-NEXT: lhu $2, 0($4)
+; MIPS64R6-ALIGNED-NEXT: sll $2, $2, 16
+; MIPS64R6-ALIGNED-NEXT: jr $ra
+; MIPS64R6-ALIGNED-NEXT: or $2, $2, $1
+ %tmp = load i32, ptr %p, align 2
+ ret i32 %tmp
+}
+
+define i64 @f1(ptr %p) nounwind {
+; MIPS32R6-UNALIGNED-LABEL: f1:
+; MIPS32R6-UNALIGNED: # %bb.0:
+; MIPS32R6-UNALIGNED-NEXT: lw $2, 0($4)
+; MIPS32R6-UNALIGNED-NEXT: lw $3, 4($4)
+; MIPS32R6-UNALIGNED-NEXT: jrc $ra
+;
+; MIPS32R6-ALIGNED-LABEL: f1:
+; MIPS32R6-ALIGNED: # %bb.0:
+; MIPS32R6-ALIGNED-NEXT: lw $2, 0($4)
+; MIPS32R6-ALIGNED-NEXT: lw $3, 4($4)
+; MIPS32R6-ALIGNED-NEXT: jrc $ra
+;
+; MIPS64R6-UNALIGNED-LABEL: f1:
+; MIPS64R6-UNALIGNED: # %bb.0:
+; MIPS64R6-UNALIGNED-NEXT: ld $2, 0($4)
+; MIPS64R6-UNALIGNED-NEXT: jrc $ra
+;
+; MIPS64R6-ALIGNED-LABEL: f1:
+; MIPS64R6-ALIGNED: # %bb.0:
+; MIPS64R6-ALIGNED-NEXT: lwu $1, 4($4)
+; MIPS64R6-ALIGNED-NEXT: lwu $2, 0($4)
+; MIPS64R6-ALIGNED-NEXT: dsll $2, $2, 32
+; MIPS64R6-ALIGNED-NEXT: jr $ra
+; MIPS64R6-ALIGNED-NEXT: or $2, $2, $1
+ %tmp = load i64, ptr %p, align 4
+ ret i64 %tmp
+}
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