[clang] 207e45f - [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896)
via cfe-commits
cfe-commits at lists.llvm.org
Wed Mar 13 14:56:28 PDT 2024
Author: Craig Topper
Date: 2024-03-13T14:56:25-07:00
New Revision: 207e45fb67ee3dbec9590d9303eebf4f720c8a40
URL: https://github.com/llvm/llvm-project/commit/207e45fb67ee3dbec9590d9303eebf4f720c8a40
DIFF: https://github.com/llvm/llvm-project/commit/207e45fb67ee3dbec9590d9303eebf4f720c8a40.diff
LOG: [RISCV] Add back SiFive's cdiscard.d.l1, cflush.d.l1, and cease instructions. (#83896)
These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.
This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally for
some time. It uses XSiFive instead of XSf like the newer extensions.
`cease` did not have an internal extension name so its using the `XSf`
convention.
The spec for the instructions is here
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.
Column width in the extension printing had to be changed to accommodate
a longer extension name.
Added:
llvm/test/MC/RISCV/xsifive-invalid.s
llvm/test/MC/RISCV/xsifive-valid.s
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
llvm/unittests/Support/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 1a15be1c6e4dc1..b2cad622610bfc 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -56,11 +56,14 @@
// CHECK-NOT: __riscv_xcvmac {{.*$}}
// CHECK-NOT: __riscv_xcvmem {{.*$}}
// CHECK-NOT: __riscv_xcvsimd {{.*$}}
+// CHECK-NOT: __riscv_xsfcease {{.*$}}
// CHECK-NOT: __riscv_xsfvcp {{.*$}}
// CHECK-NOT: __riscv_xsfvfnrclipxfqf {{.*$}}
// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_xsifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_xsifivecflushdlone {{.*$}}
// CHECK-NOT: __riscv_xtheadba {{.*$}}
// CHECK-NOT: __riscv_xtheadbb {{.*$}}
// CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -517,6 +520,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XCVSIMD-EXT %s
// CHECK-XCVSIMD-EXT: __riscv_xcvsimd 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ixsfcease -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCEASE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ixsfcease -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSFCEASE-EXT %s
+// CHECK-XSFCEASE-EXT: __riscv_xsfcease 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ixsfvcp -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVCP-EXT %s
@@ -557,6 +568,22 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
// CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 1000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ixtheadba -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a1de8596480da9..2f17c9d7dda04a 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -362,6 +362,15 @@ The current vendor extensions supported are:
``XCVbi``
LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+``XSiFivecdiscarddlone``
+ LLVM implements `the SiFive sf.cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+
+``XSiFivecflushdlone``
+ LLVM implements `the SiFive sf.cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+
+``XSfcease``
+ LLVM implements `the SiFive sf.cease instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+
Experimental C Intrinsics
=========================
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 6eec03fd6f7082..39235ace472483 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -90,11 +90,14 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xcvmac", {1, 0}},
{"xcvmem", {1, 0}},
{"xcvsimd", {1, 0}},
+ {"xsfcease", {1, 0}},
{"xsfvcp", {1, 0}},
{"xsfvfnrclipxfqf", {1, 0}},
{"xsfvfwmaccqqq", {1, 0}},
{"xsfvqmaccdod", {1, 0}},
{"xsfvqmaccqoq", {1, 0}},
+ {"xsifivecdiscarddlone", {1, 0}},
+ {"xsifivecflushdlone", {1, 0}},
{"xtheadba", {1, 0}},
{"xtheadbb", {1, 0}},
{"xtheadbs", {1, 0}},
@@ -258,7 +261,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
StringRef Description) {
outs().indent(4);
unsigned VersionWidth = Description.empty() ? 0 : 10;
- outs() << left_justify(Name, 20) << left_justify(Version, VersionWidth)
+ outs() << left_justify(Name, 21) << left_justify(Version, VersionWidth)
<< Description << "\n";
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index f1ca1212ec378e..6aadabdf1bc61a 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -595,6 +595,14 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
+ DecoderTableXSiFivecdiscarddlone32,
+ "SiFive sf.cdiscard.d.l1 custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
+ DecoderTableXSiFivecflushdlone32,
+ "SiFive sf.cflush.d.l1 custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
+ "SiFive sf.cease custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 83619ccb24baa3..f3e641e250182b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1058,6 +1058,30 @@ def HasVendorXSfvfnrclipxfqf
AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
+def FeatureVendorXSiFivecdiscarddlone
+ : SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
+ "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
+def HasVendorXSiFivecdiscarddlone
+ : Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
+ AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
+ "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
+
+def FeatureVendorXSiFivecflushdlone
+ : SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
+ "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
+def HasVendorXSiFivecflushdlone
+ : Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
+ AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
+ "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
+
+def FeatureVendorXSfcease
+ : SubtargetFeature<"xsfcease", "HasVendorXSfcease", "true",
+ "'XSfcease' (SiFive sf.cease Instruction)", []>;
+def HasVendorXSfcease
+ : Predicate<"Subtarget->hasVendorXSfcease()">,
+ AssemblerPredicate<(all_of FeatureVendorXSfcease),
+ "'XSfcease' (SiFive sf.cease Instruction)">;
+
// Core-V Extensions
def FeatureVendorXCVelw
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index b4130e3805a110..9a6818c99af206 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -808,3 +808,35 @@ let Predicates = [HasVendorXSfvfnrclipxfqf] in {
defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">;
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">;
}
+
+let Predicates = [HasVendorXSiFivecdiscarddlone] in {
+ let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSiFivecdiscarddlone" in
+ def SF_CDISCARD_D_L1
+ : RVInstIUnary<0b111111000010, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
+ "sf.cdiscard.d.l1", "$rs1">, Sched<[]> {
+ let rd = 0;
+ }
+ def : InstAlias<"sf.cdiscard.d.l1", (SF_CDISCARD_D_L1 X0)>;
+} // Predicates = [HasVendorXSifivecdiscarddlone]
+
+let Predicates = [HasVendorXSiFivecflushdlone] in {
+ let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSiFivecflushdlone" in
+ def SF_CFLUSH_D_L1
+ : RVInstIUnary<0b111111000000, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
+ "sf.cflush.d.l1", "$rs1">, Sched<[]> {
+ let rd = 0;
+ }
+ def : InstAlias<"sf.cflush.d.l1", (SF_CFLUSH_D_L1 X0)>;
+} // Predicates = [HasVendorXSifivecflushdlone]
+
+let Predicates = [HasVendorXSfcease] in {
+ let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSfcease" in
+ def SF_CEASE : RVInstIUnary<0b001100000101, 0b000, OPC_SYSTEM, (outs), (ins),
+ "sf.cease", "">, Sched<[]> {
+ let rs1 = 0b00000;
+ let rd = 0b00000;
+}
+}
diff --git a/llvm/test/MC/RISCV/xsifive-invalid.s b/llvm/test/MC/RISCV/xsifive-invalid.s
new file mode 100644
index 00000000000000..5210d29f9d3630
--- /dev/null
+++ b/llvm/test/MC/RISCV/xsifive-invalid.s
@@ -0,0 +1,20 @@
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
+
+sf.cflush.d.l1 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sf.cdiscard.d.l1 0x10 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
+
+sf.cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
+
+sf.cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
+
+sf.cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
+
+sf.cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
+
+sf.cease x1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+
+sf.cease 0x10 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+
+sf.cease # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSfcease' (SiFive sf.cease Instruction){{$}}
diff --git a/llvm/test/MC/RISCV/xsifive-valid.s b/llvm/test/MC/RISCV/xsifive-valid.s
new file mode 100644
index 00000000000000..8aa0ab1bd8ba3b
--- /dev/null
+++ b/llvm/test/MC/RISCV/xsifive-valid.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease < %s \
+# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease < %s \
+# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone,+xsfcease -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: sf.cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+sf.cflush.d.l1 x0
+# CHECK-INST: sf.cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+sf.cflush.d.l1
+
+# CHECK-INST: sf.cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+sf.cflush.d.l1 x7
+
+# CHECK-INST: sf.cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+sf.cdiscard.d.l1 x0
+# CHECK-INST: sf.cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+sf.cdiscard.d.l1
+
+# CHECK-INST: sf.cdiscard.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+sf.cdiscard.d.l1 x7
+
+# CHECK-INST: sf.cease
+# CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
+sf.cease
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 82cf4c639b6160..a331e6a74ceb63 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -739,170 +739,173 @@ TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
R"(All available -march extensions for RISC-V
- Name Version Description
- i 2.1 This is a long dummy description
- e 2.0
- m 2.0
- a 2.1
- f 2.2
- d 2.2
- c 2.0
- v 1.0
- h 1.0
- zic64b 1.0
- zicbom 1.0
- zicbop 1.0
- zicboz 1.0
- ziccamoa 1.0
- ziccif 1.0
- zicclsm 1.0
- ziccrse 1.0
- zicntr 2.0
- zicond 1.0
- zicsr 2.0
- zifencei 2.0
- zihintntl 1.0
- zihintpause 2.0
- zihpm 2.0
- zmmul 1.0
- za128rs 1.0
- za64rs 1.0
- zacas 1.0
- zawrs 1.0
- zfa 1.0
- zfh 1.0
- zfhmin 1.0
- zfinx 1.0
- zdinx 1.0
- zca 1.0
- zcb 1.0
- zcd 1.0
- zce 1.0
- zcf 1.0
- zcmp 1.0
- zcmt 1.0
- zba 1.0
- zbb 1.0
- zbc 1.0
- zbkb 1.0
- zbkc 1.0
- zbkx 1.0
- zbs 1.0
- zk 1.0
- zkn 1.0
- zknd 1.0
- zkne 1.0
- zknh 1.0
- zkr 1.0
- zks 1.0
- zksed 1.0
- zksh 1.0
- zkt 1.0
- zvbb 1.0
- zvbc 1.0
- zve32f 1.0
- zve32x 1.0
- zve64d 1.0
- zve64f 1.0
- zve64x 1.0
- zvfh 1.0
- zvfhmin 1.0
- zvkb 1.0
- zvkg 1.0
- zvkn 1.0
- zvknc 1.0
- zvkned 1.0
- zvkng 1.0
- zvknha 1.0
- zvknhb 1.0
- zvks 1.0
- zvksc 1.0
- zvksed 1.0
- zvksg 1.0
- zvksh 1.0
- zvkt 1.0
- zvl1024b 1.0
- zvl128b 1.0
- zvl16384b 1.0
- zvl2048b 1.0
- zvl256b 1.0
- zvl32768b 1.0
- zvl32b 1.0
- zvl4096b 1.0
- zvl512b 1.0
- zvl64b 1.0
- zvl65536b 1.0
- zvl8192b 1.0
- zhinx 1.0
- zhinxmin 1.0
- shcounterenw 1.0
- shgatpa 1.0
- shtvala 1.0
- shvsatpa 1.0
- shvstvala 1.0
- shvstvecd 1.0
- smaia 1.0
- smepmp 1.0
- ssaia 1.0
- ssccptr 1.0
- sscofpmf 1.0
- sscounterenw 1.0
- ssstateen 1.0
- ssstrict 1.0
- sstc 1.0
- sstvala 1.0
- sstvecd 1.0
- ssu64xl 1.0
- svade 1.0
- svadu 1.0
- svbare 1.0
- svinval 1.0
- svnapot 1.0
- svpbmt 1.0
- xcvalu 1.0
- xcvbi 1.0
- xcvbitmanip 1.0
- xcvelw 1.0
- xcvmac 1.0
- xcvmem 1.0
- xcvsimd 1.0
- xsfvcp 1.0
- xsfvfnrclipxfqf 1.0
- xsfvfwmaccqqq 1.0
- xsfvqmaccdod 1.0
- xsfvqmaccqoq 1.0
- xtheadba 1.0
- xtheadbb 1.0
- xtheadbs 1.0
- xtheadcmo 1.0
- xtheadcondmov 1.0
- xtheadfmemidx 1.0
- xtheadmac 1.0
- xtheadmemidx 1.0
- xtheadmempair 1.0
- xtheadsync 1.0
- xtheadvdot 1.0
- xventanacondops 1.0
+ Name Version Description
+ i 2.1 This is a long dummy description
+ e 2.0
+ m 2.0
+ a 2.1
+ f 2.2
+ d 2.2
+ c 2.0
+ v 1.0
+ h 1.0
+ zic64b 1.0
+ zicbom 1.0
+ zicbop 1.0
+ zicboz 1.0
+ ziccamoa 1.0
+ ziccif 1.0
+ zicclsm 1.0
+ ziccrse 1.0
+ zicntr 2.0
+ zicond 1.0
+ zicsr 2.0
+ zifencei 2.0
+ zihintntl 1.0
+ zihintpause 2.0
+ zihpm 2.0
+ zmmul 1.0
+ za128rs 1.0
+ za64rs 1.0
+ zacas 1.0
+ zawrs 1.0
+ zfa 1.0
+ zfh 1.0
+ zfhmin 1.0
+ zfinx 1.0
+ zdinx 1.0
+ zca 1.0
+ zcb 1.0
+ zcd 1.0
+ zce 1.0
+ zcf 1.0
+ zcmp 1.0
+ zcmt 1.0
+ zba 1.0
+ zbb 1.0
+ zbc 1.0
+ zbkb 1.0
+ zbkc 1.0
+ zbkx 1.0
+ zbs 1.0
+ zk 1.0
+ zkn 1.0
+ zknd 1.0
+ zkne 1.0
+ zknh 1.0
+ zkr 1.0
+ zks 1.0
+ zksed 1.0
+ zksh 1.0
+ zkt 1.0
+ zvbb 1.0
+ zvbc 1.0
+ zve32f 1.0
+ zve32x 1.0
+ zve64d 1.0
+ zve64f 1.0
+ zve64x 1.0
+ zvfh 1.0
+ zvfhmin 1.0
+ zvkb 1.0
+ zvkg 1.0
+ zvkn 1.0
+ zvknc 1.0
+ zvkned 1.0
+ zvkng 1.0
+ zvknha 1.0
+ zvknhb 1.0
+ zvks 1.0
+ zvksc 1.0
+ zvksed 1.0
+ zvksg 1.0
+ zvksh 1.0
+ zvkt 1.0
+ zvl1024b 1.0
+ zvl128b 1.0
+ zvl16384b 1.0
+ zvl2048b 1.0
+ zvl256b 1.0
+ zvl32768b 1.0
+ zvl32b 1.0
+ zvl4096b 1.0
+ zvl512b 1.0
+ zvl64b 1.0
+ zvl65536b 1.0
+ zvl8192b 1.0
+ zhinx 1.0
+ zhinxmin 1.0
+ shcounterenw 1.0
+ shgatpa 1.0
+ shtvala 1.0
+ shvsatpa 1.0
+ shvstvala 1.0
+ shvstvecd 1.0
+ smaia 1.0
+ smepmp 1.0
+ ssaia 1.0
+ ssccptr 1.0
+ sscofpmf 1.0
+ sscounterenw 1.0
+ ssstateen 1.0
+ ssstrict 1.0
+ sstc 1.0
+ sstvala 1.0
+ sstvecd 1.0
+ ssu64xl 1.0
+ svade 1.0
+ svadu 1.0
+ svbare 1.0
+ svinval 1.0
+ svnapot 1.0
+ svpbmt 1.0
+ xcvalu 1.0
+ xcvbi 1.0
+ xcvbitmanip 1.0
+ xcvelw 1.0
+ xcvmac 1.0
+ xcvmem 1.0
+ xcvsimd 1.0
+ xsfcease 1.0
+ xsfvcp 1.0
+ xsfvfnrclipxfqf 1.0
+ xsfvfwmaccqqq 1.0
+ xsfvqmaccdod 1.0
+ xsfvqmaccqoq 1.0
+ xsifivecdiscarddlone 1.0
+ xsifivecflushdlone 1.0
+ xtheadba 1.0
+ xtheadbb 1.0
+ xtheadbs 1.0
+ xtheadcmo 1.0
+ xtheadcondmov 1.0
+ xtheadfmemidx 1.0
+ xtheadmac 1.0
+ xtheadmemidx 1.0
+ xtheadmempair 1.0
+ xtheadsync 1.0
+ xtheadvdot 1.0
+ xventanacondops 1.0
Experimental extensions
- zicfilp 0.4 This is a long dummy description
- zicfiss 0.4
- zimop 0.1
- zaamo 0.2
- zabha 1.0
- zalasr 0.1
- zalrsc 0.2
- zfbfmin 1.0
- zcmop 0.2
- ztso 0.1
- zvfbfmin 1.0
- zvfbfwma 1.0
- smmpm 0.8
- smnpm 0.8
- ssnpm 0.8
- sspm 0.8
- ssqosid 1.0
- supm 0.8
+ zicfilp 0.4 This is a long dummy description
+ zicfiss 0.4
+ zimop 0.1
+ zaamo 0.2
+ zabha 1.0
+ zalasr 0.1
+ zalrsc 0.2
+ zfbfmin 1.0
+ zcmop 0.2
+ ztso 0.1
+ zvfbfmin 1.0
+ zvfbfwma 1.0
+ smmpm 0.8
+ smnpm 0.8
+ ssnpm 0.8
+ sspm 0.8
+ ssqosid 1.0
+ supm 0.8
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
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