[clang] [llvm] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1 instructions. (PR #83896)
Craig Topper via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 5 21:19:07 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/83896
>From 9434f834c4d48559aeec94403c927f48b15763e3 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 4 Mar 2024 11:24:34 -0800
Subject: [PATCH 1/4] [RISCV] Add back SiFive's cdiscard.d.l1 and cflush.d.l1
instructions.
These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.
This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally
for some time. It uses XSiFive instead of XSf like the newer extensions.
The spec for the instructions is here https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.
Column width in the extension printing had to be changed to accomodate
a longer extension name.
---
.../test/Preprocessor/riscv-target-features.c | 18 +
llvm/docs/RISCVUsage.rst | 6 +
llvm/lib/Support/RISCVISAInfo.cpp | 4 +-
.../RISCV/Disassembler/RISCVDisassembler.cpp | 6 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 16 +
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 22 ++
llvm/unittests/Support/RISCVISAInfoTest.cpp | 324 +++++++++---------
7 files changed, 234 insertions(+), 162 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 664279cb123949..f8d4800aabbb44 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,6 +60,8 @@
// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
+// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
// CHECK-NOT: __riscv_xtheadba {{.*$}}
// CHECK-NOT: __riscv_xtheadbb {{.*$}}
// CHECK-NOT: __riscv_xtheadbs {{.*$}}
@@ -548,6 +550,22 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XSFVQMACCQOQ-EXT %s
// CHECK-XSFVQMACCQOQ-EXT: __riscv_xsfvqmaccqoq 1000000{{$}}
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ixsifivecdiscarddlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ixsifivecdiscarddlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECDISCARDDLONE-EXT %s
+// CHECK-XSIFIVECDISCARDDLONE-EXT: __riscv_xsifivecdiscarddlone 1000000{{$}}
+
+// RUN: %clang --target=riscv32-unknown-linux-gnu \
+// RUN: -march=rv32ixsifivecflushdlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// RUN: %clang --target=riscv64-unknown-linux-gnu \
+// RUN: -march=rv64ixsifivecflushdlone -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-XSIFIVECFLUSHDLONE-EXT %s
+// CHECK-XSIFIVECFLUSHDLONE-EXT: __riscv_xsifivecflushdlone 1000000{{$}}
+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
// RUN: -march=rv32ixtheadba -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADBA-EXT %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 8d293b02144307..f1e2e86390c838 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -352,6 +352,12 @@ The current vendor extensions supported are:
``XCVbi``
LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+``XSiFivecdiscarddlone``
+ LLVM implements `the SiFive cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+
+``XSiFivecflushdlone``
+ LLVM implements `the SiFive cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+
Experimental C Intrinsics
=========================
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 68f5c36e8fafc6..8dbb40f97bf338 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -94,6 +94,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"xsfvfwmaccqqq", {1, 0}},
{"xsfvqmaccdod", {1, 0}},
{"xsfvqmaccqoq", {1, 0}},
+ {"xsifivecdiscarddlone", {1, 0}},
+ {"xsifivecflushdlone", {1, 0}},
{"xtheadba", {1, 0}},
{"xtheadbb", {1, 0}},
{"xtheadbs", {1, 0}},
@@ -257,7 +259,7 @@ static void PrintExtension(StringRef Name, StringRef Version,
StringRef Description) {
outs().indent(4);
unsigned VersionWidth = Description.empty() ? 0 : 10;
- outs() << left_justify(Name, 20) << left_justify(Version, VersionWidth)
+ outs() << left_justify(Name, 21) << left_justify(Version, VersionWidth)
<< Description << "\n";
}
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index f1ca1212ec378e..00518653cc494e 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -595,6 +595,12 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
+ DecoderTableXSiFivecdiscarddlone32,
+ "SiFive cdiscard.d.l1 custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
+ DecoderTableXSiFivecflushdlone32,
+ "SiFive cflush.d.l1 custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 9773b2998c7dc4..fb47e5f76c5e2e 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1054,6 +1054,22 @@ def HasVendorXSfvfnrclipxfqf
AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
+def FeatureVendorXSiFivecdiscarddlone
+ : SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
+ "'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction)", []>;
+def HasVendorXSiFivecdiscarddlone
+ : Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
+ AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
+ "'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction)">;
+
+def FeatureVendorXSiFivecflushdlone
+ : SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
+ "'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction)", []>;
+def HasVendorXSiFivecflushdlone
+ : Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
+ AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
+ "'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction)">;
+
// Core-V Extensions
def FeatureVendorXCVelw
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index b4130e3805a110..a7601724300b64 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -808,3 +808,25 @@ let Predicates = [HasVendorXSfvfnrclipxfqf] in {
defm : VPatVFNRCLIP<"vfnrclip_xu_f_qf", "VFNRCLIP_XU_F_QF">;
defm : VPatVFNRCLIP<"vfnrclip_x_f_qf", "VFNRCLIP_X_F_QF">;
}
+
+let Predicates = [HasVendorXSiFivecdiscarddlone] in {
+ let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSiFivecdiscarddlone" in
+ def SF_CDISCARD_D_L1
+ : RVInstR<0b1111110, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
+ "cdiscard.d.l1", "$rs1">, Sched<[]> {
+ let rd = 0;
+ let rs2 = 0b00010;
+ }
+} // Predicates = [HasVendorXSifivecdiscarddlone]
+
+let Predicates = [HasVendorXSiFivecflushdlone] in {
+ let hasNoSchedulingInfo = 1, hasSideEffects = 1, mayLoad = 0, mayStore = 0,
+ DecoderNamespace = "XSiFivecflushdlone" in
+ def SF_CFLUSH_D_L1
+ : RVInstR<0b1111110, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
+ "cflush.d.l1", "$rs1">, Sched<[]> {
+ let rd = 0;
+ let rs2 = 0b00000;
+ }
+} // Predicates = [HasVendorXSifivecflushdlone]
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 82cce23638d5f5..95560f34420146 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -724,169 +724,171 @@ TEST(RiscvExtensionsHelp, CheckExtensions) {
std::string ExpectedOutput =
R"(All available -march extensions for RISC-V
- Name Version Description
- i 2.1 This is a long dummy description
- e 2.0
- m 2.0
- a 2.1
- f 2.2
- d 2.2
- c 2.0
- v 1.0
- h 1.0
- zic64b 1.0
- zicbom 1.0
- zicbop 1.0
- zicboz 1.0
- ziccamoa 1.0
- ziccif 1.0
- zicclsm 1.0
- ziccrse 1.0
- zicntr 2.0
- zicond 1.0
- zicsr 2.0
- zifencei 2.0
- zihintntl 1.0
- zihintpause 2.0
- zihpm 2.0
- zmmul 1.0
- za128rs 1.0
- za64rs 1.0
- zacas 1.0
- zawrs 1.0
- zfa 1.0
- zfh 1.0
- zfhmin 1.0
- zfinx 1.0
- zdinx 1.0
- zca 1.0
- zcb 1.0
- zcd 1.0
- zce 1.0
- zcf 1.0
- zcmp 1.0
- zcmt 1.0
- zba 1.0
- zbb 1.0
- zbc 1.0
- zbkb 1.0
- zbkc 1.0
- zbkx 1.0
- zbs 1.0
- zk 1.0
- zkn 1.0
- zknd 1.0
- zkne 1.0
- zknh 1.0
- zkr 1.0
- zks 1.0
- zksed 1.0
- zksh 1.0
- zkt 1.0
- zvbb 1.0
- zvbc 1.0
- zve32f 1.0
- zve32x 1.0
- zve64d 1.0
- zve64f 1.0
- zve64x 1.0
- zvfh 1.0
- zvfhmin 1.0
- zvkb 1.0
- zvkg 1.0
- zvkn 1.0
- zvknc 1.0
- zvkned 1.0
- zvkng 1.0
- zvknha 1.0
- zvknhb 1.0
- zvks 1.0
- zvksc 1.0
- zvksed 1.0
- zvksg 1.0
- zvksh 1.0
- zvkt 1.0
- zvl1024b 1.0
- zvl128b 1.0
- zvl16384b 1.0
- zvl2048b 1.0
- zvl256b 1.0
- zvl32768b 1.0
- zvl32b 1.0
- zvl4096b 1.0
- zvl512b 1.0
- zvl64b 1.0
- zvl65536b 1.0
- zvl8192b 1.0
- zhinx 1.0
- zhinxmin 1.0
- shcounterenw 1.0
- shgatpa 1.0
- shtvala 1.0
- shvsatpa 1.0
- shvstvala 1.0
- shvstvecd 1.0
- smaia 1.0
- smepmp 1.0
- ssaia 1.0
- ssccptr 1.0
- sscounterenw 1.0
- ssstateen 1.0
- ssstrict 1.0
- sstc 1.0
- sstvala 1.0
- sstvecd 1.0
- ssu64xl 1.0
- svade 1.0
- svadu 1.0
- svbare 1.0
- svinval 1.0
- svnapot 1.0
- svpbmt 1.0
- xcvalu 1.0
- xcvbi 1.0
- xcvbitmanip 1.0
- xcvelw 1.0
- xcvmac 1.0
- xcvmem 1.0
- xcvsimd 1.0
- xsfvcp 1.0
- xsfvfnrclipxfqf 1.0
- xsfvfwmaccqqq 1.0
- xsfvqmaccdod 1.0
- xsfvqmaccqoq 1.0
- xtheadba 1.0
- xtheadbb 1.0
- xtheadbs 1.0
- xtheadcmo 1.0
- xtheadcondmov 1.0
- xtheadfmemidx 1.0
- xtheadmac 1.0
- xtheadmemidx 1.0
- xtheadmempair 1.0
- xtheadsync 1.0
- xtheadvdot 1.0
- xventanacondops 1.0
+ Name Version Description
+ i 2.1 This is a long dummy description
+ e 2.0
+ m 2.0
+ a 2.1
+ f 2.2
+ d 2.2
+ c 2.0
+ v 1.0
+ h 1.0
+ zic64b 1.0
+ zicbom 1.0
+ zicbop 1.0
+ zicboz 1.0
+ ziccamoa 1.0
+ ziccif 1.0
+ zicclsm 1.0
+ ziccrse 1.0
+ zicntr 2.0
+ zicond 1.0
+ zicsr 2.0
+ zifencei 2.0
+ zihintntl 1.0
+ zihintpause 2.0
+ zihpm 2.0
+ zmmul 1.0
+ za128rs 1.0
+ za64rs 1.0
+ zacas 1.0
+ zawrs 1.0
+ zfa 1.0
+ zfh 1.0
+ zfhmin 1.0
+ zfinx 1.0
+ zdinx 1.0
+ zca 1.0
+ zcb 1.0
+ zcd 1.0
+ zce 1.0
+ zcf 1.0
+ zcmp 1.0
+ zcmt 1.0
+ zba 1.0
+ zbb 1.0
+ zbc 1.0
+ zbkb 1.0
+ zbkc 1.0
+ zbkx 1.0
+ zbs 1.0
+ zk 1.0
+ zkn 1.0
+ zknd 1.0
+ zkne 1.0
+ zknh 1.0
+ zkr 1.0
+ zks 1.0
+ zksed 1.0
+ zksh 1.0
+ zkt 1.0
+ zvbb 1.0
+ zvbc 1.0
+ zve32f 1.0
+ zve32x 1.0
+ zve64d 1.0
+ zve64f 1.0
+ zve64x 1.0
+ zvfh 1.0
+ zvfhmin 1.0
+ zvkb 1.0
+ zvkg 1.0
+ zvkn 1.0
+ zvknc 1.0
+ zvkned 1.0
+ zvkng 1.0
+ zvknha 1.0
+ zvknhb 1.0
+ zvks 1.0
+ zvksc 1.0
+ zvksed 1.0
+ zvksg 1.0
+ zvksh 1.0
+ zvkt 1.0
+ zvl1024b 1.0
+ zvl128b 1.0
+ zvl16384b 1.0
+ zvl2048b 1.0
+ zvl256b 1.0
+ zvl32768b 1.0
+ zvl32b 1.0
+ zvl4096b 1.0
+ zvl512b 1.0
+ zvl64b 1.0
+ zvl65536b 1.0
+ zvl8192b 1.0
+ zhinx 1.0
+ zhinxmin 1.0
+ shcounterenw 1.0
+ shgatpa 1.0
+ shtvala 1.0
+ shvsatpa 1.0
+ shvstvala 1.0
+ shvstvecd 1.0
+ smaia 1.0
+ smepmp 1.0
+ ssaia 1.0
+ ssccptr 1.0
+ sscounterenw 1.0
+ ssstateen 1.0
+ ssstrict 1.0
+ sstc 1.0
+ sstvala 1.0
+ sstvecd 1.0
+ ssu64xl 1.0
+ svade 1.0
+ svadu 1.0
+ svbare 1.0
+ svinval 1.0
+ svnapot 1.0
+ svpbmt 1.0
+ xcvalu 1.0
+ xcvbi 1.0
+ xcvbitmanip 1.0
+ xcvelw 1.0
+ xcvmac 1.0
+ xcvmem 1.0
+ xcvsimd 1.0
+ xsfvcp 1.0
+ xsfvfnrclipxfqf 1.0
+ xsfvfwmaccqqq 1.0
+ xsfvqmaccdod 1.0
+ xsfvqmaccqoq 1.0
+ xsifivecdiscarddlone 1.0
+ xsifivecflushdlone 1.0
+ xtheadba 1.0
+ xtheadbb 1.0
+ xtheadbs 1.0
+ xtheadcmo 1.0
+ xtheadcondmov 1.0
+ xtheadfmemidx 1.0
+ xtheadmac 1.0
+ xtheadmemidx 1.0
+ xtheadmempair 1.0
+ xtheadsync 1.0
+ xtheadvdot 1.0
+ xventanacondops 1.0
Experimental extensions
- zicfilp 0.4 This is a long dummy description
- zicfiss 0.4
- zimop 0.1
- zaamo 0.2
- zabha 1.0
- zalasr 0.1
- zalrsc 0.2
- zfbfmin 1.0
- zcmop 0.2
- ztso 0.1
- zvfbfmin 1.0
- zvfbfwma 1.0
- smmpm 0.8
- smnpm 0.8
- ssnpm 0.8
- sspm 0.8
- ssqosid 1.0
- supm 0.8
+ zicfilp 0.4 This is a long dummy description
+ zicfiss 0.4
+ zimop 0.1
+ zaamo 0.2
+ zabha 1.0
+ zalasr 0.1
+ zalrsc 0.2
+ zfbfmin 1.0
+ zcmop 0.2
+ ztso 0.1
+ zvfbfmin 1.0
+ zvfbfwma 1.0
+ smmpm 0.8
+ smnpm 0.8
+ ssnpm 0.8
+ sspm 0.8
+ ssqosid 1.0
+ supm 0.8
Use -march to specify the target's extension.
For example, clang -march=rv32i_v1p0)";
>From 9ff1fb909c94a450030a6326dbebfd6079ccac42 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 4 Mar 2024 11:47:05 -0800
Subject: [PATCH 2/4] fixup! Add new assembler/disassembler test files
---
llvm/test/MC/RISCV/xsifive-invalid.s | 10 ++++++++++
llvm/test/MC/RISCV/xsifive-valid.s | 26 ++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
create mode 100644 llvm/test/MC/RISCV/xsifive-invalid.s
create mode 100644 llvm/test/MC/RISCV/xsifive-valid.s
diff --git a/llvm/test/MC/RISCV/xsifive-invalid.s b/llvm/test/MC/RISCV/xsifive-invalid.s
new file mode 100644
index 00000000000000..6280c722b1c250
--- /dev/null
+++ b/llvm/test/MC/RISCV/xsifive-invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
+
+cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction){{$}}
+
+cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction){{$}}
+
+cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction){{$}}
+
+cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction){{$}}
diff --git a/llvm/test/MC/RISCV/xsifive-valid.s b/llvm/test/MC/RISCV/xsifive-valid.s
new file mode 100644
index 00000000000000..54fd70ca826c13
--- /dev/null
+++ b/llvm/test/MC/RISCV/xsifive-valid.s
@@ -0,0 +1,26 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone < %s \
+# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsifivecdiscarddlone,+xsifivecflushdlone < %s \
+# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone -M no-aliases -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: cflush.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
+cflush.d.l1 x0
+
+# CHECK-INST: cflush.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
+cflush.d.l1 x7
+
+# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
+cdiscard.d.l1 x0
+
+# CHECK-INST: cdiscard.d.l1 t2
+# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
+cdiscard.d.l1 x7
>From 2a2081d253b06e8e83657383839ffcd58eb17e53 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 4 Mar 2024 11:48:48 -0800
Subject: [PATCH 3/4] fixup! fix typo in test.
---
clang/test/Preprocessor/riscv-target-features.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index f8d4800aabbb44..4511ea5ff69586 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -60,8 +60,8 @@
// CHECK-NOT: __riscv_xsfvfwmaccqqq {{.*$}}
// CHECK-NOT: __riscv_xsfqmaccdod {{.*$}}
// CHECK-NOT: __riscv_xsfvqmaccqoq {{.*$}}
-// CHECK-NOT: __riscv_sifivecdiscarddlone {{.*$}}
-// CHECK-NOT: __riscv_sifivecflushdlone {{.*$}}
+// CHECK-NOT: __riscv_xsifivecdiscarddlone {{.*$}}
+// CHECK-NOT: __riscv_xsifivecflushdlone {{.*$}}
// CHECK-NOT: __riscv_xtheadba {{.*$}}
// CHECK-NOT: __riscv_xtheadbb {{.*$}}
// CHECK-NOT: __riscv_xtheadbs {{.*$}}
>From 7b59f83ce16040f1ad07961a57bb25eb31ecde73 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 5 Mar 2024 21:18:45 -0800
Subject: [PATCH 4/4] fixup! Add sf. prefix.
---
llvm/docs/RISCVUsage.rst | 4 ++--
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++----
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 4 ++--
llvm/test/MC/RISCV/xsifive-invalid.s | 8 ++++----
llvm/test/MC/RISCV/xsifive-valid.s | 16 ++++++++--------
5 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index f1e2e86390c838..5b1b9d853dcee9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -353,10 +353,10 @@ The current vendor extensions supported are:
LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
``XSiFivecdiscarddlone``
- LLVM implements `the SiFive cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+ LLVM implements `the SiFive sf.cdiscard.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
``XSiFivecflushdlone``
- LLVM implements `the SiFive cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
+ LLVM implements `the SiFive sf.cflush.d.l1 instruction specified in <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive.
Experimental C Intrinsics
=========================
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fb47e5f76c5e2e..19580793de7b5b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1056,19 +1056,19 @@ def HasVendorXSfvfnrclipxfqf
def FeatureVendorXSiFivecdiscarddlone
: SubtargetFeature<"xsifivecdiscarddlone", "HasVendorXSiFivecdiscarddlone", "true",
- "'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction)", []>;
+ "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)", []>;
def HasVendorXSiFivecdiscarddlone
: Predicate<"Subtarget->hasVendorXSiFivecdiscarddlone()">,
AssemblerPredicate<(all_of FeatureVendorXSiFivecdiscarddlone),
- "'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction)">;
+ "'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction)">;
def FeatureVendorXSiFivecflushdlone
: SubtargetFeature<"xsifivecflushdlone", "HasVendorXSiFivecflushdlone", "true",
- "'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction)", []>;
+ "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)", []>;
def HasVendorXSiFivecflushdlone
: Predicate<"Subtarget->hasVendorXSiFivecflushdlone()">,
AssemblerPredicate<(all_of FeatureVendorXSiFivecflushdlone),
- "'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction)">;
+ "'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction)">;
// Core-V Extensions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index a7601724300b64..1b850cf2fad6f0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -814,7 +814,7 @@ let Predicates = [HasVendorXSiFivecdiscarddlone] in {
DecoderNamespace = "XSiFivecdiscarddlone" in
def SF_CDISCARD_D_L1
: RVInstR<0b1111110, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
- "cdiscard.d.l1", "$rs1">, Sched<[]> {
+ "sf.cdiscard.d.l1", "$rs1">, Sched<[]> {
let rd = 0;
let rs2 = 0b00010;
}
@@ -825,7 +825,7 @@ let Predicates = [HasVendorXSiFivecflushdlone] in {
DecoderNamespace = "XSiFivecflushdlone" in
def SF_CFLUSH_D_L1
: RVInstR<0b1111110, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1),
- "cflush.d.l1", "$rs1">, Sched<[]> {
+ "sf.cflush.d.l1", "$rs1">, Sched<[]> {
let rd = 0;
let rs2 = 0b00000;
}
diff --git a/llvm/test/MC/RISCV/xsifive-invalid.s b/llvm/test/MC/RISCV/xsifive-invalid.s
index 6280c722b1c250..6d5b430e309707 100644
--- a/llvm/test/MC/RISCV/xsifive-invalid.s
+++ b/llvm/test/MC/RISCV/xsifive-invalid.s
@@ -1,10 +1,10 @@
# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s
-cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction){{$}}
+sf.cflush.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
-cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive cflush.d.l1 Instruction){{$}}
+sf.cflush.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction){{$}}
-cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction){{$}}
+sf.cdiscard.d.l1 x0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
-cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive cdiscard.d.l1 Instruction){{$}}
+sf.cdiscard.d.l1 x7 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction){{$}}
diff --git a/llvm/test/MC/RISCV/xsifive-valid.s b/llvm/test/MC/RISCV/xsifive-valid.s
index 54fd70ca826c13..71d9a7463a8c0f 100644
--- a/llvm/test/MC/RISCV/xsifive-valid.s
+++ b/llvm/test/MC/RISCV/xsifive-valid.s
@@ -9,18 +9,18 @@
# RUN: | llvm-objdump --mattr=+xsifivecdiscarddlone,+xsifivecflushdlone -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# CHECK-INST: cflush.d.l1 zero
+# CHECK-INST: sf.cflush.d.l1 zero
# CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
-cflush.d.l1 x0
+sf.cflush.d.l1 x0
-# CHECK-INST: cflush.d.l1 t2
+# CHECK-INST: sf.cflush.d.l1 t2
# CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
-cflush.d.l1 x7
+sf.cflush.d.l1 x7
-# CHECK-INST: cdiscard.d.l1 zero
+# CHECK-INST: sf.cdiscard.d.l1 zero
# CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
-cdiscard.d.l1 x0
+sf.cdiscard.d.l1 x0
-# CHECK-INST: cdiscard.d.l1 t2
+# CHECK-INST: sf.cdiscard.d.l1 t2
# CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
-cdiscard.d.l1 x7
+sf.cdiscard.d.l1 x7
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