[clang] aeda1a6 - [Clang][LoongArch] Precommit test for fix wrong return value type of __iocsrrd_h. NFC
via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 5 17:26:40 PST 2024
Author: wanglei
Date: 2024-03-06T09:26:14+08:00
New Revision: aeda1a6e800e0dd6c91c0332b4db95094ad5b301
URL: https://github.com/llvm/llvm-project/commit/aeda1a6e800e0dd6c91c0332b4db95094ad5b301
DIFF: https://github.com/llvm/llvm-project/commit/aeda1a6e800e0dd6c91c0332b4db95094ad5b301.diff
LOG: [Clang][LoongArch] Precommit test for fix wrong return value type of __iocsrrd_h. NFC
Added:
Modified:
clang/test/CodeGen/LoongArch/intrinsic-la32.c
clang/test/CodeGen/LoongArch/intrinsic-la64.c
Removed:
################################################################################
diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la32.c b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
index 93d54f511a9cd2..6a8d99880be399 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -169,8 +169,8 @@ unsigned int cpucfg(unsigned int a) {
// LA32-LABEL: @rdtime(
// LA32-NEXT: entry:
-// LA32-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
-// LA32-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// LA32-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc [[META2:![0-9]+]]
+// LA32-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc [[META3:![0-9]+]]
// LA32-NEXT: ret void
//
void rdtime() {
@@ -201,13 +201,28 @@ void loongarch_movgr2fcsr(int a) {
__builtin_loongarch_movgr2fcsr(1, a);
}
-// CHECK-LABEL: @cacop_w(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A:%.*]], i32 1024)
-// CHECK-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A]], i32 1024)
-// CHECK-NEXT: ret void
+// LA32-LABEL: @cacop_w(
+// LA32-NEXT: entry:
+// LA32-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A:%.*]], i32 1024)
+// LA32-NEXT: tail call void @llvm.loongarch.cacop.w(i32 1, i32 [[A]], i32 1024)
+// LA32-NEXT: ret void
//
void cacop_w(unsigned long int a) {
__cacop_w(1, a, 1024);
__builtin_loongarch_cacop_w(1, a, 1024);
}
+
+// LA32-LABEL: @iocsrrd_h_result(
+// LA32-NEXT: entry:
+// LA32-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// LA32-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
+// LA32-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 255
+// LA32-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
+// LA32-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
+// LA32-NEXT: ret i16 [[CONV4]]
+//
+unsigned short iocsrrd_h_result(unsigned int a) {
+ unsigned short b = __iocsrrd_h(a);
+ unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+ return b+c;
+}
diff --git a/clang/test/CodeGen/LoongArch/intrinsic-la64.c b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
index a740882eef5411..48b6a7a3d22704 100644
--- a/clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ b/clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -387,7 +387,7 @@ unsigned int cpucfg(unsigned int a) {
// CHECK-LABEL: @rdtime_d(
// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc [[META2:![0-9]+]]
// CHECK-NEXT: ret void
//
void rdtime_d() {
@@ -396,8 +396,8 @@ void rdtime_d() {
// CHECK-LABEL: @rdtime(
// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
-// CHECK-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT: [[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc [[META3:![0-9]+]]
+// CHECK-NEXT: [[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc [[META4:![0-9]+]]
// CHECK-NEXT: ret void
//
void rdtime() {
@@ -427,3 +427,18 @@ void loongarch_movgr2fcsr(int a) {
__movgr2fcsr(1, a);
__builtin_loongarch_movgr2fcsr(1, a);
}
+
+// CHECK-LABEL: @iocsrrd_h_result(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A:%.*]])
+// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.loongarch.iocsrrd.h(i32 [[A]])
+// CHECK-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 255
+// CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[CONV2]]
+// CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
+// CHECK-NEXT: ret i16 [[CONV4]]
+//
+unsigned short iocsrrd_h_result(unsigned int a) {
+ unsigned short b = __iocsrrd_h(a);
+ unsigned short c = __builtin_loongarch_iocsrrd_h(a);
+ return b+c;
+}
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