[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
Wang Pengcheng via cfe-commits
cfe-commits at lists.llvm.org
Tue Mar 5 01:10:58 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76357
>From a54f47f8055e898b6452183663863f6df01e98e1 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified profile in `-march` with standard
arch string.
---
clang/test/Driver/riscv-profiles.c | 324 +++++++++++++++++++++++
llvm/include/llvm/Support/RISCVISAInfo.h | 2 +
llvm/lib/Support/RISCVISAInfo.cpp | 76 ++++++
llvm/lib/Target/RISCV/RISCV.td | 6 +
llvm/lib/Target/RISCV/RISCVProfiles.td | 189 +++++++++++++
llvm/lib/Target/RISCV/RISCVSubtarget.h | 19 ++
llvm/test/CodeGen/RISCV/attributes.ll | 25 ++
7 files changed, 641 insertions(+)
create mode 100644 clang/test/Driver/riscv-profiles.c
create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td
diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c
new file mode 100644
index 00000000000000..8d1a7faf607838
--- /dev/null
+++ b/clang/test/Driver/riscv-profiles.c
@@ -0,0 +1,324 @@
+// RUN: %clang -### -c %s 2>&1 -march=rvi20u32 | FileCheck -check-prefix=RVI20U32 %s
+// RVI20U32: "-target-feature" "-a"
+// RVI20U32: "-target-feature" "-c"
+// RVI20U32: "-target-feature" "-d"
+// RVI20U32: "-target-feature" "-f"
+// RVI20U32: "-target-feature" "-m"
+// RVI20U32: "-target-feature" "+rvi20u32"
+
+// RUN: %clang -### -c %s 2>&1 -march=rvi20u64 | FileCheck -check-prefix=RVI20U64 %s
+// RVI20U64: "-target-feature" "-a"
+// RVI20U64: "-target-feature" "-c"
+// RVI20U64: "-target-feature" "-d"
+// RVI20U64: "-target-feature" "-f"
+// RVI20U64: "-target-feature" "-m"
+// RVI20U64: "-target-feature" "+rvi20u64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva20u64 | FileCheck -check-prefix=RVA20U64 %s
+// RVA20U64: "-target-feature" "+m"
+// RVA20U64: "-target-feature" "+a"
+// RVA20U64: "-target-feature" "+f"
+// RVA20U64: "-target-feature" "+d"
+// RVA20U64: "-target-feature" "+c"
+// RVA20U64: "-target-feature" "+ziccamoa"
+// RVA20U64: "-target-feature" "+ziccif"
+// RVA20U64: "-target-feature" "+zicclsm"
+// RVA20U64: "-target-feature" "+ziccrse"
+// RVA20U64: "-target-feature" "+zicntr"
+// RVA20U64: "-target-feature" "+zicsr"
+// RVA20U64: "-target-feature" "+za128rs"
+// RVA20U64: "-target-feature" "+rva20u64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva20s64 | FileCheck -check-prefix=RVA20S64 %s
+// RVA20S64: "-target-feature" "+m"
+// RVA20S64: "-target-feature" "+a"
+// RVA20S64: "-target-feature" "+f"
+// RVA20S64: "-target-feature" "+d"
+// RVA20S64: "-target-feature" "+c"
+// RVA20S64: "-target-feature" "+ziccamoa"
+// RVA20S64: "-target-feature" "+ziccif"
+// RVA20S64: "-target-feature" "+zicclsm"
+// RVA20S64: "-target-feature" "+ziccrse"
+// RVA20S64: "-target-feature" "+zicntr"
+// RVA20S64: "-target-feature" "+zicsr"
+// RVA20S64: "-target-feature" "+zifencei"
+// RVA20S64: "-target-feature" "+za128rs"
+// RVA20S64: "-target-feature" "+ssccptr"
+// RVA20S64: "-target-feature" "+sstvala"
+// RVA20S64: "-target-feature" "+sstvecd"
+// RVA20S64: "-target-feature" "+svade"
+// RVA20S64: "-target-feature" "+svbare"
+// RVA20S64: "-target-feature" "+rva20s64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva22u64 | FileCheck -check-prefix=RVA22U64 %s
+// RVA22U64: "-target-feature" "+m"
+// RVA22U64: "-target-feature" "+a"
+// RVA22U64: "-target-feature" "+f"
+// RVA22U64: "-target-feature" "+d"
+// RVA22U64: "-target-feature" "+c"
+// RVA22U64: "-target-feature" "+zic64b"
+// RVA22U64: "-target-feature" "+zicbom"
+// RVA22U64: "-target-feature" "+zicbop"
+// RVA22U64: "-target-feature" "+zicboz"
+// RVA22U64: "-target-feature" "+ziccamoa"
+// RVA22U64: "-target-feature" "+ziccif"
+// RVA22U64: "-target-feature" "+zicclsm"
+// RVA22U64: "-target-feature" "+ziccrse"
+// RVA22U64: "-target-feature" "+zicntr"
+// RVA22U64: "-target-feature" "+zicsr"
+// RVA22U64: "-target-feature" "+zihintpause"
+// RVA22U64: "-target-feature" "+zihpm"
+// RVA22U64: "-target-feature" "+za64rs"
+// RVA22U64: "-target-feature" "+zfhmin"
+// RVA22U64: "-target-feature" "+zba"
+// RVA22U64: "-target-feature" "+zbb"
+// RVA22U64: "-target-feature" "+zbs"
+// RVA22U64: "-target-feature" "+zkt"
+// RVA22U64: "-target-feature" "+rva22u64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva22s64 | FileCheck -check-prefix=RVA22S64 %s
+// RVA22S64: "-target-feature" "+m"
+// RVA22S64: "-target-feature" "+a"
+// RVA22S64: "-target-feature" "+f"
+// RVA22S64: "-target-feature" "+d"
+// RVA22S64: "-target-feature" "+c"
+// RVA22S64: "-target-feature" "+zic64b"
+// RVA22S64: "-target-feature" "+zicbom"
+// RVA22S64: "-target-feature" "+zicbop"
+// RVA22S64: "-target-feature" "+zicboz"
+// RVA22S64: "-target-feature" "+ziccamoa"
+// RVA22S64: "-target-feature" "+ziccif"
+// RVA22S64: "-target-feature" "+zicclsm"
+// RVA22S64: "-target-feature" "+ziccrse"
+// RVA22S64: "-target-feature" "+zicntr"
+// RVA22S64: "-target-feature" "+zicsr"
+// RVA22S64: "-target-feature" "+zifencei"
+// RVA22S64: "-target-feature" "+zihintpause"
+// RVA22S64: "-target-feature" "+zihpm"
+// RVA22S64: "-target-feature" "+za64rs"
+// RVA22S64: "-target-feature" "+zfhmin"
+// RVA22S64: "-target-feature" "+zba"
+// RVA22S64: "-target-feature" "+zbb"
+// RVA22S64: "-target-feature" "+zbs"
+// RVA22S64: "-target-feature" "+zkt"
+// RVA22S64: "-target-feature" "+ssccptr"
+// RVA22S64: "-target-feature" "+sscounterenw"
+// RVA22S64: "-target-feature" "+sstvala"
+// RVA22S64: "-target-feature" "+sstvecd"
+// RVA22S64: "-target-feature" "+svade"
+// RVA22S64: "-target-feature" "+svbare"
+// RVA22S64: "-target-feature" "+svinval"
+// RVA22S64: "-target-feature" "+svpbmt"
+// RVA22S64: "-target-feature" "+rva22s64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions | FileCheck -check-prefix=RVA23U64 %s
+// RVA23U64: "-target-feature" "+m"
+// RVA23U64: "-target-feature" "+a"
+// RVA23U64: "-target-feature" "+f"
+// RVA23U64: "-target-feature" "+d"
+// RVA23U64: "-target-feature" "+c"
+// RVA23U64: "-target-feature" "+v"
+// RVA23U64: "-target-feature" "+zic64b"
+// RVA23U64: "-target-feature" "+zicbom"
+// RVA23U64: "-target-feature" "+zicbop"
+// RVA23U64: "-target-feature" "+zicboz"
+// RVA23U64: "-target-feature" "+ziccamoa"
+// RVA23U64: "-target-feature" "+ziccif"
+// RVA23U64: "-target-feature" "+zicclsm"
+// RVA23U64: "-target-feature" "+ziccrse"
+// RVA23U64: "-target-feature" "+zicntr"
+// RVA23U64: "-target-feature" "+zicond"
+// RVA23U64: "-target-feature" "+zicsr"
+// RVA23U64: "-target-feature" "+zihintntl"
+// RVA23U64: "-target-feature" "+zihintpause"
+// RVA23U64: "-target-feature" "+zihpm"
+// RVA23U64: "-target-feature" "+experimental-zimop"
+// RVA23U64: "-target-feature" "+za64rs"
+// RVA23U64: "-target-feature" "+zawrs"
+// RVA23U64: "-target-feature" "+zfa"
+// RVA23U64: "-target-feature" "+zfhmin"
+// RVA23U64: "-target-feature" "+zcb"
+// RVA23U64: "-target-feature" "+experimental-zcmop"
+// RVA23U64: "-target-feature" "+zba"
+// RVA23U64: "-target-feature" "+zbb"
+// RVA23U64: "-target-feature" "+zbs"
+// RVA23U64: "-target-feature" "+zkt"
+// RVA23U64: "-target-feature" "+zvbb"
+// RVA23U64: "-target-feature" "+zvfhmin"
+// RVA23U64: "-target-feature" "+zvkt"
+// RVA23U64: "-target-feature" "+rva23u64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva23s64 -menable-experimental-extensions | FileCheck -check-prefix=RVA23S64 %s
+// RVA23S64: "-target-feature" "+m"
+// RVA23S64: "-target-feature" "+a"
+// RVA23S64: "-target-feature" "+f"
+// RVA23S64: "-target-feature" "+d"
+// RVA23S64: "-target-feature" "+c"
+// RVA23S64: "-target-feature" "+v"
+// RVA23S64: "-target-feature" "+h"
+// RVA23S64: "-target-feature" "+zic64b"
+// RVA23S64: "-target-feature" "+zicbom"
+// RVA23S64: "-target-feature" "+zicbop"
+// RVA23S64: "-target-feature" "+zicboz"
+// RVA23S64: "-target-feature" "+ziccamoa"
+// RVA23S64: "-target-feature" "+ziccif"
+// RVA23S64: "-target-feature" "+zicclsm"
+// RVA23S64: "-target-feature" "+ziccrse"
+// RVA23S64: "-target-feature" "+zicntr"
+// RVA23S64: "-target-feature" "+zicond"
+// RVA23S64: "-target-feature" "+zicsr"
+// RVA23S64: "-target-feature" "+zifencei"
+// RVA23S64: "-target-feature" "+zihintntl"
+// RVA23S64: "-target-feature" "+zihintpause"
+// RVA23S64: "-target-feature" "+zihpm"
+// RVA23S64: "-target-feature" "+experimental-zimop"
+// RVA23S64: "-target-feature" "+za64rs"
+// RVA23S64: "-target-feature" "+zawrs"
+// RVA23S64: "-target-feature" "+zfa"
+// RVA23S64: "-target-feature" "+zfhmin"
+// RVA23S64: "-target-feature" "+zcb"
+// RVA23S64: "-target-feature" "+experimental-zcmop"
+// RVA23S64: "-target-feature" "+zba"
+// RVA23S64: "-target-feature" "+zbb"
+// RVA23S64: "-target-feature" "+zbs"
+// RVA23S64: "-target-feature" "+zkt"
+// RVA23S64: "-target-feature" "+zvbb"
+// RVA23S64: "-target-feature" "+zvfhmin"
+// RVA23S64: "-target-feature" "+zvkt"
+// RVA23S64: "-target-feature" "+shcounterenw"
+// RVA23S64: "-target-feature" "+shgatpa"
+// RVA23S64: "-target-feature" "+shtvala"
+// RVA23S64: "-target-feature" "+shvsatpa"
+// RVA23S64: "-target-feature" "+shvstvala"
+// RVA23S64: "-target-feature" "+shvstvecd"
+// RVA23S64: "-target-feature" "+ssccptr"
+// RVA23S64: "-target-feature" "+sscofpmf"
+// RVA23S64: "-target-feature" "+sscounterenw"
+// RVA23S64: "-target-feature" "+experimental-ssnpm"
+// RVA23S64: "-target-feature" "+ssstateen"
+// RVA23S64: "-target-feature" "+sstc"
+// RVA23S64: "-target-feature" "+sstvala"
+// RVA23S64: "-target-feature" "+sstvecd"
+// RVA23S64: "-target-feature" "+ssu64xl"
+// RVA23S64: "-target-feature" "+svade"
+// RVA23S64: "-target-feature" "+svbare"
+// RVA23S64: "-target-feature" "+svinval"
+// RVA23S64: "-target-feature" "+svnapot"
+// RVA23S64: "-target-feature" "+svpbmt"
+// RVA23S64: "-target-feature" "+rva23s64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rvb23u64 -menable-experimental-extensions | FileCheck -check-prefix=RVB23U64 %s
+// RVB23U64: "-target-feature" "+m"
+// RVB23U64: "-target-feature" "+a"
+// RVB23U64: "-target-feature" "+f"
+// RVB23U64: "-target-feature" "+d"
+// RVB23U64: "-target-feature" "+c"
+// RVB23U64: "-target-feature" "+zic64b"
+// RVB23U64: "-target-feature" "+zicbom"
+// RVB23U64: "-target-feature" "+zicbop"
+// RVB23U64: "-target-feature" "+zicboz"
+// RVB23U64: "-target-feature" "+ziccamoa"
+// RVB23U64: "-target-feature" "+ziccif"
+// RVB23U64: "-target-feature" "+zicclsm"
+// RVB23U64: "-target-feature" "+ziccrse"
+// RVB23U64: "-target-feature" "+zicntr"
+// RVB23U64: "-target-feature" "+zicond"
+// RVB23U64: "-target-feature" "+zicsr"
+// RVB23U64: "-target-feature" "+zihintntl"
+// RVB23U64: "-target-feature" "+zihintpause"
+// RVB23U64: "-target-feature" "+zihpm"
+// RVB23U64: "-target-feature" "+experimental-zimop"
+// RVB23U64: "-target-feature" "+za64rs"
+// RVB23U64: "-target-feature" "+zawrs"
+// RVB23U64: "-target-feature" "+zfa"
+// RVB23U64: "-target-feature" "+zcb"
+// RVB23U64: "-target-feature" "+experimental-zcmop"
+// RVB23U64: "-target-feature" "+zba"
+// RVB23U64: "-target-feature" "+zbb"
+// RVB23U64: "-target-feature" "+zbs"
+// RVB23U64: "-target-feature" "+zkt"
+// RVB23U64: "-target-feature" "+rvb23u64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rvb23s64 -menable-experimental-extensions | FileCheck -check-prefix=RVB23S64 %s
+// RVB23S64: "-target-feature" "+m"
+// RVB23S64: "-target-feature" "+a"
+// RVB23S64: "-target-feature" "+f"
+// RVB23S64: "-target-feature" "+d"
+// RVB23S64: "-target-feature" "+c"
+// RVB23S64: "-target-feature" "+zic64b"
+// RVB23S64: "-target-feature" "+zicbom"
+// RVB23S64: "-target-feature" "+zicbop"
+// RVB23S64: "-target-feature" "+zicboz"
+// RVB23S64: "-target-feature" "+ziccamoa"
+// RVB23S64: "-target-feature" "+ziccif"
+// RVB23S64: "-target-feature" "+zicclsm"
+// RVB23S64: "-target-feature" "+ziccrse"
+// RVB23S64: "-target-feature" "+zicntr"
+// RVB23S64: "-target-feature" "+zicond"
+// RVB23S64: "-target-feature" "+zicsr"
+// RVB23S64: "-target-feature" "+zifencei"
+// RVB23S64: "-target-feature" "+zihintntl"
+// RVB23S64: "-target-feature" "+zihintpause"
+// RVB23S64: "-target-feature" "+zihpm"
+// RVB23S64: "-target-feature" "+experimental-zimop"
+// RVB23S64: "-target-feature" "+za64rs"
+// RVB23S64: "-target-feature" "+zawrs"
+// RVB23S64: "-target-feature" "+zfa"
+// RVB23S64: "-target-feature" "+zcb"
+// RVB23S64: "-target-feature" "+experimental-zcmop"
+// RVB23S64: "-target-feature" "+zba"
+// RVB23S64: "-target-feature" "+zbb"
+// RVB23S64: "-target-feature" "+zbs"
+// RVB23S64: "-target-feature" "+zkt"
+// RVB23S64: "-target-feature" "+ssccptr"
+// RVB23S64: "-target-feature" "+sscofpmf"
+// RVB23S64: "-target-feature" "+sscounterenw"
+// RVB23S64: "-target-feature" "+sstc"
+// RVB23S64: "-target-feature" "+sstvala"
+// RVB23S64: "-target-feature" "+sstvecd"
+// RVB23S64: "-target-feature" "+ssu64xl"
+// RVB23S64: "-target-feature" "+svade"
+// RVB23S64: "-target-feature" "+svbare"
+// RVB23S64: "-target-feature" "+svinval"
+// RVB23S64: "-target-feature" "+svnapot"
+// RVB23S64: "-target-feature" "+svpbmt"
+// RVB23S64: "-target-feature" "+rvb23s64"
+
+// RUN: %clang -### -c %s 2>&1 -march=rvm23u32 -menable-experimental-extensions | FileCheck -check-prefix=RVM23U32 %s
+// RVM23U32: "-target-feature" "+m"
+// RVM23U32: "-target-feature" "+zicbop"
+// RVM23U32: "-target-feature" "+zicond"
+// RVM23U32: "-target-feature" "+zicsr"
+// RVM23U32: "-target-feature" "+zihintntl"
+// RVM23U32: "-target-feature" "+zihintpause"
+// RVM23U32: "-target-feature" "+experimental-zimop"
+// RVM23U32: "-target-feature" "+zce"
+// RVM23U32: "-target-feature" "+experimental-zcmop"
+// RVM23U32: "-target-feature" "+zba"
+// RVM23U32: "-target-feature" "+zbb"
+// RVM23U32: "-target-feature" "+zbs"
+// RVM23U32: "-target-feature" "+rvm23u32"
+
+// RUN: %clang -### -c %s 2>&1 -march=rva22u64_zfa | FileCheck -check-prefix=PROFILE-WITH-ADDITIONAL %s
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+m"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+a"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+f"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+d"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+c"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbom"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicbop"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zicboz"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zihintpause"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zfa"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zfhmin"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zba"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zbb"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zbs"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+zkt"
+// PROFILE-WITH-ADDITIONAL: "-target-feature" "+rva22u64"
+
+// RUN: not %clang -### -c %s 2>&1 -march=rva19u64_zfa | FileCheck -check-prefix=INVALID-PROFILE %s
+// INVALID-PROFILE: error: invalid arch name 'rva19u64_zfa', unsupported profile
+
+// RUN: not %clang -### -c %s 2>&1 -march=rva22u64zfa | FileCheck -check-prefix=INVALID-ADDITIONAL %s
+// INVALID-ADDITIONAL: error: invalid arch name 'rva22u64zfa', additional extensions must be after separator '_'
diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h
index 46df93d7522602..9cb545dbacff2f 100644
--- a/llvm/include/llvm/Support/RISCVISAInfo.h
+++ b/llvm/include/llvm/Support/RISCVISAInfo.h
@@ -80,6 +80,7 @@ class RISCVISAInfo {
unsigned getMaxVLen() const { return 65536; }
unsigned getMaxELen() const { return MaxELen; }
unsigned getMaxELenFp() const { return MaxELenFp; }
+ StringRef getProfile() const { return Profile; }
bool hasExtension(StringRef Ext) const;
std::string toString() const;
@@ -102,6 +103,7 @@ class RISCVISAInfo {
unsigned FLen;
unsigned MinVLen;
unsigned MaxELen, MaxELenFp;
+ std::string Profile;
OrderedExtensionMap Exts;
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 54b4dcb22de8e0..d119e521445a73 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
+ const char *Name;
+ const char *MArch;
+};
+
} // end anonymous namespace
static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh";
@@ -241,6 +246,42 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
};
// clang-format on
+static const RISCVProfile SupportedProfiles[] = {
+ {"rvi20u32", "rv32i"},
+ {"rvi20u64", "rv64i"},
+ {"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"},
+ {"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_"
+ "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"},
+ {"rva22u64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
+ "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"},
+ {"rva22s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
+ "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_"
+ "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"},
+ {"rva23u64",
+ "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
+ "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_"
+ "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"},
+ {"rva23s64",
+ "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_"
+ "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_"
+ "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_"
+ "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_"
+ "svbare_svinval_svnapot_svpbmt"},
+ {"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_"
+ "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_"
+ "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"},
+ {"rvb23s64",
+ "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_"
+ "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_"
+ "zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_"
+ "sstvala_sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"},
+ {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop0p1_"
+ "zca_zcb_zce_zcmop0p2_zcmp_zcmt_zba_zbb_zbs"},
+};
+
static void verifyTables() {
#ifndef NDEBUG
static std::atomic<bool> TableChecked(false);
@@ -528,6 +569,11 @@ std::vector<std::string> RISCVISAInfo::toFeatures(bool AddAllExtensions,
Features.push_back((llvm::Twine("-experimental-") + Ext.Name).str());
}
}
+
+ // Add profile feature.
+ if (!Profile.empty())
+ Features.push_back((Twine("+") + Profile).str());
+
return Features;
}
@@ -840,6 +886,33 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ std::string ProfileName;
+ if (IsProfile) {
+ const auto *FoundProfile =
+ llvm::find_if(SupportedProfiles, [&](const RISCVProfile &Profile) {
+ return Arch.starts_with(Profile.Name);
+ });
+
+ if (FoundProfile == adl_end(SupportedProfiles))
+ return createStringError(errc::invalid_argument, "unsupported profile");
+
+ ProfileName = FoundProfile->Name;
+ NewArch = FoundProfile->MArch;
+
+ StringRef ArchWithoutProfile = Arch.substr(ProfileName.size());
+ if (!ArchWithoutProfile.empty()) {
+ if (!ArchWithoutProfile.starts_with("_"))
+ return createStringError(
+ errc::invalid_argument,
+ "additional extensions must be after separator '_'");
+ NewArch = NewArch + ArchWithoutProfile.str();
+ }
+ Arch = NewArch;
+ }
+
bool HasRV64 = Arch.starts_with("rv64");
// ISA string must begin with rv32 or rv64.
if (!(Arch.starts_with("rv32") || HasRV64) || (Arch.size() < 5)) {
@@ -850,6 +923,9 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension,
unsigned XLen = HasRV64 ? 64 : 32;
std::unique_ptr<RISCVISAInfo> ISAInfo(new RISCVISAInfo(XLen));
+ if (!ProfileName.empty())
+ ISAInfo->Profile = ProfileName;
+
MapVector<std::string, RISCVISAInfo::ExtensionVersion,
std::map<std::string, unsigned>>
SeenExtMap;
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 575bd4c9d3561d..a8f28fadea5f3c 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -52,6 +52,12 @@ include "RISCVSchedXiangShanNanHu.td"
include "RISCVProcessors.td"
+//===----------------------------------------------------------------------===//
+// RISC-V profiles supported.
+//===----------------------------------------------------------------------===//
+
+include "RISCVProfiles.td"
+
//===----------------------------------------------------------------------===//
// Define the RISC-V target.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td
new file mode 100644
index 00000000000000..b9fd59a3a4eeaf
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVProfiles.td
@@ -0,0 +1,189 @@
+//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+class RISCVProfile<string name, list<SubtargetFeature> features>
+ : SubtargetFeature<name, "RISCVProfile", NAME,
+ "RISC-V " # name # " profile",
+ features>;
+
+def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit]>;
+
+def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit]>;
+
+def RVA20U64 : RISCVProfile<"rva20u64", [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZa128rs,
+ FeatureStdExtZicclsm]>;
+
+def RVA20S64 : RISCVProfile<"rva20s64", [RVA20U64,
+ FeatureStdExtZifencei,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala]>;
+
+def RVA22U64 : RISCVProfile<"rva22u64", [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZihpm,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtZfhmin,
+ FeatureStdExtZkt]>;
+
+def RVA22S64 : RISCVProfile<"rva22s64", [RVA22U64,
+ FeatureStdExtZifencei,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala,
+ FeatureStdExtSscounterenw,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval]>;
+
+def RVA23U64 : RISCVProfile<"rva23u64", [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtZfhmin,
+ FeatureStdExtZkt,
+ FeatureStdExtV,
+ FeatureStdExtZvfhmin,
+ FeatureStdExtZvbb,
+ FeatureStdExtZvkt,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZicond,
+ FeatureStdExtZimop,
+ FeatureStdExtZcmop,
+ FeatureStdExtZcb,
+ FeatureStdExtZfa,
+ FeatureStdExtZawrs]>;
+
+def RVA23S64 : RISCVProfile<"rva23s64", [RVA23U64,
+ FeatureStdExtZifencei,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala,
+ FeatureStdExtSscounterenw,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval,
+ FeatureStdExtSvnapot,
+ FeatureStdExtSstc,
+ FeatureStdExtSscofpmf,
+ FeatureStdExtSsnpm,
+ FeatureStdExtSsu64xl,
+ FeatureStdExtH,
+ FeatureStdExtSsstateen,
+ FeatureStdExtShcounterenw,
+ FeatureStdExtShvstvala,
+ FeatureStdExtShtvala,
+ FeatureStdExtShvstvecd,
+ FeatureStdExtShvsatpa,
+ FeatureStdExtShgatpa]>;
+
+def RVB23U64 : RISCVProfile<"rvb23u64", [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicntr,
+ FeatureStdExtZihpm,
+ FeatureStdExtZiccif,
+ FeatureStdExtZiccrse,
+ FeatureStdExtZiccamoa,
+ FeatureStdExtZicclsm,
+ FeatureStdExtZa64rs,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZic64b,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicboz,
+ FeatureStdExtZkt,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZicond,
+ FeatureStdExtZimop,
+ FeatureStdExtZcmop,
+ FeatureStdExtZcb,
+ FeatureStdExtZfa,
+ FeatureStdExtZawrs]>;
+
+def RVB23S64 : RISCVProfile<"rvb23s64", [RVB23U64,
+ FeatureStdExtZifencei,
+ FeatureStdExtSvnapot,
+ FeatureStdExtSvbare,
+ FeatureStdExtSvade,
+ FeatureStdExtSsccptr,
+ FeatureStdExtSstvecd,
+ FeatureStdExtSstvala,
+ FeatureStdExtSscounterenw,
+ FeatureStdExtSvpbmt,
+ FeatureStdExtSvinval,
+ FeatureStdExtSstc,
+ FeatureStdExtSscofpmf,
+ FeatureStdExtSsu64xl]>;
+
+def RVM23U32 : RISCVProfile<"rvm23u32", [Feature32Bit,
+ FeatureStdExtM,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZicond,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZce,
+ FeatureStdExtZicbop,
+ FeatureStdExtZimop,
+ FeatureStdExtZcmop]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index ba108912d93400..643f6d45510ec9 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -56,6 +56,21 @@ struct RISCVTuneInfo {
#include "RISCVGenSearchableTables.inc"
} // namespace RISCVTuneInfoTable
+enum RISCVProfileEnum : uint8_t {
+ Unspecified,
+ RVA20S64,
+ RVA20U64,
+ RVA22S64,
+ RVA22U64,
+ RVA23S64,
+ RVA23U64,
+ RVB23S64,
+ RVB23U64,
+ RVI20U32,
+ RVI20U64,
+ RVM23U32,
+};
+
class RISCVSubtarget : public RISCVGenSubtargetInfo {
public:
// clang-format off
@@ -70,6 +85,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
RISCVProcFamilyEnum RISCVProcFamily = Others;
+ RISCVProfileEnum RISCVProfile = Unspecified;
+
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
bool ATTRIBUTE = DEFAULT;
#include "RISCVGenSubtargetInfo.inc"
@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
/// initializeProperties().
RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
+ RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; }
+
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
bool GETTER() const { return ATTRIBUTE; }
#include "RISCVGenSubtargetInfo.inc"
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index cc332df271043f..eb394b0a3c4274 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -254,6 +254,19 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
+; Tests for profile features.
+; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rvi20u64 %s -o - | FileCheck --check-prefix=RVI20U64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva20u64 %s -o - | FileCheck --check-prefix=RVA20U64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s
+; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s
+
; CHECK: .attribute 4, 16
; RV32M: .attribute 5, "rv32i2p1_m2p0"
@@ -508,6 +521,18 @@
; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
+; RVI20U32: .attribute 5, "rv32i2p1"
+; RVI20U64: .attribute 5, "rv64i2p1"
+; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_za128rs1p0"
+; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
+; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
+; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
+; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop0p1_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop0p2_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop0p1_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop0p2_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
+; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop0p1_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop0p2_zba1p0_zbb1p0_zbs1p0_zkt1p0"
+; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop0p1_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop0p2_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
+; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop0p1_zca1p0_zcb1p0_zce1p0_zcmop0p2_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
+
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
ret i32 %1
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