[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)

[Brandon Wu via cfe-commits]

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@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include <riscv_vector.h>
+
+void test_builtin() {
+  __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_rvv_vsetvli' needs target feature zve32x}}
+}
+
+__attribute__((target("+zve32x")))
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4vtomat wrote:

Updated thanks!

https://github.com/llvm/llvm-project/pull/83674