[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)
Wang Pengcheng via cfe-commits
cfe-commits at lists.llvm.org
Sun Feb 18 03:27:57 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/79975
>From 5b9c6d91a47da63d278983ab1e64b25739200ffa Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Tue, 30 Jan 2024 18:31:28 +0800
Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
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Created using spr 1.3.4
---
clang/include/clang/Basic/riscv_vector.td | 100 ++-
.../non-policy/non-overloaded/vsetvl.c | 619 ++++++++++++++++--
.../non-policy/non-overloaded/vsetvlmax.c | 312 +++++++--
.../policy/non-overloaded/vsetvl.c | 619 ++++++++++++++++--
.../policy/non-overloaded/vsetvlmax.c | 312 +++++++--
.../rvv-intrinsics-handcrafted/rvv-error.c | 10 +-
6 files changed, 1791 insertions(+), 181 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index a00ca353588ed5..84f61e3be4cfa4 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -669,10 +669,104 @@ let HasBuiltinAlias = false,
HasVL = false,
HasMasked = false,
MaskedPolicyScheme = NonePolicy,
- Log2LMUL = [0],
- ManualCodegen = [{IntrinsicTypes = {ResultType};}] in // Set XLEN type
-{
+ Log2LMUL = [0] in {
+
+ let ManualCodegen = [{
+ {
+ // Set XLEN type
+ IntrinsicTypes = {ResultType};
+ llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+ llvm::Value *VSetVL = Builder.CreateCall(F, Ops, "vl");
+
+ const TargetInfo &TI = getContext().getTargetInfo();
+ auto VScale = TI.getVScaleRange(getContext().getLangOpts());
+
+ if (VScale && VScale->first && VScale->first == VScale->second) {
+ // Assumptions:
+ // Let:
+ // fixed_vl = __riscv_v_fixed_vlen / 8;
+ // We have:
+ // (avl > fixed_vl || vl == avl)
+ // and
+ // (avl < fixed_vl * 2 || vl == fixed_vl)
+ Value *FixedVL = llvm::ConstantInt::get(ResultType, VScale->first * 8);
+ Value *FixedVLx2 =
+ llvm::ConstantInt::get(ResultType, VScale->first * 8 * 2);
+ Value *Cond0 = Builder.CreateICmpULE(
+ Ops[0], ConstantInt::get(ResultType, VScale->first * 8));
+
+ BasicBlock *AssumptionBlock =
+ createBasicBlock("assumption", this->CurFn);
+ BasicBlock *AssumptionEndBlock =
+ createBasicBlock("assumption_end", this->CurFn);
+ Builder.CreateCondBr(Cond0, AssumptionBlock, AssumptionEndBlock);
+
+ Builder.SetInsertPoint(AssumptionBlock);
+ Builder.CreateAssumption(Builder.CreateICmpEQ(VSetVL, Ops[0]));
+ Builder.CreateBr(AssumptionEndBlock);
+
+ Builder.SetInsertPoint(AssumptionEndBlock);
+ Value *Assumption0 = Builder.CreateICmpULT(Ops[0], FixedVLx2);
+ Value *Assumption1 = Builder.CreateICmpEQ(VSetVL, FixedVL);
+ Builder.CreateAssumption(Builder.CreateSelect(
+ Assumption0, ConstantInt::getTrue(getLLVMContext()), Assumption1));
+ } else {
+ // Assumptions:
+ // Let:
+ // min_vl = __riscv_v_min_vlen / 8
+ // We have:
+ // (avl > min_vl || vl == avl)
+ Value *Cond0 = Builder.CreateICmpULE(
+ Ops[0], ConstantInt::get(ResultType, VScale->first * 8));
+
+ BasicBlock *AssumptionBlock = createBasicBlock("assumption", this->CurFn);
+ BasicBlock *AssumptionEndBlock = createBasicBlock("assumption_end", this->CurFn);
+ Builder.CreateCondBr(Cond0, AssumptionBlock, AssumptionEndBlock);
+
+ Builder.SetInsertPoint(AssumptionBlock);
+ Value *Assumption = Builder.CreateICmpEQ(VSetVL, Ops[0]);
+ Builder.CreateAssumption(Assumption);
+ Builder.CreateBr(AssumptionEndBlock);
+
+ Builder.SetInsertPoint(AssumptionEndBlock);
+ }
+ return VSetVL;
+ }
+ }] in
def vsetvli : RVVBuiltin<"", "zzKzKz", "i">;
+
+ let ManualCodegen = [{
+ {
+ // Set XLEN type
+ IntrinsicTypes = {ResultType};
+ llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+ llvm::Value *VSetVL = Builder.CreateCall(F, Ops, "vl");
+
+ const TargetInfo &TI = getContext().getTargetInfo();
+ auto VScale = TI.getVScaleRange(getContext().getLangOpts());
+
+ Value *Assumption;
+ if (VScale && VScale->first && VScale->first == VScale->second)
+ // Assumptions:
+ // Let:
+ // fixed_vl = __riscv_v_fixed_vlen / 8;
+ // We have:
+ // vlmax == fixed_vl
+ Assumption = Builder.CreateICmpEQ(
+ VSetVL, llvm::ConstantInt::get(ResultType, VScale->first * 8));
+ else
+ // Assumptions:
+ // Let:
+ // min_vl = __riscv_v_min_vlen / 8
+ // We have:
+ // vlmax >= min_vl
+ Assumption = Builder.CreateICmpUGE(
+ VSetVL, ConstantInt::get(ResultType, VScale->first * 8));
+
+ Builder.CreateAssumption(Assumption);
+ return VSetVL;
+ }
+ }] in
def vsetvlimax : RVVBuiltin<"", "zKzKz", "i">;
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
index 26d2e0a4868d5a..42f465e33f6fda 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
@@ -3,14 +3,41 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
+// RUN: -mvscale-min=2 -mvscale-max=2 -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64-FIXED %s
#include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8mf8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8mf8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8mf8(size_t avl) {
return __riscv_vsetvl_e8mf8(avl);
@@ -19,8 +46,32 @@ size_t test_vsetvl_e8mf8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8mf4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8mf4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8mf4(size_t avl) {
return __riscv_vsetvl_e8mf4(avl);
@@ -29,8 +80,32 @@ size_t test_vsetvl_e8mf4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8mf2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8mf2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8mf2(size_t avl) {
return __riscv_vsetvl_e8mf2(avl);
@@ -39,8 +114,32 @@ size_t test_vsetvl_e8mf2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m1(size_t avl) {
return __riscv_vsetvl_e8m1(avl);
@@ -49,8 +148,32 @@ size_t test_vsetvl_e8m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m2(size_t avl) {
return __riscv_vsetvl_e8m2(avl);
@@ -59,8 +182,32 @@ size_t test_vsetvl_e8m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m4(size_t avl) {
return __riscv_vsetvl_e8m4(avl);
@@ -69,8 +216,32 @@ size_t test_vsetvl_e8m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m8(size_t avl) {
return __riscv_vsetvl_e8m8(avl);
@@ -79,8 +250,32 @@ size_t test_vsetvl_e8m8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16mf4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16mf4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16mf4(size_t avl) {
return __riscv_vsetvl_e16mf4(avl);
@@ -89,8 +284,32 @@ size_t test_vsetvl_e16mf4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16mf2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16mf2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16mf2(size_t avl) {
return __riscv_vsetvl_e16mf2(avl);
@@ -99,8 +318,32 @@ size_t test_vsetvl_e16mf2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m1(size_t avl) {
return __riscv_vsetvl_e16m1(avl);
@@ -109,8 +352,32 @@ size_t test_vsetvl_e16m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m2(size_t avl) {
return __riscv_vsetvl_e16m2(avl);
@@ -119,8 +386,32 @@ size_t test_vsetvl_e16m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m4(size_t avl) {
return __riscv_vsetvl_e16m4(avl);
@@ -129,8 +420,32 @@ size_t test_vsetvl_e16m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m8(size_t avl) {
return __riscv_vsetvl_e16m8(avl);
@@ -139,8 +454,32 @@ size_t test_vsetvl_e16m8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32mf2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32mf2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32mf2(size_t avl) {
return __riscv_vsetvl_e32mf2(avl);
@@ -149,8 +488,32 @@ size_t test_vsetvl_e32mf2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m1(size_t avl) {
return __riscv_vsetvl_e32m1(avl);
@@ -159,8 +522,32 @@ size_t test_vsetvl_e32m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m2(size_t avl) {
return __riscv_vsetvl_e32m2(avl);
@@ -169,8 +556,32 @@ size_t test_vsetvl_e32m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m4(size_t avl) {
return __riscv_vsetvl_e32m4(avl);
@@ -179,8 +590,32 @@ size_t test_vsetvl_e32m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m8(size_t avl) {
return __riscv_vsetvl_e32m8(avl);
@@ -189,8 +624,32 @@ size_t test_vsetvl_e32m8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m1(size_t avl) {
return __riscv_vsetvl_e64m1(avl);
@@ -199,8 +658,32 @@ size_t test_vsetvl_e64m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m2(size_t avl) {
return __riscv_vsetvl_e64m2(avl);
@@ -209,8 +692,32 @@ size_t test_vsetvl_e64m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m4(size_t avl) {
return __riscv_vsetvl_e64m4(avl);
@@ -219,8 +726,32 @@ size_t test_vsetvl_e64m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m8(size_t avl) {
return __riscv_vsetvl_e64m8(avl);
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
index 792e43c22f519b..fd6d091df69102 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
@@ -3,14 +3,28 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
+// RUN: -mvscale-min=2 -mvscale-max=2 -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64-FIXED %s
+
#include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8mf8
// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8mf8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8mf8() {
return __riscv_vsetvlmax_e8mf8();
@@ -19,8 +33,18 @@ size_t test_vsetvlmax_e8mf8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8mf4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8mf4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8mf4() {
return __riscv_vsetvlmax_e8mf4();
@@ -29,8 +53,18 @@ size_t test_vsetvlmax_e8mf4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8mf2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8mf2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8mf2() {
return __riscv_vsetvlmax_e8mf2();
@@ -39,8 +73,18 @@ size_t test_vsetvlmax_e8mf2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m1() {
return __riscv_vsetvlmax_e8m1();
@@ -49,8 +93,18 @@ size_t test_vsetvlmax_e8m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m2() {
return __riscv_vsetvlmax_e8m2();
@@ -59,8 +113,18 @@ size_t test_vsetvlmax_e8m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m4() {
return __riscv_vsetvlmax_e8m4();
@@ -69,8 +133,18 @@ size_t test_vsetvlmax_e8m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m8() {
return __riscv_vsetvlmax_e8m8();
@@ -79,8 +153,18 @@ size_t test_vsetvlmax_e8m8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16mf4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16mf4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16mf4() {
return __riscv_vsetvlmax_e16mf4();
@@ -89,8 +173,18 @@ size_t test_vsetvlmax_e16mf4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16mf2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16mf2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16mf2() {
return __riscv_vsetvlmax_e16mf2();
@@ -99,8 +193,18 @@ size_t test_vsetvlmax_e16mf2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m1() {
return __riscv_vsetvlmax_e16m1();
@@ -109,8 +213,18 @@ size_t test_vsetvlmax_e16m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m2() {
return __riscv_vsetvlmax_e16m2();
@@ -119,8 +233,18 @@ size_t test_vsetvlmax_e16m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m4() {
return __riscv_vsetvlmax_e16m4();
@@ -129,8 +253,18 @@ size_t test_vsetvlmax_e16m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m8() {
return __riscv_vsetvlmax_e16m8();
@@ -139,8 +273,18 @@ size_t test_vsetvlmax_e16m8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32mf2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32mf2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32mf2() {
return __riscv_vsetvlmax_e32mf2();
@@ -149,8 +293,18 @@ size_t test_vsetvlmax_e32mf2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m1() {
return __riscv_vsetvlmax_e32m1();
@@ -159,8 +313,18 @@ size_t test_vsetvlmax_e32m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m2() {
return __riscv_vsetvlmax_e32m2();
@@ -169,8 +333,18 @@ size_t test_vsetvlmax_e32m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m4() {
return __riscv_vsetvlmax_e32m4();
@@ -179,8 +353,18 @@ size_t test_vsetvlmax_e32m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m8() {
return __riscv_vsetvlmax_e32m8();
@@ -189,8 +373,18 @@ size_t test_vsetvlmax_e32m8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m1() {
return __riscv_vsetvlmax_e64m1();
@@ -199,8 +393,18 @@ size_t test_vsetvlmax_e64m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m2() {
return __riscv_vsetvlmax_e64m2();
@@ -209,8 +413,18 @@ size_t test_vsetvlmax_e64m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m4() {
return __riscv_vsetvlmax_e64m4();
@@ -219,8 +433,18 @@ size_t test_vsetvlmax_e64m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m8() {
return __riscv_vsetvlmax_e64m8();
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
index 26d2e0a4868d5a..42f465e33f6fda 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
@@ -3,14 +3,41 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
+// RUN: -mvscale-min=2 -mvscale-max=2 -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64-FIXED %s
#include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8mf8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8mf8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8mf8(size_t avl) {
return __riscv_vsetvl_e8mf8(avl);
@@ -19,8 +46,32 @@ size_t test_vsetvl_e8mf8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8mf4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8mf4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8mf4(size_t avl) {
return __riscv_vsetvl_e8mf4(avl);
@@ -29,8 +80,32 @@ size_t test_vsetvl_e8mf4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8mf2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8mf2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8mf2(size_t avl) {
return __riscv_vsetvl_e8mf2(avl);
@@ -39,8 +114,32 @@ size_t test_vsetvl_e8mf2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m1(size_t avl) {
return __riscv_vsetvl_e8m1(avl);
@@ -49,8 +148,32 @@ size_t test_vsetvl_e8m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m2(size_t avl) {
return __riscv_vsetvl_e8m2(avl);
@@ -59,8 +182,32 @@ size_t test_vsetvl_e8m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m4(size_t avl) {
return __riscv_vsetvl_e8m4(avl);
@@ -69,8 +216,32 @@ size_t test_vsetvl_e8m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e8m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e8m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e8m8(size_t avl) {
return __riscv_vsetvl_e8m8(avl);
@@ -79,8 +250,32 @@ size_t test_vsetvl_e8m8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16mf4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16mf4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16mf4(size_t avl) {
return __riscv_vsetvl_e16mf4(avl);
@@ -89,8 +284,32 @@ size_t test_vsetvl_e16mf4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16mf2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16mf2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16mf2(size_t avl) {
return __riscv_vsetvl_e16mf2(avl);
@@ -99,8 +318,32 @@ size_t test_vsetvl_e16mf2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m1(size_t avl) {
return __riscv_vsetvl_e16m1(avl);
@@ -109,8 +352,32 @@ size_t test_vsetvl_e16m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m2(size_t avl) {
return __riscv_vsetvl_e16m2(avl);
@@ -119,8 +386,32 @@ size_t test_vsetvl_e16m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m4(size_t avl) {
return __riscv_vsetvl_e16m4(avl);
@@ -129,8 +420,32 @@ size_t test_vsetvl_e16m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e16m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e16m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e16m8(size_t avl) {
return __riscv_vsetvl_e16m8(avl);
@@ -139,8 +454,32 @@ size_t test_vsetvl_e16m8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32mf2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32mf2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32mf2(size_t avl) {
return __riscv_vsetvl_e32mf2(avl);
@@ -149,8 +488,32 @@ size_t test_vsetvl_e32mf2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m1(size_t avl) {
return __riscv_vsetvl_e32m1(avl);
@@ -159,8 +522,32 @@ size_t test_vsetvl_e32m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m2(size_t avl) {
return __riscv_vsetvl_e32m2(avl);
@@ -169,8 +556,32 @@ size_t test_vsetvl_e32m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m4(size_t avl) {
return __riscv_vsetvl_e32m4(avl);
@@ -179,8 +590,32 @@ size_t test_vsetvl_e32m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e32m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e32m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e32m8(size_t avl) {
return __riscv_vsetvl_e32m8(avl);
@@ -189,8 +624,32 @@ size_t test_vsetvl_e32m8(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m1
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m1
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m1(size_t avl) {
return __riscv_vsetvl_e64m1(avl);
@@ -199,8 +658,32 @@ size_t test_vsetvl_e64m1(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m2
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m2
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m2(size_t avl) {
return __riscv_vsetvl_e64m2(avl);
@@ -209,8 +692,32 @@ size_t test_vsetvl_e64m2(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m4
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m4
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m4(size_t avl) {
return __riscv_vsetvl_e64m4(avl);
@@ -219,8 +726,32 @@ size_t test_vsetvl_e64m4(size_t avl) {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvl_e64m8
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64: assumption:
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64: assumption_end:
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvl_e64m8
+// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64-FIXED: assumption:
+// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
+// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64-FIXED: assumption_end:
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvl_e64m8(size_t avl) {
return __riscv_vsetvl_e64m8(avl);
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
index 792e43c22f519b..fd6d091df69102 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
@@ -3,14 +3,28 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone \
+// RUN: -mvscale-min=2 -mvscale-max=2 -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64-FIXED %s
+
#include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8mf8
// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8mf8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8mf8() {
return __riscv_vsetvlmax_e8mf8();
@@ -19,8 +33,18 @@ size_t test_vsetvlmax_e8mf8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8mf4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8mf4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8mf4() {
return __riscv_vsetvlmax_e8mf4();
@@ -29,8 +53,18 @@ size_t test_vsetvlmax_e8mf4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8mf2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8mf2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8mf2() {
return __riscv_vsetvlmax_e8mf2();
@@ -39,8 +73,18 @@ size_t test_vsetvlmax_e8mf2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m1() {
return __riscv_vsetvlmax_e8m1();
@@ -49,8 +93,18 @@ size_t test_vsetvlmax_e8m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m2() {
return __riscv_vsetvlmax_e8m2();
@@ -59,8 +113,18 @@ size_t test_vsetvlmax_e8m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m4() {
return __riscv_vsetvlmax_e8m4();
@@ -69,8 +133,18 @@ size_t test_vsetvlmax_e8m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e8m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e8m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e8m8() {
return __riscv_vsetvlmax_e8m8();
@@ -79,8 +153,18 @@ size_t test_vsetvlmax_e8m8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16mf4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16mf4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16mf4() {
return __riscv_vsetvlmax_e16mf4();
@@ -89,8 +173,18 @@ size_t test_vsetvlmax_e16mf4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16mf2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16mf2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16mf2() {
return __riscv_vsetvlmax_e16mf2();
@@ -99,8 +193,18 @@ size_t test_vsetvlmax_e16mf2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m1() {
return __riscv_vsetvlmax_e16m1();
@@ -109,8 +213,18 @@ size_t test_vsetvlmax_e16m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m2() {
return __riscv_vsetvlmax_e16m2();
@@ -119,8 +233,18 @@ size_t test_vsetvlmax_e16m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m4() {
return __riscv_vsetvlmax_e16m4();
@@ -129,8 +253,18 @@ size_t test_vsetvlmax_e16m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e16m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e16m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e16m8() {
return __riscv_vsetvlmax_e16m8();
@@ -139,8 +273,18 @@ size_t test_vsetvlmax_e16m8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32mf2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32mf2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32mf2() {
return __riscv_vsetvlmax_e32mf2();
@@ -149,8 +293,18 @@ size_t test_vsetvlmax_e32mf2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m1() {
return __riscv_vsetvlmax_e32m1();
@@ -159,8 +313,18 @@ size_t test_vsetvlmax_e32m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m2() {
return __riscv_vsetvlmax_e32m2();
@@ -169,8 +333,18 @@ size_t test_vsetvlmax_e32m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m4() {
return __riscv_vsetvlmax_e32m4();
@@ -179,8 +353,18 @@ size_t test_vsetvlmax_e32m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e32m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e32m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e32m8() {
return __riscv_vsetvlmax_e32m8();
@@ -189,8 +373,18 @@ size_t test_vsetvlmax_e32m8() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m1
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m1
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m1() {
return __riscv_vsetvlmax_e64m1();
@@ -199,8 +393,18 @@ size_t test_vsetvlmax_e64m1() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m2
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m2
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m2() {
return __riscv_vsetvlmax_e64m2();
@@ -209,8 +413,18 @@ size_t test_vsetvlmax_e64m2() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m4
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m4
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m4() {
return __riscv_vsetvlmax_e64m4();
@@ -219,8 +433,18 @@ size_t test_vsetvlmax_e64m4() {
// CHECK-RV64-LABEL: define dso_local i64 @test_vsetvlmax_e64m8
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
-// CHECK-RV64-NEXT: ret i64 [[TMP0]]
+// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-NEXT: ret i64 [[VL]]
+//
+// CHECK-RV64-FIXED-LABEL: define dso_local i64 @test_vsetvlmax_e64m8
+// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
+// CHECK-RV64-FIXED-NEXT: entry:
+// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 3)
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
size_t test_vsetvlmax_e64m8() {
return __riscv_vsetvlmax_e64m8();
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
index 6ec9b057997690..601cc379563cf8 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-error.c
@@ -6,8 +6,14 @@
// CHECK-RV64V-LABEL: @test(
// CHECK-RV64V-NEXT: entry:
-// CHECK-RV64V-NEXT: [[TMP0:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
-// CHECK-RV64V-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
+// CHECK-RV64V-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 0, i64 0)
+// CHECK-RV64V-NEXT: br i1 true, label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
+// CHECK-RV64V: assumption:
+// CHECK-RV64V-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 1
+// CHECK-RV64V-NEXT: call void @llvm.assume(i1 [[TMP0]])
+// CHECK-RV64V-NEXT: br label [[ASSUMPTION_END]]
+// CHECK-RV64V: assumption_end:
+// CHECK-RV64V-NEXT: [[CONV:%.*]] = trunc i64 [[VL]] to i32
// CHECK-RV64V-NEXT: ret i32 [[CONV]]
//
>From 35cd4977c4ea595f21c426db22d139c0a83ddd83 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 1 Feb 2024 15:17:53 +0800
Subject: [PATCH 2/3] Add a test to show the optimization
Created using spr 1.3.4
---
.../vsetvl-assumption.c | 370 ++++++++++++++++++
1 file changed, 370 insertions(+)
create mode 100644 clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsetvl-assumption.c
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsetvl-assumption.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsetvl-assumption.c
new file mode 100644
index 00000000000000..bd61f2b134430d
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsetvl-assumption.c
@@ -0,0 +1,370 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck --check-prefix=RV32 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck --check-prefix=RV64 %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -O2 -emit-llvm %s -o - \
+// RUN: -mvscale-min=2 -mvscale-max=2 \
+// RUN: | FileCheck --check-prefix=RV32-FIXED %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -O2 -emit-llvm %s -o - \
+// RUN: -mvscale-min=2 -mvscale-max=2 \
+// RUN: | FileCheck --check-prefix=RV64-FIXED %s
+
+#include <riscv_vector.h>
+
+inline void test_vsetvlmax(void *data, size_t len) {
+ uint8_t *ptr = (uint8_t *)data;
+ size_t vl = __riscv_vsetvlmax_e8m1();
+ vuint8m1_t zero = __riscv_vmv_v_x_u8m1(0, vl);
+ while (len > vl) {
+ __riscv_vse8(ptr, zero, vl);
+ ptr += vl;
+ len -= vl;
+ }
+ __riscv_vse8(ptr, zero, len);
+}
+
+inline void test_vsetvli(void *data, size_t len) {
+ uint8_t *ptr = (uint8_t *)data;
+ size_t vl = __riscv_vsetvl_e8m1(len);
+ while (len > 0) {
+ vuint8m1_t zero = __riscv_vmv_v_x_u8m1(0, vl);
+ __riscv_vse8(ptr, zero, vl);
+ ptr += vl;
+ len -= vl;
+ vl = __riscv_vsetvl_e8m1(len);
+ }
+}
+
+// RV32-LABEL: @test_vsetvlmax_known_vl(
+// RV32-NEXT: test_vsetvlmax.exit:
+// RV32-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvlimax.i32(i32 0, i32 0)
+// RV32-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[VL1_I]], 15
+// RV32-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV32-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 [[VL1_I]])
+// RV32-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i32 8)
+// RV32-NEXT: ret void
+//
+// RV64-LABEL: @test_vsetvlmax_known_vl(
+// RV64-NEXT: test_vsetvlmax.exit:
+// RV64-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// RV64-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[VL1_I]], 15
+// RV64-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV64-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 [[VL1_I]])
+// RV64-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i64 8)
+// RV64-NEXT: ret void
+//
+// RV32-FIXED-LABEL: @test_vsetvlmax_known_vl(
+// RV32-FIXED-NEXT: entry:
+// RV32-FIXED-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvlimax.i32(i32 0, i32 0)
+// RV32-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i32 [[VL1_I]], 16
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV32-FIXED-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 16)
+// RV32-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i32 8)
+// RV32-FIXED-NEXT: ret void
+//
+// RV64-FIXED-LABEL: @test_vsetvlmax_known_vl(
+// RV64-FIXED-NEXT: entry:
+// RV64-FIXED-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL1_I]], 16
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV64-FIXED-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 16)
+// RV64-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i64 8)
+// RV64-FIXED-NEXT: ret void
+//
+void test_vsetvlmax_known_vl(uint64_t* data) { test_vsetvlmax(data, sizeof(uint64_t)); }
+
+// RV32-LABEL: @test_vsetvlmax_agnostic_vl(
+// RV32-NEXT: entry:
+// RV32-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvlimax.i32(i32 0, i32 0)
+// RV32-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[VL1_I]], 15
+// RV32-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV32-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 [[VL1_I]])
+// RV32-NEXT: [[CMP10_I:%.*]] = icmp ult i32 [[VL1_I]], [[LEN:%.*]]
+// RV32-NEXT: br i1 [[CMP10_I]], label [[WHILE_BODY_I:%.*]], label [[TEST_VSETVLMAX_EXIT:%.*]]
+// RV32: while.body.i:
+// RV32-NEXT: [[LEN_ADDR_012_I:%.*]] = phi i32 [ [[SUB_I:%.*]], [[WHILE_BODY_I]] ], [ [[LEN]], [[ENTRY:%.*]] ]
+// RV32-NEXT: [[PTR_011_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[DATA:%.*]], [[ENTRY]] ]
+// RV32-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_011_I]], i32 [[VL1_I]])
+// RV32-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_011_I]], i32 [[VL1_I]]
+// RV32-NEXT: [[SUB_I]] = sub i32 [[LEN_ADDR_012_I]], [[VL1_I]]
+// RV32-NEXT: [[CMP_I:%.*]] = icmp ugt i32 [[SUB_I]], [[VL1_I]]
+// RV32-NEXT: br i1 [[CMP_I]], label [[WHILE_BODY_I]], label [[TEST_VSETVLMAX_EXIT]], !llvm.loop [[LOOP4:![0-9]+]]
+// RV32: test_vsetvlmax.exit:
+// RV32-NEXT: [[PTR_0_LCSSA_I:%.*]] = phi ptr [ [[DATA]], [[ENTRY]] ], [ [[ADD_PTR_I]], [[WHILE_BODY_I]] ]
+// RV32-NEXT: [[LEN_ADDR_0_LCSSA_I:%.*]] = phi i32 [ [[LEN]], [[ENTRY]] ], [ [[SUB_I]], [[WHILE_BODY_I]] ]
+// RV32-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_0_LCSSA_I]], i32 [[LEN_ADDR_0_LCSSA_I]])
+// RV32-NEXT: ret void
+//
+// RV64-LABEL: @test_vsetvlmax_agnostic_vl(
+// RV64-NEXT: entry:
+// RV64-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// RV64-NEXT: [[TMP0:%.*]] = icmp ugt i64 [[VL1_I]], 15
+// RV64-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV64-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 [[VL1_I]])
+// RV64-NEXT: [[CMP10_I:%.*]] = icmp ult i64 [[VL1_I]], [[LEN:%.*]]
+// RV64-NEXT: br i1 [[CMP10_I]], label [[WHILE_BODY_I:%.*]], label [[TEST_VSETVLMAX_EXIT:%.*]]
+// RV64: while.body.i:
+// RV64-NEXT: [[LEN_ADDR_012_I:%.*]] = phi i64 [ [[SUB_I:%.*]], [[WHILE_BODY_I]] ], [ [[LEN]], [[ENTRY:%.*]] ]
+// RV64-NEXT: [[PTR_011_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[DATA:%.*]], [[ENTRY]] ]
+// RV64-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_011_I]], i64 [[VL1_I]])
+// RV64-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_011_I]], i64 [[VL1_I]]
+// RV64-NEXT: [[SUB_I]] = sub i64 [[LEN_ADDR_012_I]], [[VL1_I]]
+// RV64-NEXT: [[CMP_I:%.*]] = icmp ugt i64 [[SUB_I]], [[VL1_I]]
+// RV64-NEXT: br i1 [[CMP_I]], label [[WHILE_BODY_I]], label [[TEST_VSETVLMAX_EXIT]], !llvm.loop [[LOOP4:![0-9]+]]
+// RV64: test_vsetvlmax.exit:
+// RV64-NEXT: [[PTR_0_LCSSA_I:%.*]] = phi ptr [ [[DATA]], [[ENTRY]] ], [ [[ADD_PTR_I]], [[WHILE_BODY_I]] ]
+// RV64-NEXT: [[LEN_ADDR_0_LCSSA_I:%.*]] = phi i64 [ [[LEN]], [[ENTRY]] ], [ [[SUB_I]], [[WHILE_BODY_I]] ]
+// RV64-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_0_LCSSA_I]], i64 [[LEN_ADDR_0_LCSSA_I]])
+// RV64-NEXT: ret void
+//
+// RV32-FIXED-LABEL: @test_vsetvlmax_agnostic_vl(
+// RV32-FIXED-NEXT: entry:
+// RV32-FIXED-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvlimax.i32(i32 0, i32 0)
+// RV32-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i32 [[VL1_I]], 16
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV32-FIXED-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 16)
+// RV32-FIXED-NEXT: [[CMP10_I:%.*]] = icmp ugt i32 [[LEN:%.*]], 16
+// RV32-FIXED-NEXT: br i1 [[CMP10_I]], label [[WHILE_BODY_I:%.*]], label [[TEST_VSETVLMAX_EXIT:%.*]]
+// RV32-FIXED: while.body.i:
+// RV32-FIXED-NEXT: [[LEN_ADDR_012_I:%.*]] = phi i32 [ [[SUB_I:%.*]], [[WHILE_BODY_I]] ], [ [[LEN]], [[ENTRY:%.*]] ]
+// RV32-FIXED-NEXT: [[PTR_011_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[DATA:%.*]], [[ENTRY]] ]
+// RV32-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_011_I]], i32 16)
+// RV32-FIXED-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_011_I]], i32 16
+// RV32-FIXED-NEXT: [[SUB_I]] = add i32 [[LEN_ADDR_012_I]], -16
+// RV32-FIXED-NEXT: [[CMP_I:%.*]] = icmp ugt i32 [[SUB_I]], 16
+// RV32-FIXED-NEXT: br i1 [[CMP_I]], label [[WHILE_BODY_I]], label [[TEST_VSETVLMAX_EXIT]], !llvm.loop [[LOOP4:![0-9]+]]
+// RV32-FIXED: test_vsetvlmax.exit:
+// RV32-FIXED-NEXT: [[PTR_0_LCSSA_I:%.*]] = phi ptr [ [[DATA]], [[ENTRY]] ], [ [[ADD_PTR_I]], [[WHILE_BODY_I]] ]
+// RV32-FIXED-NEXT: [[LEN_ADDR_0_LCSSA_I:%.*]] = phi i32 [ [[LEN]], [[ENTRY]] ], [ [[SUB_I]], [[WHILE_BODY_I]] ]
+// RV32-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_0_LCSSA_I]], i32 [[LEN_ADDR_0_LCSSA_I]])
+// RV32-FIXED-NEXT: ret void
+//
+// RV64-FIXED-LABEL: @test_vsetvlmax_agnostic_vl(
+// RV64-FIXED-NEXT: entry:
+// RV64-FIXED-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 0)
+// RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL1_I]], 16
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV64-FIXED-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 16)
+// RV64-FIXED-NEXT: [[CMP10_I:%.*]] = icmp ugt i64 [[LEN:%.*]], 16
+// RV64-FIXED-NEXT: br i1 [[CMP10_I]], label [[WHILE_BODY_I:%.*]], label [[TEST_VSETVLMAX_EXIT:%.*]]
+// RV64-FIXED: while.body.i:
+// RV64-FIXED-NEXT: [[LEN_ADDR_012_I:%.*]] = phi i64 [ [[SUB_I:%.*]], [[WHILE_BODY_I]] ], [ [[LEN]], [[ENTRY:%.*]] ]
+// RV64-FIXED-NEXT: [[PTR_011_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[WHILE_BODY_I]] ], [ [[DATA:%.*]], [[ENTRY]] ]
+// RV64-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_011_I]], i64 16)
+// RV64-FIXED-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_011_I]], i64 16
+// RV64-FIXED-NEXT: [[SUB_I]] = add i64 [[LEN_ADDR_012_I]], -16
+// RV64-FIXED-NEXT: [[CMP_I:%.*]] = icmp ugt i64 [[SUB_I]], 16
+// RV64-FIXED-NEXT: br i1 [[CMP_I]], label [[WHILE_BODY_I]], label [[TEST_VSETVLMAX_EXIT]], !llvm.loop [[LOOP4:![0-9]+]]
+// RV64-FIXED: test_vsetvlmax.exit:
+// RV64-FIXED-NEXT: [[PTR_0_LCSSA_I:%.*]] = phi ptr [ [[DATA]], [[ENTRY]] ], [ [[ADD_PTR_I]], [[WHILE_BODY_I]] ]
+// RV64-FIXED-NEXT: [[LEN_ADDR_0_LCSSA_I:%.*]] = phi i64 [ [[LEN]], [[ENTRY]] ], [ [[SUB_I]], [[WHILE_BODY_I]] ]
+// RV64-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[PTR_0_LCSSA_I]], i64 [[LEN_ADDR_0_LCSSA_I]])
+// RV64-FIXED-NEXT: ret void
+//
+void test_vsetvlmax_agnostic_vl(void *data, size_t len) { test_vsetvlmax(data, len); }
+
+// RV32-LABEL: @test_vsetvli_known_vl(
+// RV32-NEXT: assumption_end4.i:
+// RV32-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 8, i32 0, i32 0)
+// RV32-NEXT: [[TMP0:%.*]] = icmp eq i32 [[VL1_I]], 8
+// RV32-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV32-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 8)
+// RV32-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i32 8)
+// RV32-NEXT: [[VL2_I:%.*]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 0, i32 0, i32 0)
+// RV32-NEXT: [[TMP2:%.*]] = icmp eq i32 [[VL2_I]], 0
+// RV32-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
+// RV32-NEXT: ret void
+//
+// RV64-LABEL: @test_vsetvli_known_vl(
+// RV64-NEXT: assumption_end4.i:
+// RV64-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 8, i64 0, i64 0)
+// RV64-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL1_I]], 8
+// RV64-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV64-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 8)
+// RV64-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i64 8)
+// RV64-NEXT: [[VL2_I:%.*]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 0, i64 0, i64 0)
+// RV64-NEXT: [[TMP2:%.*]] = icmp eq i64 [[VL2_I]], 0
+// RV64-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
+// RV64-NEXT: ret void
+//
+// RV32-FIXED-LABEL: @test_vsetvli_known_vl(
+// RV32-FIXED-NEXT: assumption_end4.i:
+// RV32-FIXED-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 8, i32 0, i32 0)
+// RV32-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i32 [[VL1_I]], 8
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV32-FIXED-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 8)
+// RV32-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i32 8)
+// RV32-FIXED-NEXT: [[VL2_I:%.*]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 0, i32 0, i32 0)
+// RV32-FIXED-NEXT: [[TMP2:%.*]] = icmp eq i32 [[VL2_I]], 0
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
+// RV32-FIXED-NEXT: ret void
+//
+// RV64-FIXED-LABEL: @test_vsetvli_known_vl(
+// RV64-FIXED-NEXT: assumption_end4.i:
+// RV64-FIXED-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 8, i64 0, i64 0)
+// RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL1_I]], 8
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
+// RV64-FIXED-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 8)
+// RV64-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP1]], ptr [[DATA:%.*]], i64 8)
+// RV64-FIXED-NEXT: [[VL2_I:%.*]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 0, i64 0, i64 0)
+// RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp eq i64 [[VL2_I]], 0
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
+// RV64-FIXED-NEXT: ret void
+//
+void test_vsetvli_known_vl(uint64_t* data) { test_vsetvli(data, sizeof(uint64_t)); }
+
+// RV32-LABEL: @test_vsetvli_agnostic_vl(
+// RV32-NEXT: entry:
+// RV32-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 [[LEN:%.*]], i32 0, i32 0)
+// RV32-NEXT: [[TMP0:%.*]] = icmp ult i32 [[LEN]], 17
+// RV32-NEXT: br i1 [[TMP0]], label [[ASSUMPTION_END_I:%.*]], label [[WHILE_BODY_I_PREHEADER:%.*]]
+// RV32: assumption_end.i:
+// RV32-NEXT: [[TMP1:%.*]] = icmp eq i32 [[VL1_I]], [[LEN]]
+// RV32-NEXT: tail call void @llvm.assume(i1 [[TMP1]])
+// RV32-NEXT: [[CMP_NOT12_I:%.*]] = icmp eq i32 [[LEN]], 0
+// RV32-NEXT: br i1 [[CMP_NOT12_I]], label [[TEST_VSETVLI_EXIT:%.*]], label [[WHILE_BODY_I_PREHEADER]]
+// RV32: while.body.i.preheader:
+// RV32-NEXT: br label [[WHILE_BODY_I:%.*]]
+// RV32: while.body.i:
+// RV32-NEXT: [[LEN_ADDR_015_I:%.*]] = phi i32 [ [[SUB_I:%.*]], [[ASSUMPTION_END4_I:%.*]] ], [ [[LEN]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV32-NEXT: [[VL_014_I:%.*]] = phi i32 [ [[VL2_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[VL1_I]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV32-NEXT: [[PTR_013_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[DATA:%.*]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV32-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 [[VL_014_I]])
+// RV32-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP2]], ptr [[PTR_013_I]], i32 [[VL_014_I]])
+// RV32-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_013_I]], i32 [[VL_014_I]]
+// RV32-NEXT: [[SUB_I]] = sub i32 [[LEN_ADDR_015_I]], [[VL_014_I]]
+// RV32-NEXT: [[VL2_I]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 [[SUB_I]], i32 0, i32 0)
+// RV32-NEXT: [[TMP3:%.*]] = icmp ult i32 [[SUB_I]], 17
+// RV32-NEXT: br i1 [[TMP3]], label [[ASSUMPTION3_I:%.*]], label [[ASSUMPTION_END4_I]]
+// RV32: assumption3.i:
+// RV32-NEXT: [[TMP4:%.*]] = icmp eq i32 [[VL2_I]], [[SUB_I]]
+// RV32-NEXT: tail call void @llvm.assume(i1 [[TMP4]])
+// RV32-NEXT: br label [[ASSUMPTION_END4_I]]
+// RV32: assumption_end4.i:
+// RV32-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i32 [[SUB_I]], 0
+// RV32-NEXT: br i1 [[CMP_NOT_I]], label [[TEST_VSETVLI_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP6:![0-9]+]]
+// RV32: test_vsetvli.exit:
+// RV32-NEXT: ret void
+//
+// RV64-LABEL: @test_vsetvli_agnostic_vl(
+// RV64-NEXT: entry:
+// RV64-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 [[LEN:%.*]], i64 0, i64 0)
+// RV64-NEXT: [[TMP0:%.*]] = icmp ult i64 [[LEN]], 17
+// RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION_END_I:%.*]], label [[WHILE_BODY_I_PREHEADER:%.*]]
+// RV64: assumption_end.i:
+// RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL1_I]], [[LEN]]
+// RV64-NEXT: tail call void @llvm.assume(i1 [[TMP1]])
+// RV64-NEXT: [[CMP_NOT12_I:%.*]] = icmp eq i64 [[LEN]], 0
+// RV64-NEXT: br i1 [[CMP_NOT12_I]], label [[TEST_VSETVLI_EXIT:%.*]], label [[WHILE_BODY_I_PREHEADER]]
+// RV64: while.body.i.preheader:
+// RV64-NEXT: br label [[WHILE_BODY_I:%.*]]
+// RV64: while.body.i:
+// RV64-NEXT: [[LEN_ADDR_015_I:%.*]] = phi i64 [ [[SUB_I:%.*]], [[ASSUMPTION_END4_I:%.*]] ], [ [[LEN]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV64-NEXT: [[VL_014_I:%.*]] = phi i64 [ [[VL2_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[VL1_I]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV64-NEXT: [[PTR_013_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[DATA:%.*]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV64-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 [[VL_014_I]])
+// RV64-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP2]], ptr [[PTR_013_I]], i64 [[VL_014_I]])
+// RV64-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_013_I]], i64 [[VL_014_I]]
+// RV64-NEXT: [[SUB_I]] = sub i64 [[LEN_ADDR_015_I]], [[VL_014_I]]
+// RV64-NEXT: [[VL2_I]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 [[SUB_I]], i64 0, i64 0)
+// RV64-NEXT: [[TMP3:%.*]] = icmp ult i64 [[SUB_I]], 17
+// RV64-NEXT: br i1 [[TMP3]], label [[ASSUMPTION3_I:%.*]], label [[ASSUMPTION_END4_I]]
+// RV64: assumption3.i:
+// RV64-NEXT: [[TMP4:%.*]] = icmp eq i64 [[VL2_I]], [[SUB_I]]
+// RV64-NEXT: tail call void @llvm.assume(i1 [[TMP4]])
+// RV64-NEXT: br label [[ASSUMPTION_END4_I]]
+// RV64: assumption_end4.i:
+// RV64-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i64 [[SUB_I]], 0
+// RV64-NEXT: br i1 [[CMP_NOT_I]], label [[TEST_VSETVLI_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP6:![0-9]+]]
+// RV64: test_vsetvli.exit:
+// RV64-NEXT: ret void
+//
+// RV32-FIXED-LABEL: @test_vsetvli_agnostic_vl(
+// RV32-FIXED-NEXT: entry:
+// RV32-FIXED-NEXT: [[VL1_I:%.*]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 [[LEN:%.*]], i32 0, i32 0)
+// RV32-FIXED-NEXT: [[TMP0:%.*]] = icmp ult i32 [[LEN]], 17
+// RV32-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION_END_I:%.*]], label [[ASSUMPTION_END_THREAD_I:%.*]]
+// RV32-FIXED: assumption_end.thread.i:
+// RV32-FIXED-NEXT: [[TMP1:%.*]] = icmp ult i32 [[LEN]], 32
+// RV32-FIXED-NEXT: [[TMP2:%.*]] = icmp eq i32 [[VL1_I]], 16
+// RV32-FIXED-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]]
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP3]])
+// RV32-FIXED-NEXT: br label [[WHILE_BODY_I_PREHEADER:%.*]]
+// RV32-FIXED: assumption_end.i:
+// RV32-FIXED-NEXT: [[TMP4:%.*]] = icmp eq i32 [[VL1_I]], [[LEN]]
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP4]])
+// RV32-FIXED-NEXT: [[CMP_NOT12_I:%.*]] = icmp eq i32 [[LEN]], 0
+// RV32-FIXED-NEXT: br i1 [[CMP_NOT12_I]], label [[TEST_VSETVLI_EXIT:%.*]], label [[WHILE_BODY_I_PREHEADER]]
+// RV32-FIXED: while.body.i.preheader:
+// RV32-FIXED-NEXT: br label [[WHILE_BODY_I:%.*]]
+// RV32-FIXED: while.body.i:
+// RV32-FIXED-NEXT: [[LEN_ADDR_015_I:%.*]] = phi i32 [ [[SUB_I:%.*]], [[ASSUMPTION_END4_I:%.*]] ], [ [[LEN]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV32-FIXED-NEXT: [[VL_014_I:%.*]] = phi i32 [ [[VL2_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[VL1_I]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV32-FIXED-NEXT: [[PTR_013_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[DATA:%.*]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV32-FIXED-NEXT: [[TMP5:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i32(<vscale x 8 x i8> poison, i8 0, i32 [[VL_014_I]])
+// RV32-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i32(<vscale x 8 x i8> [[TMP5]], ptr [[PTR_013_I]], i32 [[VL_014_I]])
+// RV32-FIXED-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_013_I]], i32 [[VL_014_I]]
+// RV32-FIXED-NEXT: [[SUB_I]] = sub i32 [[LEN_ADDR_015_I]], [[VL_014_I]]
+// RV32-FIXED-NEXT: [[VL2_I]] = tail call i32 @llvm.riscv.vsetvli.i32(i32 [[SUB_I]], i32 0, i32 0)
+// RV32-FIXED-NEXT: [[TMP6:%.*]] = icmp ult i32 [[SUB_I]], 17
+// RV32-FIXED-NEXT: br i1 [[TMP6]], label [[ASSUMPTION3_I:%.*]], label [[ASSUMPTION_END4_I]]
+// RV32-FIXED: assumption3.i:
+// RV32-FIXED-NEXT: [[TMP7:%.*]] = icmp eq i32 [[VL2_I]], [[SUB_I]]
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP7]])
+// RV32-FIXED-NEXT: br label [[ASSUMPTION_END4_I]]
+// RV32-FIXED: assumption_end4.i:
+// RV32-FIXED-NEXT: [[TMP8:%.*]] = icmp ult i32 [[SUB_I]], 32
+// RV32-FIXED-NEXT: [[TMP9:%.*]] = icmp eq i32 [[VL2_I]], 16
+// RV32-FIXED-NEXT: [[TMP10:%.*]] = select i1 [[TMP8]], i1 true, i1 [[TMP9]]
+// RV32-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP10]])
+// RV32-FIXED-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i32 [[SUB_I]], 0
+// RV32-FIXED-NEXT: br i1 [[CMP_NOT_I]], label [[TEST_VSETVLI_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP6:![0-9]+]]
+// RV32-FIXED: test_vsetvli.exit:
+// RV32-FIXED-NEXT: ret void
+//
+// RV64-FIXED-LABEL: @test_vsetvli_agnostic_vl(
+// RV64-FIXED-NEXT: entry:
+// RV64-FIXED-NEXT: [[VL1_I:%.*]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 [[LEN:%.*]], i64 0, i64 0)
+// RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ult i64 [[LEN]], 17
+// RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION_END_I:%.*]], label [[ASSUMPTION_END_THREAD_I:%.*]]
+// RV64-FIXED: assumption_end.thread.i:
+// RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp ult i64 [[LEN]], 32
+// RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp eq i64 [[VL1_I]], 16
+// RV64-FIXED-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i1 true, i1 [[TMP2]]
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP3]])
+// RV64-FIXED-NEXT: br label [[WHILE_BODY_I_PREHEADER:%.*]]
+// RV64-FIXED: assumption_end.i:
+// RV64-FIXED-NEXT: [[TMP4:%.*]] = icmp eq i64 [[VL1_I]], [[LEN]]
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP4]])
+// RV64-FIXED-NEXT: [[CMP_NOT12_I:%.*]] = icmp eq i64 [[LEN]], 0
+// RV64-FIXED-NEXT: br i1 [[CMP_NOT12_I]], label [[TEST_VSETVLI_EXIT:%.*]], label [[WHILE_BODY_I_PREHEADER]]
+// RV64-FIXED: while.body.i.preheader:
+// RV64-FIXED-NEXT: br label [[WHILE_BODY_I:%.*]]
+// RV64-FIXED: while.body.i:
+// RV64-FIXED-NEXT: [[LEN_ADDR_015_I:%.*]] = phi i64 [ [[SUB_I:%.*]], [[ASSUMPTION_END4_I:%.*]] ], [ [[LEN]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV64-FIXED-NEXT: [[VL_014_I:%.*]] = phi i64 [ [[VL2_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[VL1_I]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV64-FIXED-NEXT: [[PTR_013_I:%.*]] = phi ptr [ [[ADD_PTR_I:%.*]], [[ASSUMPTION_END4_I]] ], [ [[DATA:%.*]], [[WHILE_BODY_I_PREHEADER]] ]
+// RV64-FIXED-NEXT: [[TMP5:%.*]] = tail call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i64(<vscale x 8 x i8> poison, i8 0, i64 [[VL_014_I]])
+// RV64-FIXED-NEXT: tail call void @llvm.riscv.vse.nxv8i8.i64(<vscale x 8 x i8> [[TMP5]], ptr [[PTR_013_I]], i64 [[VL_014_I]])
+// RV64-FIXED-NEXT: [[ADD_PTR_I]] = getelementptr inbounds i8, ptr [[PTR_013_I]], i64 [[VL_014_I]]
+// RV64-FIXED-NEXT: [[SUB_I]] = sub i64 [[LEN_ADDR_015_I]], [[VL_014_I]]
+// RV64-FIXED-NEXT: [[VL2_I]] = tail call i64 @llvm.riscv.vsetvli.i64(i64 [[SUB_I]], i64 0, i64 0)
+// RV64-FIXED-NEXT: [[TMP6:%.*]] = icmp ult i64 [[SUB_I]], 17
+// RV64-FIXED-NEXT: br i1 [[TMP6]], label [[ASSUMPTION3_I:%.*]], label [[ASSUMPTION_END4_I]]
+// RV64-FIXED: assumption3.i:
+// RV64-FIXED-NEXT: [[TMP7:%.*]] = icmp eq i64 [[VL2_I]], [[SUB_I]]
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP7]])
+// RV64-FIXED-NEXT: br label [[ASSUMPTION_END4_I]]
+// RV64-FIXED: assumption_end4.i:
+// RV64-FIXED-NEXT: [[TMP8:%.*]] = icmp ult i64 [[SUB_I]], 32
+// RV64-FIXED-NEXT: [[TMP9:%.*]] = icmp eq i64 [[VL2_I]], 16
+// RV64-FIXED-NEXT: [[TMP10:%.*]] = select i1 [[TMP8]], i1 true, i1 [[TMP9]]
+// RV64-FIXED-NEXT: tail call void @llvm.assume(i1 [[TMP10]])
+// RV64-FIXED-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i64 [[SUB_I]], 0
+// RV64-FIXED-NEXT: br i1 [[CMP_NOT_I]], label [[TEST_VSETVLI_EXIT]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP6:![0-9]+]]
+// RV64-FIXED: test_vsetvli.exit:
+// RV64-FIXED-NEXT: ret void
+//
+void test_vsetvli_agnostic_vl(void *data, size_t len) { test_vsetvli(data, len); }
>From 28e571f7e8af000b0027ddec66fcc9dd12b3b465 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Sun, 18 Feb 2024 19:27:45 +0800
Subject: [PATCH 3/3] Take SEW/LMUL into account
Created using spr 1.3.4
---
clang/include/clang/Basic/riscv_vector.td | 34 +++--
.../non-policy/non-overloaded/vsetvl.c | 144 +++++++++---------
.../non-policy/non-overloaded/vsetvlmax.c | 72 ++++-----
.../policy/non-overloaded/vsetvl.c | 144 +++++++++---------
.../policy/non-overloaded/vsetvlmax.c | 72 ++++-----
5 files changed, 238 insertions(+), 228 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 84f61e3be4cfa4..8dc378e6132b8f 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -680,20 +680,25 @@ let HasBuiltinAlias = false,
const TargetInfo &TI = getContext().getTargetInfo();
auto VScale = TI.getVScaleRange(getContext().getLangOpts());
+ uint64_t SEW = 1 << (cast<ConstantInt>(Ops[1])->getZExtValue() + 3);
+ uint64_t LMUL = cast<ConstantInt>(Ops[2])->getZExtValue();
+ bool Fractional = LMUL > 4;
+ uint64_t VLMAX = Fractional ? VScale->first * 64 / (1 << (8 - LMUL)) / SEW
+ : VScale->first * 64 * (1 << LMUL) / SEW;
- if (VScale && VScale->first && VScale->first == VScale->second) {
+ if (VScale->first && VScale->first == VScale->second) {
// Assumptions:
// Let:
- // fixed_vl = __riscv_v_fixed_vlen / 8;
+ // fixed_vl = __riscv_v_fixed_vlen * LMUL / SEW;
// We have:
// (avl > fixed_vl || vl == avl)
// and
// (avl < fixed_vl * 2 || vl == fixed_vl)
- Value *FixedVL = llvm::ConstantInt::get(ResultType, VScale->first * 8);
+ Value *FixedVL = llvm::ConstantInt::get(ResultType, VLMAX);
Value *FixedVLx2 =
- llvm::ConstantInt::get(ResultType, VScale->first * 8 * 2);
+ llvm::ConstantInt::get(ResultType, VLMAX * 2);
Value *Cond0 = Builder.CreateICmpULE(
- Ops[0], ConstantInt::get(ResultType, VScale->first * 8));
+ Ops[0], ConstantInt::get(ResultType, VLMAX));
BasicBlock *AssumptionBlock =
createBasicBlock("assumption", this->CurFn);
@@ -713,11 +718,11 @@ let HasBuiltinAlias = false,
} else {
// Assumptions:
// Let:
- // min_vl = __riscv_v_min_vlen / 8
+ // min_vl = __riscv_v_min_vlen * LMUL / SEW
// We have:
// (avl > min_vl || vl == avl)
Value *Cond0 = Builder.CreateICmpULE(
- Ops[0], ConstantInt::get(ResultType, VScale->first * 8));
+ Ops[0], ConstantInt::get(ResultType, VLMAX));
BasicBlock *AssumptionBlock = createBasicBlock("assumption", this->CurFn);
BasicBlock *AssumptionEndBlock = createBasicBlock("assumption_end", this->CurFn);
@@ -744,24 +749,29 @@ let HasBuiltinAlias = false,
const TargetInfo &TI = getContext().getTargetInfo();
auto VScale = TI.getVScaleRange(getContext().getLangOpts());
+ uint64_t SEW = 1 << (cast<ConstantInt>(Ops[0])->getZExtValue() + 3);
+ uint64_t LMUL = cast<ConstantInt>(Ops[1])->getZExtValue();
+ bool Fractional = LMUL > 4;
+ uint64_t VLMAX = Fractional ? VScale->first * 64 / (1 << (8 - LMUL)) / SEW
+ : VScale->first * 64 * (1 << LMUL) / SEW;
Value *Assumption;
- if (VScale && VScale->first && VScale->first == VScale->second)
+ if (VScale->first && VScale->first == VScale->second)
// Assumptions:
// Let:
- // fixed_vl = __riscv_v_fixed_vlen / 8;
+ // fixed_vl = __riscv_v_fixed_vlen * LMUL / SEW
// We have:
// vlmax == fixed_vl
Assumption = Builder.CreateICmpEQ(
- VSetVL, llvm::ConstantInt::get(ResultType, VScale->first * 8));
+ VSetVL, llvm::ConstantInt::get(ResultType, VLMAX));
else
// Assumptions:
// Let:
- // min_vl = __riscv_v_min_vlen / 8
+ // min_vl = __riscv_v_min_vlen * LMUL / SEW
// We have:
// vlmax >= min_vl
Assumption = Builder.CreateICmpUGE(
- VSetVL, ConstantInt::get(ResultType, VScale->first * 8));
+ VSetVL, ConstantInt::get(ResultType, VLMAX));
Builder.CreateAssumption(Assumption);
return VSetVL;
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
index 42f465e33f6fda..a73d3b7b1925a5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvl.c
@@ -13,7 +13,7 @@
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -26,15 +26,15 @@
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -47,7 +47,7 @@ size_t test_vsetvl_e8mf8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -60,15 +60,15 @@ size_t test_vsetvl_e8mf8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -81,7 +81,7 @@ size_t test_vsetvl_e8mf4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -94,15 +94,15 @@ size_t test_vsetvl_e8mf4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -149,7 +149,7 @@ size_t test_vsetvl_e8m1(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -162,15 +162,15 @@ size_t test_vsetvl_e8m1(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 64
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -183,7 +183,7 @@ size_t test_vsetvl_e8m2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -196,15 +196,15 @@ size_t test_vsetvl_e8m2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 128
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -217,7 +217,7 @@ size_t test_vsetvl_e8m4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 128
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -230,15 +230,15 @@ size_t test_vsetvl_e8m4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 128
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 256
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 128
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -251,7 +251,7 @@ size_t test_vsetvl_e8m8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -264,15 +264,15 @@ size_t test_vsetvl_e8m8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -285,7 +285,7 @@ size_t test_vsetvl_e16mf4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -298,15 +298,15 @@ size_t test_vsetvl_e16mf4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -319,7 +319,7 @@ size_t test_vsetvl_e16mf2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -332,15 +332,15 @@ size_t test_vsetvl_e16mf2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -387,7 +387,7 @@ size_t test_vsetvl_e16m2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -400,15 +400,15 @@ size_t test_vsetvl_e16m2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 64
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -421,7 +421,7 @@ size_t test_vsetvl_e16m4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -434,15 +434,15 @@ size_t test_vsetvl_e16m4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 128
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -455,7 +455,7 @@ size_t test_vsetvl_e16m8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -468,15 +468,15 @@ size_t test_vsetvl_e16m8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -489,7 +489,7 @@ size_t test_vsetvl_e32mf2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -502,15 +502,15 @@ size_t test_vsetvl_e32mf2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -523,7 +523,7 @@ size_t test_vsetvl_e32m1(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -536,15 +536,15 @@ size_t test_vsetvl_e32m1(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -591,7 +591,7 @@ size_t test_vsetvl_e32m4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -604,15 +604,15 @@ size_t test_vsetvl_e32m4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 64
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -625,7 +625,7 @@ size_t test_vsetvl_e32m8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -638,15 +638,15 @@ size_t test_vsetvl_e32m8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -659,7 +659,7 @@ size_t test_vsetvl_e64m1(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -672,15 +672,15 @@ size_t test_vsetvl_e64m1(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -693,7 +693,7 @@ size_t test_vsetvl_e64m2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -706,15 +706,15 @@ size_t test_vsetvl_e64m2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
index fd6d091df69102..7d063ee799d21d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsetvlmax.c
@@ -14,7 +14,7 @@
// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -22,7 +22,7 @@
// CHECK-RV64-FIXED-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -34,7 +34,7 @@ size_t test_vsetvlmax_e8mf8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -42,7 +42,7 @@ size_t test_vsetvlmax_e8mf8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -54,7 +54,7 @@ size_t test_vsetvlmax_e8mf4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -62,7 +62,7 @@ size_t test_vsetvlmax_e8mf4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -94,7 +94,7 @@ size_t test_vsetvlmax_e8m1() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 32
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -102,7 +102,7 @@ size_t test_vsetvlmax_e8m1() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -114,7 +114,7 @@ size_t test_vsetvlmax_e8m2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 64
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -122,7 +122,7 @@ size_t test_vsetvlmax_e8m2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -134,7 +134,7 @@ size_t test_vsetvlmax_e8m4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 128
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -142,7 +142,7 @@ size_t test_vsetvlmax_e8m4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 128
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -154,7 +154,7 @@ size_t test_vsetvlmax_e8m8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -162,7 +162,7 @@ size_t test_vsetvlmax_e8m8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -174,7 +174,7 @@ size_t test_vsetvlmax_e16mf4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -182,7 +182,7 @@ size_t test_vsetvlmax_e16mf4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -194,7 +194,7 @@ size_t test_vsetvlmax_e16mf2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -202,7 +202,7 @@ size_t test_vsetvlmax_e16mf2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -234,7 +234,7 @@ size_t test_vsetvlmax_e16m2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 32
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -242,7 +242,7 @@ size_t test_vsetvlmax_e16m2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -254,7 +254,7 @@ size_t test_vsetvlmax_e16m4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 64
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -262,7 +262,7 @@ size_t test_vsetvlmax_e16m4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -274,7 +274,7 @@ size_t test_vsetvlmax_e16m8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -282,7 +282,7 @@ size_t test_vsetvlmax_e16m8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -294,7 +294,7 @@ size_t test_vsetvlmax_e32mf2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -302,7 +302,7 @@ size_t test_vsetvlmax_e32mf2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -314,7 +314,7 @@ size_t test_vsetvlmax_e32m1() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -322,7 +322,7 @@ size_t test_vsetvlmax_e32m1() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -354,7 +354,7 @@ size_t test_vsetvlmax_e32m4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 32
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -362,7 +362,7 @@ size_t test_vsetvlmax_e32m4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -374,7 +374,7 @@ size_t test_vsetvlmax_e32m8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -382,7 +382,7 @@ size_t test_vsetvlmax_e32m8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -394,7 +394,7 @@ size_t test_vsetvlmax_e64m1() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -402,7 +402,7 @@ size_t test_vsetvlmax_e64m1() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -414,7 +414,7 @@ size_t test_vsetvlmax_e64m2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -422,7 +422,7 @@ size_t test_vsetvlmax_e64m2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
index 42f465e33f6fda..a73d3b7b1925a5 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvl.c
@@ -13,7 +13,7 @@
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -26,15 +26,15 @@
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 5)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -47,7 +47,7 @@ size_t test_vsetvl_e8mf8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -60,15 +60,15 @@ size_t test_vsetvl_e8mf8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -81,7 +81,7 @@ size_t test_vsetvl_e8mf4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -94,15 +94,15 @@ size_t test_vsetvl_e8mf4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -149,7 +149,7 @@ size_t test_vsetvl_e8m1(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -162,15 +162,15 @@ size_t test_vsetvl_e8m1(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 64
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -183,7 +183,7 @@ size_t test_vsetvl_e8m2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -196,15 +196,15 @@ size_t test_vsetvl_e8m2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 128
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -217,7 +217,7 @@ size_t test_vsetvl_e8m4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 128
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -230,15 +230,15 @@ size_t test_vsetvl_e8m4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 0, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 128
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 256
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 128
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -251,7 +251,7 @@ size_t test_vsetvl_e8m8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -264,15 +264,15 @@ size_t test_vsetvl_e8m8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -285,7 +285,7 @@ size_t test_vsetvl_e16mf4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -298,15 +298,15 @@ size_t test_vsetvl_e16mf4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -319,7 +319,7 @@ size_t test_vsetvl_e16mf2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -332,15 +332,15 @@ size_t test_vsetvl_e16mf2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -387,7 +387,7 @@ size_t test_vsetvl_e16m2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -400,15 +400,15 @@ size_t test_vsetvl_e16m2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 64
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -421,7 +421,7 @@ size_t test_vsetvl_e16m4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -434,15 +434,15 @@ size_t test_vsetvl_e16m4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 1, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 64
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 128
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -455,7 +455,7 @@ size_t test_vsetvl_e16m8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -468,15 +468,15 @@ size_t test_vsetvl_e16m8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -489,7 +489,7 @@ size_t test_vsetvl_e32mf2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -502,15 +502,15 @@ size_t test_vsetvl_e32mf2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -523,7 +523,7 @@ size_t test_vsetvl_e32m1(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -536,15 +536,15 @@ size_t test_vsetvl_e32m1(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -591,7 +591,7 @@ size_t test_vsetvl_e32m4(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -604,15 +604,15 @@ size_t test_vsetvl_e32m4(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 2, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 32
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 64
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -625,7 +625,7 @@ size_t test_vsetvl_e32m8(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -638,15 +638,15 @@ size_t test_vsetvl_e32m8(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 2
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 4
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -659,7 +659,7 @@ size_t test_vsetvl_e64m1(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -672,15 +672,15 @@ size_t test_vsetvl_e64m1(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 4
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 8
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
@@ -693,7 +693,7 @@ size_t test_vsetvl_e64m2(size_t avl) {
// CHECK-RV64-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64: assumption:
// CHECK-RV64-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
@@ -706,15 +706,15 @@ size_t test_vsetvl_e64m2(size_t avl) {
// CHECK-RV64-FIXED-SAME: (i64 noundef [[AVL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 [[AVL]], i64 3, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp ule i64 [[AVL]], 8
// CHECK-RV64-FIXED-NEXT: br i1 [[TMP0]], label [[ASSUMPTION:%.*]], label [[ASSUMPTION_END:%.*]]
// CHECK-RV64-FIXED: assumption:
// CHECK-RV64-FIXED-NEXT: [[TMP1:%.*]] = icmp eq i64 [[VL]], [[AVL]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP1]])
// CHECK-RV64-FIXED-NEXT: br label [[ASSUMPTION_END]]
// CHECK-RV64-FIXED: assumption_end:
-// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 32
-// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP2:%.*]] = icmp ult i64 [[AVL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP3:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: [[TMP4:%.*]] = select i1 [[TMP2]], i1 true, i1 [[TMP3]]
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP4]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
index fd6d091df69102..7d063ee799d21d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsetvlmax.c
@@ -14,7 +14,7 @@
// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -22,7 +22,7 @@
// CHECK-RV64-FIXED-SAME: () #[[ATTR0:[0-9]+]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 5)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -34,7 +34,7 @@ size_t test_vsetvlmax_e8mf8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -42,7 +42,7 @@ size_t test_vsetvlmax_e8mf8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -54,7 +54,7 @@ size_t test_vsetvlmax_e8mf4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -62,7 +62,7 @@ size_t test_vsetvlmax_e8mf4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -94,7 +94,7 @@ size_t test_vsetvlmax_e8m1() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 32
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -102,7 +102,7 @@ size_t test_vsetvlmax_e8m1() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -114,7 +114,7 @@ size_t test_vsetvlmax_e8m2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 64
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -122,7 +122,7 @@ size_t test_vsetvlmax_e8m2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -134,7 +134,7 @@ size_t test_vsetvlmax_e8m4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 128
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -142,7 +142,7 @@ size_t test_vsetvlmax_e8m4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 0, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 128
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -154,7 +154,7 @@ size_t test_vsetvlmax_e8m8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -162,7 +162,7 @@ size_t test_vsetvlmax_e8m8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 6)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -174,7 +174,7 @@ size_t test_vsetvlmax_e16mf4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -182,7 +182,7 @@ size_t test_vsetvlmax_e16mf4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -194,7 +194,7 @@ size_t test_vsetvlmax_e16mf2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -202,7 +202,7 @@ size_t test_vsetvlmax_e16mf2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -234,7 +234,7 @@ size_t test_vsetvlmax_e16m2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 32
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -242,7 +242,7 @@ size_t test_vsetvlmax_e16m2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -254,7 +254,7 @@ size_t test_vsetvlmax_e16m4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 64
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -262,7 +262,7 @@ size_t test_vsetvlmax_e16m4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 64
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -274,7 +274,7 @@ size_t test_vsetvlmax_e16m8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -282,7 +282,7 @@ size_t test_vsetvlmax_e16m8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 7)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -294,7 +294,7 @@ size_t test_vsetvlmax_e32mf2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -302,7 +302,7 @@ size_t test_vsetvlmax_e32mf2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -314,7 +314,7 @@ size_t test_vsetvlmax_e32m1() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -322,7 +322,7 @@ size_t test_vsetvlmax_e32m1() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -354,7 +354,7 @@ size_t test_vsetvlmax_e32m4() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 32
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -362,7 +362,7 @@ size_t test_vsetvlmax_e32m4() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 2, i64 3)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 32
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -374,7 +374,7 @@ size_t test_vsetvlmax_e32m8() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 2
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -382,7 +382,7 @@ size_t test_vsetvlmax_e32m8() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 0)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 2
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -394,7 +394,7 @@ size_t test_vsetvlmax_e64m1() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 4
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -402,7 +402,7 @@ size_t test_vsetvlmax_e64m1() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 1)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 4
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
@@ -414,7 +414,7 @@ size_t test_vsetvlmax_e64m2() {
// CHECK-RV64-SAME: () #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
-// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 16
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = icmp uge i64 [[VL]], 8
// CHECK-RV64-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-NEXT: ret i64 [[VL]]
//
@@ -422,7 +422,7 @@ size_t test_vsetvlmax_e64m2() {
// CHECK-RV64-FIXED-SAME: () #[[ATTR0]] {
// CHECK-RV64-FIXED-NEXT: entry:
// CHECK-RV64-FIXED-NEXT: [[VL:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 3, i64 2)
-// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 16
+// CHECK-RV64-FIXED-NEXT: [[TMP0:%.*]] = icmp eq i64 [[VL]], 8
// CHECK-RV64-FIXED-NEXT: call void @llvm.assume(i1 [[TMP0]])
// CHECK-RV64-FIXED-NEXT: ret i64 [[VL]]
//
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